From patchwork Mon Jun 4 08:05:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Goel X-Patchwork-Id: 924879 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40znYZ4X3rz9s0W for ; Mon, 4 Jun 2018 18:05:38 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40znYZ2j7NzF0vb for ; Mon, 4 Jun 2018 18:05:38 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=huntbag@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40znYK3NCdzF0pD for ; Mon, 4 Jun 2018 18:05:21 +1000 (AEST) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w5483gDr089483 for ; Mon, 4 Jun 2018 04:05:19 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2jd0kyang3-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 04 Jun 2018 04:05:19 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 4 Jun 2018 09:05:14 +0100 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w5485D3727197682 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Jun 2018 08:05:13 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B5B94A404D; Mon, 4 Jun 2018 08:56:17 +0100 (BST) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B88B0A4040; Mon, 4 Jun 2018 08:56:16 +0100 (BST) Received: from fir03.in.ibm.com (unknown [9.124.102.72]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 4 Jun 2018 08:56:16 +0100 (BST) From: Abhishek Goel To: skiboot@lists.ozlabs.org Date: Mon, 4 Jun 2018 13:35:05 +0530 X-Mailer: git-send-email 2.14.1 X-TM-AS-GCONF: 00 x-cbid: 18060408-4275-0000-0000-000002895181 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18060408-4276-0000-0000-000037906509 Message-Id: <20180604080505.103996-1-huntbag@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-04_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=3 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1805220000 definitions=main-1806040101 Subject: [Skiboot] [PATCH v2] SLW: Provide cpuidle state description in device tree X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stewart@linux.vnet.ibm.com, ego@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch adds description for every cpuidle state and expose it through device tree. Up until now, name was being used for description as no description was provided for cpuidle states. The description for idle states in case of POWER can be printed using "cpupower monitor -l" or "cpupower idle-info". Signed-off-by: Abhishek Goel --- doc/device-tree/ibm,opal/power-mgt.rst | 5 ++++ hw/slw.c | 49 +++++++++++++++++++++++++++++----- 2 files changed, 48 insertions(+), 6 deletions(-) diff --git a/doc/device-tree/ibm,opal/power-mgt.rst b/doc/device-tree/ibm,opal/power-mgt.rst index b326a24b..598f8651 100644 --- a/doc/device-tree/ibm,opal/power-mgt.rst +++ b/doc/device-tree/ibm,opal/power-mgt.rst @@ -10,6 +10,10 @@ ibm,opal/power-mgt device tree entries All available CPU idle states are listed in ibm,cpu-idle-state-names +The description field for cpuidle states describes the impact of that +idle state. It describes about the power management steps taken to save +power in that idle state and also whether its impact is thread/core/quad +domain. For example: @@ -17,6 +21,7 @@ For example: power-mgt { ibm,cpu-idle-state-names = "nap", "fastsleep_", "winkle"; + ibm,cpu-idle-state-descs = "stop processor execution", "Core and L2 clock gating", "core and L3 power gating"; ibm,cpu-idle-state-residency-ns = <0x1 0x2 0x3>; ibm,cpu-idle-state-latencies-ns = <0x1 0x2 0x3>; }; diff --git a/hw/slw.c b/hw/slw.c index 49bcd839..b0f6955e 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -414,8 +414,10 @@ static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c) /* Define device-tree fields */ #define MAX_NAME_LEN 16 +#define MAX_DESC_LEN 60 struct cpu_idle_states { char name[MAX_NAME_LEN]; + char desc[MAX_DESC_LEN]; u32 latency_ns; u32 residency_ns; /* @@ -430,6 +432,7 @@ struct cpu_idle_states { static struct cpu_idle_states power7_cpu_idle_states[] = { { /* nap */ .name = "nap", + .desc = "stop processor execution", .latency_ns = 4000, .residency_ns = 100000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -448,6 +451,7 @@ static struct cpu_idle_states power7_cpu_idle_states[] = { static struct cpu_idle_states power8_cpu_idle_states[] = { { /* nap */ .name = "nap", + .desc = "stop processor execution", .latency_ns = 4000, .residency_ns = 100000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -461,6 +465,7 @@ static struct cpu_idle_states power8_cpu_idle_states[] = { .pm_ctrl_reg_mask = 0 }, { /* fast sleep (with workaround) */ .name = "fastsleep_", + .desc = "Core and L2 clock gating", .latency_ns = 40000, .residency_ns = 300000000, .flags = 1*OPAL_PM_DEC_STOP \ @@ -475,6 +480,7 @@ static struct cpu_idle_states power8_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_SLEEP_PMICR_MASK }, { /* Winkle */ .name = "winkle", + .desc = "core and L3 power gating", .latency_ns = 10000000, .residency_ns = 1000000000, /* Educated guess (not measured). * Winkle is not currently used by @@ -503,6 +509,7 @@ static struct cpu_idle_states power8_cpu_idle_states[] = { static struct cpu_idle_states power9_cpu_idle_states[] = { { .name = "stop0_lite", /* Enter stop0 with no state loss */ + .desc = "thread level stop instruction dispatch", .latency_ns = 1000, .residency_ns = 10000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -517,6 +524,7 @@ static struct cpu_idle_states power9_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, { .name = "stop0", + .desc = "low latency SMT switching", .latency_ns = 2000, .residency_ns = 20000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -536,6 +544,7 @@ static struct cpu_idle_states power9_cpu_idle_states[] = { { .name = "stop1", + .desc = "SMT switching with basic clock gating", .latency_ns = 5000, .residency_ns = 50000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -557,6 +566,7 @@ static struct cpu_idle_states power9_cpu_idle_states[] = { { .name = "stop2", + .desc = "core level clock gating", .latency_ns = 10000, .residency_ns = 100000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -573,6 +583,7 @@ static struct cpu_idle_states power9_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, { .name = "stop4", + .desc = "core level power gating", .latency_ns = 100000, .residency_ns = 10000000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -589,6 +600,7 @@ static struct cpu_idle_states power9_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, { .name = "stop5", + .desc = "core level power gating and turbo boost benefit", .latency_ns = 200000, .residency_ns = 20000000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -606,6 +618,7 @@ static struct cpu_idle_states power9_cpu_idle_states[] = { { .name = "stop8", + .desc = "core power gating and L2 clock gating", .latency_ns = 2000000, .residency_ns = 20000000, .flags = 1*OPAL_PM_DEC_STOP \ @@ -623,6 +636,7 @@ static struct cpu_idle_states power9_cpu_idle_states[] = { { .name = "stop11", + .desc = "quad level core and cache power gating", .latency_ns = 10000000, .residency_ns = 100000000, .flags = 1*OPAL_PM_DEC_STOP \ @@ -647,6 +661,7 @@ static struct cpu_idle_states power9_cpu_idle_states[] = { static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { { .name = "stop0", + .desc = "low latency SMT switching", .latency_ns = 2000, .residency_ns = 20000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -663,6 +678,7 @@ static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, { .name = "stop1", + .desc = "SMT switching with basic clock gating", .latency_ns = 5000, .residency_ns = 50000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -679,6 +695,7 @@ static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, { .name = "stop2", + .desc = "core level clock gating", .latency_ns = 10000, .residency_ns = 100000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -695,6 +712,7 @@ static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, { .name = "stop4", + .desc = "core level power gating", .latency_ns = 100000, .residency_ns = 1000000, .flags = 1*OPAL_PM_DEC_STOP \ @@ -712,6 +730,7 @@ static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { { .name = "stop8", + .desc = "core power gating and L2 clock gating", .latency_ns = 2000000, .residency_ns = 20000000, .flags = 1*OPAL_PM_DEC_STOP \ @@ -729,6 +748,7 @@ static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { { .name = "stop11", + .desc = "quad level core and cache power gating", .latency_ns = 10000000, .residency_ns = 100000000, .flags = 1*OPAL_PM_DEC_STOP \ @@ -750,6 +770,7 @@ static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { static struct cpu_idle_states power9_ndd1_cpu_idle_states[] = { { .name = "stop0_lite", + .desc = "thread level stop instruction dispatch", .latency_ns = 1000, .residency_ns = 10000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -764,6 +785,7 @@ static struct cpu_idle_states power9_ndd1_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, { .name = "stop1_lite", + .desc = "functional unit clock gating no SMT switching", .latency_ns = 4900, .residency_ns = 49000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -778,6 +800,7 @@ static struct cpu_idle_states power9_ndd1_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, { .name = "stop1", + .desc = "SMT switching with basic clock gating", .latency_ns = 2050000, .residency_ns = 50000, .flags = 0*OPAL_PM_DEC_STOP \ @@ -840,10 +863,12 @@ void add_cpu_idle_state_properties(void) /* Variables to track buffer length */ u8 name_buf_len; + u32 desc_buf_len; u8 num_supported_idle_states; /* Buffers to hold idle state properties */ char *name_buf, *alloced_name_buf; + char *desc_buf, *alloced_desc_buf; u32 *latency_ns_buf; u32 *residency_ns_buf; u32 *flags_buf; @@ -949,15 +974,18 @@ void add_cpu_idle_state_properties(void) */ /* Allocate memory to idle state property buffers. */ - alloced_name_buf= malloc(nr_states * sizeof(char) * MAX_NAME_LEN); + alloced_name_buf = malloc(nr_states * sizeof(char) * MAX_NAME_LEN); name_buf = alloced_name_buf; + alloced_desc_buf = malloc(nr_states * sizeof(char) * MAX_DESC_LEN); + desc_buf = alloced_desc_buf; latency_ns_buf = malloc(nr_states * sizeof(u32)); - residency_ns_buf= malloc(nr_states * sizeof(u32)); - flags_buf = malloc(nr_states * sizeof(u32)); - pm_ctrl_reg_val_buf = malloc(nr_states * sizeof(u64)); - pm_ctrl_reg_mask_buf = malloc(nr_states * sizeof(u64)); + residency_ns_buf = malloc(nr_states * sizeof(u32)); + flags_buf = malloc(nr_states * sizeof(u32)); + pm_ctrl_reg_val_buf = malloc(nr_states * sizeof(u64)); + pm_ctrl_reg_mask_buf = malloc(nr_states * sizeof(u64)); name_buf_len = 0; + desc_buf_len = 0; num_supported_idle_states = 0; /* @@ -1021,6 +1049,9 @@ void add_cpu_idle_state_properties(void) strncpy(name_buf, states[i].name, MAX_NAME_LEN); name_buf = name_buf + strlen(states[i].name) + 1; + strncpy(desc_buf, states[i].desc, MAX_DESC_LEN); + desc_buf = desc_buf + strlen(states[i].desc) + 1; + *latency_ns_buf = cpu_to_fdt32(states[i].latency_ns); latency_ns_buf++; @@ -1038,12 +1069,14 @@ void add_cpu_idle_state_properties(void) /* Increment buffer length trackers */ name_buf_len += strlen(states[i].name) + 1; + desc_buf_len += strlen(states[i].name) + 1; num_supported_idle_states++; } /* Point buffer pointers back to beginning of the buffer */ name_buf -= name_buf_len; + desc_buf -= desc_buf_len; latency_ns_buf -= num_supported_idle_states; residency_ns_buf -= num_supported_idle_states; flags_buf -= num_supported_idle_states; @@ -1051,7 +1084,9 @@ void add_cpu_idle_state_properties(void) pm_ctrl_reg_mask_buf -= num_supported_idle_states; /* Create dt properties with the buffer content */ dt_add_property(power_mgt, "ibm,cpu-idle-state-names", name_buf, - name_buf_len* sizeof(char)); + name_buf_len * sizeof(char)); + dt_add_property(power_mgt, "ibm,cpu-idle-state-descs", desc_buf, + desc_buf_len * sizeof(char)); dt_add_property(power_mgt, "ibm,cpu-idle-state-latencies-ns", latency_ns_buf, num_supported_idle_states * sizeof(u32)); dt_add_property(power_mgt, "ibm,cpu-idle-state-residency-ns", @@ -1075,7 +1110,9 @@ void add_cpu_idle_state_properties(void) num_supported_idle_states * sizeof(u64)); } assert(alloced_name_buf == name_buf); + assert(alloced_desc_buf == desc_buf); free(alloced_name_buf); + free(alloced_desc_buf); free(latency_ns_buf); free(residency_ns_buf); free(flags_buf);