From patchwork Sun Jun 3 22:36:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 924775 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ezQXOkyp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40zY0K0g7hz9ryk for ; Mon, 4 Jun 2018 08:39:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751713AbeFCWiX (ORCPT ); Sun, 3 Jun 2018 18:38:23 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:40609 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751674AbeFCWiV (ORCPT ); Sun, 3 Jun 2018 18:38:21 -0400 Received: by mail-lf0-f65.google.com with SMTP id q11-v6so22264698lfc.7; Sun, 03 Jun 2018 15:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Hu3xoZzDE4jadHfA9GevvF77MLBzA74lyZNPbkECnZE=; b=ezQXOkyp3Rhnvhfyvuo7mDF1TpOk7nQktcE7X0nyOsxRSZ2EC/1f7DKGcJxLHDcGfa 97ouHFNr6lpJktbmdLyask+z6uQfrZUH1pDzN7EOmLnt6hcJEH6/busOZcRTjadXB56o UGtoa5cer+WZqAVoPw28hfpr1JcDc31AslWdJuUUSWiaKOBhkPVgC79PzkAAL164TaU/ yIZWukQon2SLPHPCamgvn6u4+uNv9tVmvU3Phv7/yabULyQNGLQRwQgjpt+SsENypyJf yW/JMke9wktbfjLUWGsJJilUImmCMcw303GG1E11jcIHZi6SeCVB1apHKmO+lnFMF6L4 s9Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hu3xoZzDE4jadHfA9GevvF77MLBzA74lyZNPbkECnZE=; b=KZsiR7s/87gZFYhhIKWjU3njtxFKROMjWAvhDV/rdCN9/ozqgkIoyhzLVBYhkr6S4g XrkizpI/J4REzpedjBlg5jZXMnbypZuA6ChPwxY30ocf9mkH2qmRSv3xc/qODCVeoNB+ sKXAMco7/m9Y9ikM9QBqCEk0y/77dFKofQPg/jWkrnS6CWHRWWSGnzAbB61d7aMdbcHP df+5N+RlvX9PEoQGWbr6oOpkUxK44SON5UxN93w5B79rKAcBD1+G2+q/vCw8aWGOUpdf /nMiCqE+RDvK3pPPdp26pbAh75d2+4crILfDMBqwRFqxQp1oKimtQzKd5M3rHRPih0KT DQSA== X-Gm-Message-State: ALKqPwemdLjpcewreCTAUOSGxFCmPpCuD/4u1bkDaq3XTdbCC4f7iTNr VQk4q18iaV+ovaUF0yemZcg= X-Google-Smtp-Source: ADUXVKJVDiyK3j/A/FzFh+0rX30fPZO4aWseZh94+ng3TOXObMlVX0YS26Y7c0oREt1bb9XrrEk7Wg== X-Received: by 2002:a2e:2d0a:: with SMTP id t10-v6mr6542893ljt.50.1528065500044; Sun, 03 Jun 2018 15:38:20 -0700 (PDT) Received: from localhost.localdomain (109-252-91-41.nat.spd-mgts.ru. [109.252.91.41]) by smtp.gmail.com with ESMTPSA id a2-v6sm9344121ljd.18.2018.06.03.15.38.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Jun 2018 15:38:19 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] dt: bindings: tegra20-emc: Document interrupt property Date: Mon, 4 Jun 2018 01:36:50 +0300 Message-Id: <20180603223654.23324-2-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180603223654.23324-1-digetx@gmail.com> References: <20180603223654.23324-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org EMC has a dedicated interrupt that is used to notify about completion of HW operations. Document the interrupt property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index 4c33b29dc660..a6fe401d0d48 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -10,6 +10,7 @@ Properties: and chosen using the ramcode board selector. If omitted, only one set of tables can be present and said tables will be used irrespective of ram-code configuration. +- interrupts : Should contain EMC General interrupt. Child device nodes describe the memory settings for different configurations and clock rates. @@ -20,6 +21,7 @@ Example: #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; + interrupts = <0 78 0x04>; } From patchwork Sun Jun 3 22:36:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 924777 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f7C7JNVP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40zY0Y6lVzz9ryk for ; Mon, 4 Jun 2018 08:39:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751885AbeFCWjb (ORCPT ); Sun, 3 Jun 2018 18:39:31 -0400 Received: from mail-lf0-f67.google.com ([209.85.215.67]:39212 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751685AbeFCWiX (ORCPT ); Sun, 3 Jun 2018 18:38:23 -0400 Received: by mail-lf0-f67.google.com with SMTP id t134-v6so22252481lff.6; Sun, 03 Jun 2018 15:38:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=01PYMgEsBvVg7wtDu9tzcBp0PUsVPyFncK6O6mZm+O0=; b=f7C7JNVPTxPiPSr/rRxusJWWChUJRHS+YlRF3ZMrpKKGC8g0ErE7MXLogRnQ/sa30k l7vV/roUt5zYH8fexI4bZfO155pnVCs40HAB2I3kbhNDvde8Emx2kNU7i1hXBoQ8nJCe bCk1OntYRSXNDZi7HOtLAAinoM2CHoOqfuuTeCjA4J2PFTkYlw9qXDUrRFgX/PXtstTq oZA6gdDpLKJL3g7H8eJVuWK8ohwnT8WjFsDS2Zq2PNqYRxf+HEC1ixZr0aqOSIePUG98 UxdssSFvXaPS/C0ggwT0eWlStVWjfkUv92YKPIh8OAhFennx7NS7esQWeXIwcB6LhZYB S4fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=01PYMgEsBvVg7wtDu9tzcBp0PUsVPyFncK6O6mZm+O0=; b=nsmcugabZSis7Ro9HSd3rNCU0CiyMSyn5iwYSR0FKkWIL75bNYYcVKHpvlsv9MqL/A k3mIMUTDnc3WjiZXL0Rygq/TM5WQ9of0vLME4tkHTvx0dt4RL7oQolJfizcy4ABy8ZMs Z+YPB9SEFp/efJne3WXyAo+vjCNHPH8C7RBdJmAD1eqZE6Rqf4PUSBUIpzKVkXjdSDh4 CBCEp7kYwJjieyWPL7DMJ8QSjF4HrOL7MRnq/ADmcaAdj9XvY9MvT8ugghf7I+AeC1W7 VrdX0u4WX1pnhqfMBDcMrT7xOXB2u/ylh5P+5IeLZaRGX5hH672VxvaLOTm7mzuCLBUY QAGA== X-Gm-Message-State: ALKqPwdGjUUolR7uzDDknmCTVqiTLQXha2nIG1ljjNNE7GcjxGUbxulI FesZ0XydEhkI1A70pq1TS6o= X-Google-Smtp-Source: ADUXVKLjClbkE+XQRApxRy2VzhOn6UAi3TvivVsYpC7mrSQgdKsTOF1PTBjzyVP2OFUS8ZjETB6pcg== X-Received: by 2002:a2e:1b0a:: with SMTP id b10-v6mr13220330ljb.76.1528065501091; Sun, 03 Jun 2018 15:38:21 -0700 (PDT) Received: from localhost.localdomain (109-252-91-41.nat.spd-mgts.ru. [109.252.91.41]) by smtp.gmail.com with ESMTPSA id a2-v6sm9344121ljd.18.2018.06.03.15.38.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Jun 2018 15:38:20 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] ARM: dts: tegra20: Add interrupt to External Memory Controller Date: Mon, 4 Jun 2018 01:36:51 +0300 Message-Id: <20180603223654.23324-3-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180603223654.23324-1-digetx@gmail.com> References: <20180603223654.23324-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add interrupt entry into the EMC DT node. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 983dd5c14794..3cd3cb28cfd9 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -609,6 +609,7 @@ memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; }; From patchwork Sun Jun 3 22:36:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 924772 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CIVxkuYc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40zXzg2l5dz9ryk for ; Mon, 4 Jun 2018 08:38:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751795AbeFCWia (ORCPT ); Sun, 3 Jun 2018 18:38:30 -0400 Received: from mail-lf0-f67.google.com ([209.85.215.67]:33885 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751706AbeFCWiY (ORCPT ); Sun, 3 Jun 2018 18:38:24 -0400 Received: by mail-lf0-f67.google.com with SMTP id o9-v6so22254297lfk.1; Sun, 03 Jun 2018 15:38:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ASM6UGc3tjWV8yR28zPoHohRmblqfCz+RGQZb6C2Rps=; b=CIVxkuYcofwM+e6PT/Fgn39z3I4soS1O5Tlwq9CHyxbAzlUa3raHmEcKSDEUklo4+T 4PTDBZLPCaIo4C73vMcuEwMwGhkLbEfpbuEMJpJ6Q5xoViHnBi+FHg/xgqdJ4bvcSuqp t7N9It5dTyrrtq8vg4BwJ80M25+mUJgsUqZCm9+mag3KKDqSQeP/ilWf2aHvz1c3XyJI UqKrJ+dPispwp3jXlYO2lKJYSHLDLX0SWilqdFc56wUdpynM9XB7ZmUoXZjfwdD1HUk7 ZbfKGaFTosJUPBvs01Fg4ztbjq4Z36lTL07tOOEQ0EnQF7CTI02QotBLZlWM/vHcRFpC npGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ASM6UGc3tjWV8yR28zPoHohRmblqfCz+RGQZb6C2Rps=; b=aBsG1UpRTX4JThgG/EkY1icj0g2rbM9/ZxS/8NnvibehC9Rv63VcRMMPfrPaLWws4d qWg30Uo22J+a0q60GFT11yEj9QK9uickQJLqYkx1nHo7Vb82zIjn8/+Coy3wqWwsqln/ c5MMpmZNxsfaqhvUTueCTgrzbkBBTqfJMvh66oqJ9QVMVBzrn9rinxR+VwMIpw91M9UN 4+/e11x5AVz/wot0aqk+4rHRbG0HsOWlMgRYtrkkH7pZm4WbUpKCbIw6fh3wRPmA/Pde fhGmkte6FzGNqdXkCYibGOxzv4GIo+H9WyygW+7HjJQyyB57qaNxgZ6T8PfzfOmD+glY p+XA== X-Gm-Message-State: ALKqPwdwhxnf+ApjjEd2zHzVR1Mme7PkVt8JhcCqCtQcGV3jobkbj1dM n28ydEZoAFOQBHSIron2UMM= X-Google-Smtp-Source: ADUXVKIaD1x4E+bdXifbabUuCoYIy5SZKAlpvDu5zodrctJQ11ehu+iy9B5rh50R/wjwPqH0arjmzg== X-Received: by 2002:a2e:7113:: with SMTP id m19-v6mr14106978ljc.44.1528065502129; Sun, 03 Jun 2018 15:38:22 -0700 (PDT) Received: from localhost.localdomain (109-252-91-41.nat.spd-mgts.ru. [109.252.91.41]) by smtp.gmail.com with ESMTPSA id a2-v6sm9344121ljd.18.2018.06.03.15.38.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Jun 2018 15:38:21 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] clk: tegra20: Turn EMC clock gate into divider Date: Mon, 4 Jun 2018 01:36:52 +0300 Message-Id: <20180603223654.23324-4-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180603223654.23324-1-digetx@gmail.com> References: <20180603223654.23324-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Kernel should never gate the EMC clock as it causes immediate lockup, so removing clk-gate functionality doesn't affect anything. Turning EMC clk gate into divider allows to implement glitch-less EMC scaling, avoiding reparenting to a backup clock. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 36 ++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index cc857d4d4a86..2bd35418716a 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -578,7 +578,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true }, [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true }, [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true }, - [tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true }, }; static unsigned long tegra20_clk_measure_input_freq(void) @@ -799,6 +798,31 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), }; +static void __init tegra20_emc_clk_init(void) +{ + struct clk *clk; + + clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, + ARRAY_SIZE(mux_pllmcp_clkm), + CLK_SET_RATE_NO_REPARENT, + clk_base + CLK_SOURCE_EMC, + 30, 2, 0, &emc_lock); + + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, + &emc_lock); + clks[TEGRA20_CLK_MC] = clk; + + /* + * Note that 'emc_mux' source and 'emc' rate shouldn't be changed at + * the same time due to a HW bug, this won't happen because we're + * defining 'emc_mux' and 'emc' as a distinct clocks. + */ + clk = clk_register_divider(NULL, "emc", "emc_mux", CLK_IS_CRITICAL, + clk_base + CLK_SOURCE_EMC, 0, 7, + 0, &emc_lock); + clks[TEGRA20_CLK_EMC] = clk; +} + static void __init tegra20_periph_clk_init(void) { struct tegra_periph_init_data *data; @@ -812,15 +836,7 @@ static void __init tegra20_periph_clk_init(void) clks[TEGRA20_CLK_AC97] = clk; /* emc */ - clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, - ARRAY_SIZE(mux_pllmcp_clkm), - CLK_SET_RATE_NO_REPARENT, - clk_base + CLK_SOURCE_EMC, - 30, 2, 0, &emc_lock); - - clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, - &emc_lock); - clks[TEGRA20_CLK_MC] = clk; + tegra20_emc_clk_init(); /* dsi */ clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, From patchwork Sun Jun 3 22:36:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 924771 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fBqYYU49"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40zXzB4cgrz9s02 for ; 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[109.252.91.41]) by smtp.gmail.com with ESMTPSA id a2-v6sm9344121ljd.18.2018.06.03.15.38.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Jun 2018 15:38:22 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC Date: Mon, 4 Jun 2018 01:36:53 +0300 Message-Id: <20180603223654.23324-5-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180603223654.23324-1-digetx@gmail.com> References: <20180603223654.23324-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Ensure that direct PLLM sourcing is turned off for EMC as we don't support that configuration in the clk driver. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 2bd35418716a..ca4eadb9520e 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -800,7 +800,9 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra20_emc_clk_init(void) { + const u32 use_pllm_ud = BIT(29); struct clk *clk; + u32 emc_reg; clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, ARRAY_SIZE(mux_pllmcp_clkm), @@ -812,6 +814,14 @@ static void __init tegra20_emc_clk_init(void) &emc_lock); clks[TEGRA20_CLK_MC] = clk; + /* un-divided pll_m_out0 is currently unsupported */ + emc_reg = readl_relaxed(clk_base + CLK_SOURCE_EMC); + if (emc_reg & use_pllm_ud) { + pr_err("%s: un-divided PllM_out0 used as clock source\n", + __func__); + return; + } + /* * Note that 'emc_mux' source and 'emc' rate shouldn't be changed at * the same time due to a HW bug, this won't happen because we're From patchwork Sun Jun 3 22:36:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 924773 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="in0JhLGy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40zY083L9Jz9ryk for ; Mon, 4 Jun 2018 08:39:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751840AbeFCWjG (ORCPT ); Sun, 3 Jun 2018 18:39:06 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:44564 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751758AbeFCWi0 (ORCPT ); Sun, 3 Jun 2018 18:38:26 -0400 Received: by mail-lf0-f65.google.com with SMTP id 36-v6so20317432lfr.11; Sun, 03 Jun 2018 15:38:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=czAOYjK0NeSZtbQMvLMkVe+JGQYA3yzHnxRjnIaKKh0=; b=in0JhLGyUumXjSXP9D3WuT937GjV2uqkoncjlvuK8hdunVsOECpOJHvVEOYeJ1WdMq ZidQjwMSdBRoII5UkhHtJgHcHdJHR6ekoXN4jGz1el3vOwiImqBx4HUoBjlDavLjhBMK jaL9yeLVdho8AXE64pUc1HBGsCDR6JStKnSKQ73kCblXjIwomdn6urEhDffiEBsq1Ytw zQqwtGIhF9g3fu9IGQjdM1yeBo4ItgOMWYlWVTFqytewJR8+te027Hwen0WOzbFCS+0P LCauP7p4ZdDaHECO6XTyxQijvh4Lc/u2odKdOyK8Wv4jsxKGM092iK3zxJA4QiFXQCUP DipA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=czAOYjK0NeSZtbQMvLMkVe+JGQYA3yzHnxRjnIaKKh0=; b=AcdZMXsu342t1W2AXkhiaPNVSJunOcC4CIC/Np+rDucCp8ZMTicnJd7WBKYpe/O6cE ev7Krzc64HP2djuP9MRIRx161sCRkH1NqfulgPaGYkqwPfaV3LPPNEedTe5b5VJ1Dtdy /SskQvKoqEVVvi1tABQKQdVcShox+gkPGCyunLaiqZC+tAHMt/rdb9qK+OBN7cJUKcpz 9/KAKFHc1+G3qqHN1WH6Wrns0dXCCrsKeFsILcReCWRfqOe/JjAvveGYwfurpxX+9UZP QLIpmXBwPVAfRbtmMqfPSSHpcUDeF5Iz0CC6qvVUmiyiQCZ3++MSWybylJt6bxduRMZV mKzA== X-Gm-Message-State: ALKqPwebBuThxGW64vCuktIZDWcvaFQx3iXVbRmpAzLsCGKunQQjjW/p KEIiQRfvbVcvU/V5R8LCyV4= X-Google-Smtp-Source: ADUXVKKQ7XkU6jG+nqCh/w3oPnXOrwRuxiz3R8juCQ/QU3sVAJmUAvyd2ltgdKqf9P6Wh5XZnJX5rA== X-Received: by 2002:a2e:44c6:: with SMTP id b67-v6mr7179113ljf.120.1528065504278; Sun, 03 Jun 2018 15:38:24 -0700 (PDT) Received: from localhost.localdomain (109-252-91-41.nat.spd-mgts.ru. [109.252.91.41]) by smtp.gmail.com with ESMTPSA id a2-v6sm9344121ljd.18.2018.06.03.15.38.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Jun 2018 15:38:23 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] memory: tegra: Introduce Tegra20 EMC driver Date: Mon, 4 Jun 2018 01:36:54 +0300 Message-Id: <20180603223654.23324-6-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180603223654.23324-1-digetx@gmail.com> References: <20180603223654.23324-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Introduce driver for the External Memory Controller (EMC) found on Tegra20 chips, which controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/tegra20-emc.c | 586 +++++++++++++++++++++++++++++ 3 files changed, 597 insertions(+) create mode 100644 drivers/memory/tegra/tegra20-emc.c diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 6d74e499e18d..34e0b70f5c5f 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -6,6 +6,16 @@ config TEGRA_MC This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. +config TEGRA20_EMC + bool "NVIDIA Tegra20 External Memory Controller driver" + default y + depends on ARCH_TEGRA_2x_SOC + help + This driver is for the External Memory Controller (EMC) found on + Tegra20 chips. The EMC controls the external DRAM on the board. + This driver is required to change memory timings / clock rate for + external memory. + config TEGRA124_EMC bool "NVIDIA Tegra124 External Memory Controller driver" default y diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 94ab16ba075b..3971a6b7c487 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -10,5 +10,6 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o +obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c new file mode 100644 index 000000000000..26a18b5e7941 --- /dev/null +++ b/drivers/memory/tegra/tegra20-emc.c @@ -0,0 +1,586 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tegra20 External Memory Controller driver + * + * Author: Dmitry Osipenko + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EMC_INTSTATUS 0x000 +#define EMC_INTMASK 0x004 +#define EMC_TIMING_CONTROL 0x028 +#define EMC_RC 0x02c +#define EMC_RFC 0x030 +#define EMC_RAS 0x034 +#define EMC_RP 0x038 +#define EMC_R2W 0x03c +#define EMC_W2R 0x040 +#define EMC_R2P 0x044 +#define EMC_W2P 0x048 +#define EMC_RD_RCD 0x04c +#define EMC_WR_RCD 0x050 +#define EMC_RRD 0x054 +#define EMC_REXT 0x058 +#define EMC_WDV 0x05c +#define EMC_QUSE 0x060 +#define EMC_QRST 0x064 +#define EMC_QSAFE 0x068 +#define EMC_RDV 0x06c +#define EMC_REFRESH 0x070 +#define EMC_BURST_REFRESH_NUM 0x074 +#define EMC_PDEX2WR 0x078 +#define EMC_PDEX2RD 0x07c +#define EMC_PCHG2PDEN 0x080 +#define EMC_ACT2PDEN 0x084 +#define EMC_AR2PDEN 0x088 +#define EMC_RW2PDEN 0x08c +#define EMC_TXSR 0x090 +#define EMC_TCKE 0x094 +#define EMC_TFAW 0x098 +#define EMC_TRPAB 0x09c +#define EMC_TCLKSTABLE 0x0a0 +#define EMC_TCLKSTOP 0x0a4 +#define EMC_TREFBW 0x0a8 +#define EMC_QUSE_EXTRA 0x0ac +#define EMC_ODT_WRITE 0x0b0 +#define EMC_ODT_READ 0x0b4 +#define EMC_FBIO_CFG5 0x104 +#define EMC_FBIO_CFG6 0x114 +#define EMC_AUTO_CAL_INTERVAL 0x2a8 +#define EMC_CFG_2 0x2b8 +#define EMC_CFG_DIG_DLL 0x2bc +#define EMC_DLL_XFORM_DQS 0x2c0 +#define EMC_DLL_XFORM_QUSE 0x2c4 +#define EMC_ZCAL_REF_CNT 0x2e0 +#define EMC_ZCAL_WAIT_CNT 0x2e4 +#define EMC_CFG_CLKTRIM_0 0x2d0 +#define EMC_CFG_CLKTRIM_1 0x2d4 +#define EMC_CFG_CLKTRIM_2 0x2d8 + +#define EMC_CLKCHANGE_REQ_ENABLE BIT(0) +#define EMC_CLKCHANGE_PD_ENABLE BIT(1) +#define EMC_CLKCHANGE_SR_ENABLE BIT(2) + +#define EMC_TIMING_UPDATE BIT(0) + +#define EMC_CLKCHANGE_COMPLETE_INT BIT(4) + +static const unsigned long emc_timing_registers[] = { + EMC_RC, + EMC_RFC, + EMC_RAS, + EMC_RP, + EMC_R2W, + EMC_W2R, + EMC_R2P, + EMC_W2P, + EMC_RD_RCD, + EMC_WR_RCD, + EMC_RRD, + EMC_REXT, + EMC_WDV, + EMC_QUSE, + EMC_QRST, + EMC_QSAFE, + EMC_RDV, + EMC_REFRESH, + EMC_BURST_REFRESH_NUM, + EMC_PDEX2WR, + EMC_PDEX2RD, + EMC_PCHG2PDEN, + EMC_ACT2PDEN, + EMC_AR2PDEN, + EMC_RW2PDEN, + EMC_TXSR, + EMC_TCKE, + EMC_TFAW, + EMC_TRPAB, + EMC_TCLKSTABLE, + EMC_TCLKSTOP, + EMC_TREFBW, + EMC_QUSE_EXTRA, + EMC_FBIO_CFG6, + EMC_ODT_WRITE, + EMC_ODT_READ, + EMC_FBIO_CFG5, + EMC_CFG_DIG_DLL, + EMC_DLL_XFORM_DQS, + EMC_DLL_XFORM_QUSE, + EMC_ZCAL_REF_CNT, + EMC_ZCAL_WAIT_CNT, + EMC_AUTO_CAL_INTERVAL, + EMC_CFG_CLKTRIM_0, + EMC_CFG_CLKTRIM_1, + EMC_CFG_CLKTRIM_2, +}; + +struct emc_timing { + unsigned long rate; + u32 emc_registers_data[ARRAY_SIZE(emc_timing_registers)]; +}; + +struct tegra_emc { + struct device *dev; + struct notifier_block clk_nb; + struct clk *backup_clk; + struct clk *emc_mux; + struct clk *pll_m; + struct clk *clk; + void __iomem *regs; + + struct completion clk_handshake_complete; + int irq; + + struct emc_timing *timings; + unsigned int num_timings; +}; + +static irqreturn_t tegra_emc_isr(int irq, void *data) +{ + struct tegra_emc *emc = data; + u32 intmask = EMC_CLKCHANGE_COMPLETE_INT; + u32 status; + + status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; + if (!status) + return IRQ_NONE; + + /* clear interrupts */ + writel_relaxed(status, emc->regs + EMC_INTSTATUS); + + /* notify about EMC-CAR handshake completion */ + complete(&emc->clk_handshake_complete); + + return IRQ_HANDLED; +} + +static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, + unsigned long rate) +{ + struct emc_timing *timing = NULL; + unsigned int i; + + for (i = 0; i < emc->num_timings; i++) { + if (emc->timings[i].rate >= rate) { + timing = &emc->timings[i]; + break; + } + } + + if (!timing) { + dev_err(emc->dev, "no timing for rate %lu\n", rate); + return NULL; + } + + return timing; +} + +static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) +{ + struct emc_timing *timing = tegra_emc_find_timing(emc, rate); + unsigned int i; + + if (!timing) + return -ENOENT; + + dev_dbg(emc->dev, "%s: timing rate %lu emc rate %lu\n", + __func__, timing->rate, rate); + + /* program shadow registers */ + for (i = 0; i < ARRAY_SIZE(timing->emc_registers_data); i++) + writel_relaxed(timing->emc_registers_data[i], + emc->regs + emc_timing_registers[i]); + + /* wait until programming has settled */ + readl_relaxed(emc->regs + emc_timing_registers[0]); + + if (emc->irq < 0) + writel_relaxed(EMC_CLKCHANGE_COMPLETE_INT, + emc->regs + EMC_INTMASK); + else + reinit_completion(&emc->clk_handshake_complete); + + return 0; +} + +static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) +{ + long timeout; + u32 value; + int err; + + dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); + + if (flush) { + /* manually initiate memory timing update */ + writel_relaxed(EMC_TIMING_UPDATE, + emc->regs + EMC_TIMING_CONTROL); + return 0; + } + + if (emc->irq < 0) { + /* poll interrupt status if IRQ isn't available */ + err = readl_relaxed_poll_timeout(emc->regs + EMC_INTSTATUS, + value, value & EMC_CLKCHANGE_COMPLETE_INT, + 1, 100); + if (err) { + dev_err(emc->dev, "EMC-CAR handshake failed\n"); + return -EIO; + } + + return 0; + } + + timeout = wait_for_completion_timeout(&emc->clk_handshake_complete, + usecs_to_jiffies(100)); + if (timeout == 0) { + dev_err(emc->dev, "EMC handshake failed\n"); + return -EIO; + } else if (timeout < 0) { + dev_err(emc->dev, "failed to wait for EMC-CAR handshake: %ld\n", + timeout); + return timeout; + } + + return 0; +} + +static int load_one_timing_from_dt(struct tegra_emc *emc, + struct emc_timing *timing, + struct device_node *node) +{ + u32 rate; + int err; + + if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { + dev_err(emc->dev, "incompatible DT node \"%s\"\n", + node->name); + return -EINVAL; + } + + err = of_property_read_u32(node, "clock-frequency", &rate); + if (err) { + dev_err(emc->dev, "timing %s: failed to read rate: %d\n", + node->name, err); + return err; + } + + err = of_property_read_u32_array(node, "nvidia,emc-registers", + timing->emc_registers_data, + ARRAY_SIZE(emc_timing_registers)); + if (err) { + dev_err(emc->dev, + "timing %s: failed to read emc timing data: %d\n", + node->name, err); + return err; + } + + /* + * The EMC clock rate is twice the bus rate, and the bus rate is + * measured in kHz. + */ + timing->rate = rate * 2 * 1000; + + dev_dbg(emc->dev, "%s: emc rate %ld\n", __func__, timing->rate); + + return 0; +} + +static int cmp_timings(const void *_a, const void *_b) +{ + const struct emc_timing *a = _a; + const struct emc_timing *b = _b; + + if (a->rate < b->rate) + return -1; + else if (a->rate == b->rate) + return 0; + else + return 1; +} + +static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, + struct device_node *node) +{ + struct device_node *child; + struct emc_timing *timing; + int child_count; + int err; + + child_count = of_get_child_count(node); + if (!child_count) { + dev_err(emc->dev, "no memory timings in DT node\n"); + return -ENOENT; + } + + emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), + GFP_KERNEL); + if (!emc->timings) + return -ENOMEM; + + emc->num_timings = child_count; + timing = emc->timings; + + for_each_child_of_node(node, child) { + err = load_one_timing_from_dt(emc, timing++, child); + if (err) { + of_node_put(child); + return err; + } + } + + sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, + NULL); + + return 0; +} + +static struct device_node * +tegra_emc_find_node_by_ram_code(struct tegra_emc *emc, u32 ram_code) +{ + struct device_node *np; + int err; + + for_each_child_of_node(emc->dev->of_node, np) { + u32 value; + + err = of_property_read_u32(np, "nvidia,ram-code", &value); + if (err || value != ram_code) + continue; + + return np; + } + + dev_info(emc->dev, "no memory timings for RAM code %u found in DT\n", + ram_code); + + return NULL; +} + +static int tegra_emc_clk_change_notify(struct notifier_block *nb, + unsigned long msg, void *data) +{ + struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); + struct clk_notifier_data *cnd = data; + int err; + + switch (msg) { + case PRE_RATE_CHANGE: + err = emc_prepare_timing_change(emc, cnd->new_rate); + break; + + case ABORT_RATE_CHANGE: + err = emc_prepare_timing_change(emc, cnd->old_rate); + if (err) + break; + + err = emc_complete_timing_change(emc, true); + break; + + case POST_RATE_CHANGE: + err = emc_complete_timing_change(emc, false); + break; + + default: + return NOTIFY_DONE; + } + + return notifier_from_errno(err); +} + +static int emc_setup_hw(struct tegra_emc *emc) +{ + u32 emc_cfg; + + emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); + + /* + * Depending on a memory type, DRAM should enter either self-refresh + * or power-down state on EMC clock change. + */ + if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && + !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) + { + dev_err(emc->dev, + "bootloader didn't specify DRAM auto-suspend mode\n"); + return -EINVAL; + } + + /* allow EMC and CAR to handshake on PLL divider/source changes */ + emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; + writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); + + /* initialize interrupt */ + writel_relaxed(EMC_CLKCHANGE_COMPLETE_INT, emc->regs + EMC_INTMASK); + writel_relaxed(EMC_CLKCHANGE_COMPLETE_INT, emc->regs + EMC_INTSTATUS); + + return 0; +} + +static int emc_init(struct tegra_emc *emc, unsigned long rate) +{ + int err; + + err = clk_set_parent(emc->emc_mux, emc->backup_clk); + if (err) { + dev_err(emc->dev, + "failed to reparent to backup source: %d\n", err); + return err; + } + + err = clk_set_rate(emc->pll_m, rate); + if (err) + dev_err(emc->dev, + "failed to change pll_m rate: %d\n", err); + + err = clk_set_parent(emc->emc_mux, emc->pll_m); + if (err) { + dev_err(emc->dev, + "failed to reparent to pll_m: %d\n", err); + return err; + } + + return 0; +} + +static int tegra_emc_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct tegra_emc *emc; + struct resource *res; + u32 ram_code; + int err; + + emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); + if (!emc) + return -ENOMEM; + + emc->dev = &pdev->dev; + + ram_code = tegra_read_ram_code(); + + np = tegra_emc_find_node_by_ram_code(emc, ram_code); + if (!np) + return -ENOENT; + + err = tegra_emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + emc->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(emc->regs)) + return PTR_ERR(emc->regs); + + err = emc_setup_hw(emc); + if (err) + return err; + + emc->irq = platform_get_irq(pdev, 0); + if (emc->irq < 0) { + dev_warn(&pdev->dev, "interrupt not specified\n"); + dev_warn(&pdev->dev, "continuing, but please update your DT\n"); + } else { + init_completion(&emc->clk_handshake_complete); + + err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0, + dev_name(&pdev->dev), emc); + if (err < 0) { + dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", + emc->irq, err); + return err; + } + } + + emc->pll_m = clk_get_sys(NULL, "pll_m"); + if (IS_ERR(emc->pll_m)) { + err = PTR_ERR(emc->pll_m); + dev_err(&pdev->dev, "failed to get pll_m: %d\n", err); + return err; + } + + emc->backup_clk = clk_get_sys(NULL, "pll_p"); + if (IS_ERR(emc->backup_clk)) { + err = PTR_ERR(emc->backup_clk); + dev_err(&pdev->dev, "failed to get pll_p: %d\n", err); + goto put_pll_m; + } + + emc->clk = clk_get_sys(NULL, "emc"); + if (IS_ERR(emc->clk)) { + err = PTR_ERR(emc->clk); + dev_err(&pdev->dev, "failed to get emc: %d\n", err); + goto put_backup; + } + + emc->emc_mux = clk_get_parent(emc->clk); + if (IS_ERR(emc->emc_mux)) { + err = PTR_ERR(emc->emc_mux); + dev_err(&pdev->dev, "failed to get emc_mux: %d\n", err); + goto put_emc; + } + + emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; + + err = clk_notifier_register(emc->clk, &emc->clk_nb); + if (err) { + dev_err(&pdev->dev, "failed to register clk notifier: %d\n", + err); + goto put_emc; + } + + /* set DRAM clock rate to maximum */ + err = emc_init(emc, emc->timings[emc->num_timings - 1].rate); + if (err) { + dev_err(&pdev->dev, "failed to initialize clk rate: %d\n", + err); + goto unreg_notifier; + } + + return 0; + +unreg_notifier: + clk_notifier_unregister(emc->emc_mux, &emc->clk_nb); +put_emc: + clk_put(emc->clk); +put_backup: + clk_put(emc->backup_clk); +put_pll_m: + clk_put(emc->pll_m); + + return err; +} + +static const struct of_device_id tegra_emc_of_match[] = { + { .compatible = "nvidia,tegra20-emc", }, + {}, +}; + +static struct platform_driver tegra_emc_driver = { + .probe = tegra_emc_probe, + .driver = { + .name = "tegra20-emc", + .of_match_table = tegra_emc_of_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init tegra_emc_init(void) +{ + return platform_driver_register(&tegra_emc_driver); +} +subsys_initcall(tegra_emc_init);