From patchwork Sat Jun 2 09:11:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 924446 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40yb7521qcz9s08 for ; Sat, 2 Jun 2018 19:12:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750869AbeFBJL7 (ORCPT ); Sat, 2 Jun 2018 05:11:59 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17149 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750821AbeFBJL6 (ORCPT ); Sat, 2 Jun 2018 05:11:58 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Sat, 02 Jun 2018 02:12:11 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sat, 02 Jun 2018 02:12:02 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sat, 02 Jun 2018 02:12:02 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Sat, 2 Jun 2018 09:11:57 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Sat, 2 Jun 2018 09:11:57 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Sat, 2 Jun 2018 09:11:57 +0000 Received: from vbhadram.nvidia.com (Not Verified[10.19.65.141]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 02 Jun 2018 02:11:57 -0700 From: Bhadram Varka To: , , , , , CC: , , Subject: [PATCH] arm64: tegra: Remove unused interrupt properties Date: Sat, 2 Jun 2018 14:41:51 +0530 Message-ID: <1527930713-4479-1-git-send-email-vbhadram@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org DWC EQOS on Tegra handles all interrupts through common interrupt line. So lets remove unused power and per-channel interrupt properties. Signed-off-by: Bhadram Varka --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b762227..252133b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -41,16 +41,7 @@ compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; reg = <0x0 0x02490000 0x0 0x10000>; - interrupts = , /* common */ - , /* power */ - , /* rx0 */ - , /* tx0 */ - , /* rx1 */ - , /* tx1 */ - , /* rx2 */ - , /* tx2 */ - , /* rx3 */ - ; /* tx3 */ + interrupts = ; /* common */ clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, <&bpmp TEGRA186_CLK_EQOS_AXI>, <&bpmp TEGRA186_CLK_EQOS_RX>, From patchwork Sat Jun 2 09:11:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 924447 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40yb772GMgz9ry1 for ; Sat, 2 Jun 2018 19:12:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750952AbeFBJMC (ORCPT ); Sat, 2 Jun 2018 05:12:02 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7792 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750892AbeFBJMB (ORCPT ); Sat, 2 Jun 2018 05:12:01 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Sat, 02 Jun 2018 02:12:10 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sat, 02 Jun 2018 02:12:05 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sat, 02 Jun 2018 02:12:05 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Sat, 2 Jun 2018 09:11:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Sat, 2 Jun 2018 09:11:59 +0000 Received: from vbhadram.nvidia.com (Not Verified[10.19.65.141]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 02 Jun 2018 02:11:59 -0700 From: Bhadram Varka To: , , , , , CC: , , Subject: [PATCH 2/3] arm64: tegra: Enable multi-queue for DWC EQOS Date: Sat, 2 Jun 2018 14:41:52 +0530 Message-ID: <1527930713-4479-2-git-send-email-vbhadram@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527930713-4479-1-git-send-email-vbhadram@nvidia.com> References: <1527930713-4479-1-git-send-email-vbhadram@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org DWC EQOS supports four MTL queues for Tx and Rx separately. Signed-off-by: Bhadram Varka --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 0f4bed8..f27730d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -37,6 +37,52 @@ gpio-controller; }; + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,priority = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,priority = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,priority = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,priority = <0x3>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; + ethernet@2490000 { compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; @@ -57,6 +103,8 @@ snps,burst-map = <0x7>; snps,txpbl = <32>; snps,rxpbl = <8>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; }; memory-controller@2c00000 { From patchwork Sat Jun 2 09:11:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 924448 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40yb793NPFz9ry1 for ; Sat, 2 Jun 2018 19:12:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751297AbeFBJME (ORCPT ); Sat, 2 Jun 2018 05:12:04 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11453 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750964AbeFBJMD (ORCPT ); Sat, 2 Jun 2018 05:12:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Sat, 02 Jun 2018 02:11:59 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 02 Jun 2018 02:12:03 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 02 Jun 2018 02:12:03 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Sat, 2 Jun 2018 09:12:02 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Sat, 2 Jun 2018 09:12:02 +0000 Received: from vbhadram.nvidia.com (Not Verified[10.19.65.141]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 02 Jun 2018 02:12:02 -0700 From: Bhadram Varka To: , , , , , CC: , , Subject: [PATCH 3/3] arm64: tegra: Configure DWC EQOS TxPBL for multi-queue Date: Sat, 2 Jun 2018 14:41:53 +0530 Message-ID: <1527930713-4479-3-git-send-email-vbhadram@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527930713-4479-1-git-send-email-vbhadram@nvidia.com> References: <1527930713-4479-1-git-send-email-vbhadram@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PBL should be limited to half of the Queue size. For multi-queue: Total MTL queue size 4KB. PBL = 16, PBLx8 = 1 -> This setting would lead to an effective burst = 8*16 = 128, which would mean 128*16B = 2KB (half of queue size) Signed-off-by: Bhadram Varka --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index f27730d..630cb81 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -101,7 +101,7 @@ snps,write-requests = <1>; snps,read-requests = <3>; snps,burst-map = <0x7>; - snps,txpbl = <32>; + snps,txpbl = <16>; snps,rxpbl = <8>; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>;