From patchwork Fri Jun 1 12:12:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Suchanek X-Patchwork-Id: 923980 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-478896-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mips.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="N0NVsQwP"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40y3BP6DRcz9ry1 for ; Fri, 1 Jun 2018 22:13:01 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=t4B WBpyz+SkJ6uZ/KMFQO4eoaZxAIllLmIvvbV0c9k2xswxIPD0BwMPNgVR8NbJDf6A rxqxmBfVcGgczhfZyRES4g1olLN/CnD9/fm6LOELZf+J9MxrTwIx5AAzutu8UG11 ANsEEzP16exUGs62gL/dXextTkthD/a3oeHXSu+w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=pcRoqSsNW +pdfRMaqmltE6V9sFI=; b=N0NVsQwPUCTg0mNn2X2qnn2gVB1shfjcsai4X99Oo 0/DDwMLz9wgCj0opWbt2rxXYmfymG9jGywuDvXWRc1MQFdtm5oaOpWUlNQQLJo2o YMn5tDblBEf9O2Peqd/cCnm3Rh2YO/+UxUOD6UXt/6c66WY+rYaV9a2Igq0JxTOc oc= Received: (qmail 103959 invoked by alias); 1 Jun 2018 12:12:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 103240 invoked by uid 89); 1 Jun 2018 12:12:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy=robert, Robert, H*r:0700 X-HELO: 9pmail.ess.barracuda.com Received: from 9pmail.ess.barracuda.com (HELO 9pmail.ess.barracuda.com) (64.235.154.211) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 01 Jun 2018 12:12:40 +0000 Received: from mipsdag01.mipstec.com (mail1.mips.com [12.201.5.31]) by mx1413.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Fri, 01 Jun 2018 12:12:37 +0000 Received: from mipsdag02.mipstec.com (10.20.40.47) by mipsdag01.mipstec.com (10.20.40.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Fri, 1 Jun 2018 05:12:43 -0700 Received: from mipsdag02.mipstec.com ([fe80::b55f:2191:505b:cd29]) by mipsdag02.mipstec.com ([fe80::b55f:2191:505b:cd29%15]) with mapi id 15.01.1415.002; Fri, 1 Jun 2018 05:12:43 -0700 From: Robert Suchanek To: Matthew Fortune CC: "gcc-patches@gcc.gnu.org" Subject: [PATCH] MIPS: Update I6400 scheduler Date: Fri, 1 Jun 2018 12:12:43 +0000 Message-ID: MIME-Version: 1.0 X-BESS-ID: 1527855157-531715-3460-42696-1 X-BESS-VER: 2018.6-r1805312037 X-BESS-Apparent-Source-IP: 12.201.5.31 X-BESS-Outbound-Spam-Score: 0.01 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.193606 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn' t match header 0.01 BSF_SC0_SA_TO_FROM_DOMAIN_MATCH META: Sender Domain Matches Recipient Domain X-BESS-Outbound-Spam-Status: SCORE=0.01 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND, BSF_SC0_MISMATCH_TO, BSF_SC0_SA_TO_FROM_DOMAIN_MATCH X-BESS-BRTS-Status: 1 Hi, Update to i6400 scheduler. Regards, Robert gcc/ChangeLog: 2018-06-01 Prachi Godbole * config/mips/i6400.md (i6400_gpmuldiv): Remove cpu_unit. (i6400_gpmul): Add cpu_unit. (i6400_gpdiv): Likewise. (i6400_msa_add_d): Update reservations. (i6400_msa_int_add) Likewise. (i6400_msa_short_logic3) Likewise. (i6400_msa_short_logic2) Likewise. (i6400_msa_short_logic) Likewise. (i6400_msa_move) Likewise. (i6400_msa_cmp) Likewise. (i6400_msa_short_float2) Likewise. (i6400_msa_div_d) Likewise. (i6400_msa_long_logic1) Likewise. (i6400_msa_long_logic2) Likewise. (i6400_msa_mult) Likewise. (i6400_msa_long_float2) Likewise. (i6400_msa_long_float4) Likewise. (i6400_msa_long_float5) Likewise. (i6400_msa_long_float8) Likewise. (i6400_fpu_minmax): New define_insn_reservation. (i6400_fpu_fadd): Include frint type. (i6400_fpu_store): New define_insn_reservation. (i6400_fpu_load): Likewise. (i6400_fpu_move): Likewise. (i6400_fpu_fcmp): Likewise. (i6400_fpu_fmadd): Likewise. (i6400_int_mult): Include imul3nc type and update reservation. (i6400_int_div): Include idiv3 type and update reservation. (i6400_int_load): Update to check type not move_type. (i6400_int_store): Likewise. (i6400_int_prefetch): Set zero latency. --- gcc/config/mips/i6400.md | 86 ++++++++++++++++++++++++++++++++++-------------- 1 file changed, 61 insertions(+), 25 deletions(-) diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md index 413e9e8..a985401 100644 --- a/gcc/config/mips/i6400.md +++ b/gcc/config/mips/i6400.md @@ -21,7 +21,7 @@ (define_automaton "i6400_int_pipe, i6400_mdu_pipe, i6400_fpu_short_pipe, i6400_fpu_long_pipe") -(define_cpu_unit "i6400_gpmuldiv" "i6400_mdu_pipe") +(define_cpu_unit "i6400_gpmul, i6400_gpdiv" "i6400_mdu_pipe") (define_cpu_unit "i6400_agen, i6400_alu1, i6400_lsu" "i6400_int_pipe") (define_cpu_unit "i6400_control, i6400_ctu, i6400_alu0" "i6400_int_pipe") @@ -50,49 +50,49 @@ (define_insn_reservation "i6400_msa_add_d" 1 (and (eq_attr "cpu" "i6400") (and (eq_attr "mode" "!V2DI") (eq_attr "alu_type" "simd_add"))) - "i6400_fpu_short, i6400_fpu_intadd") + "i6400_fpu_short+i6400_fpu_intadd*2") ;; add, hadd, sub, hsub, average, min, max, compare (define_insn_reservation "i6400_msa_int_add" 2 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_int_arith")) - "i6400_fpu_short, i6400_fpu_intadd") + "i6400_fpu_short+i6400_fpu_intadd*2") ;; sat, pcnt (define_insn_reservation "i6400_msa_short_logic3" 3 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_sat,simd_pcnt")) - "i6400_fpu_short, i6400_fpu_logic") + "i6400_fpu_short+i6400_fpu_logic*2") ;; shifts, nloc, nlzc, bneg, bclr, shf (define_insn_reservation "i6400_msa_short_logic2" 2 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_shift,simd_shf,simd_bit")) - "i6400_fpu_short, i6400_fpu_logic") + "i6400_fpu_short+i6400_fpu_logic*2") ;; and, or, xor, ilv, pck, fill, splat (define_insn_reservation "i6400_msa_short_logic" 1 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_permute,simd_logic,simd_splat,simd_fill")) - "i6400_fpu_short, i6400_fpu_logic") + "i6400_fpu_short+i6400_fpu_logic*2") ;; move.v, ldi (define_insn_reservation "i6400_msa_move" 1 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_move")) - "i6400_fpu_short, i6400_fpu_logic") + "i6400_fpu_short+i6400_fpu_logic*2") ;; Float compare New: CMP.cond.fmt (define_insn_reservation "i6400_msa_cmp" 2 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_fcmp")) - "i6400_fpu_short, i6400_fpu_cmp") + "i6400_fpu_short+i6400_fpu_cmp*2") ;; Float min, max, class (define_insn_reservation "i6400_msa_short_float2" 2 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_fminmax,simd_fclass")) - "i6400_fpu_short, i6400_fpu_float") + "i6400_fpu_short+i6400_fpu_float*2") ;; div.d, mod.d (non-pipelined) (define_insn_reservation "i6400_msa_div_d" 36 @@ -158,43 +158,43 @@ (define_insn_reservation "i6400_fpu_msa_move" 1 (define_insn_reservation "i6400_msa_long_logic1" 1 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_bitmov,simd_insert")) - "i6400_fpu_long, i6400_fpu_logic_l") + "i6400_fpu_long+i6400_fpu_logic_l*2") ;; binsl, binsr, vshf, sld (define_insn_reservation "i6400_msa_long_logic2" 2 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_bitins,simd_sld")) - "i6400_fpu_long, i6400_fpu_logic_l") + "i6400_fpu_long+i6400_fpu_logic_l*2") ;; Vector mul, dotp, madd, msub (define_insn_reservation "i6400_msa_mult" 5 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_mul")) - "i6400_fpu_long, i6400_fpu_mult") + "i6400_fpu_long+i6400_fpu_mult*2") ;; Float flog2 (define_insn_reservation "i6400_msa_long_float2" 2 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_flog2")) - "i6400_fpu_long, i6400_fpu_float_l") + "i6400_fpu_long+i6400_fpu_float_l*2") ;; fadd, fsub (define_insn_reservation "i6400_msa_long_float4" 4 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_fadd,simd_fcvt")) - "i6400_fpu_long, i6400_fpu_float_l") + "i6400_fpu_long+i6400_fpu_float_l*2") ;; fmul, fexp2 (define_insn_reservation "i6400_msa_long_float5" 5 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_fmul,simd_fexp2")) - "i6400_fpu_long, i6400_fpu_float_l") + "i6400_fpu_long+i6400_fpu_float_l*2") ;; fmadd, fmsub (define_insn_reservation "i6400_msa_long_float8" 8 (and (eq_attr "cpu" "i6400") (eq_attr "type" "simd_fmadd")) - "i6400_fpu_long, i6400_fpu_float_l") + "i6400_fpu_long+i6400_fpu_float_l*2") ;; fdiv.d (define_insn_reservation "i6400_msa_fdiv_df" 30 @@ -219,10 +219,16 @@ (define_insn_reservation "i6400_fpu_fabs" 1 (eq_attr "type" "fabs,fneg,fmove")) "i6400_fpu_short, i6400_fpu_apu") +;; min, max, min_a, max_a, class +(define_insn_reservation "i6400_fpu_minmax" 2 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fminmax,fclass")) + "i6400_fpu_short+i6400_fpu_logic") + ;; fadd, fsub, fcvt (define_insn_reservation "i6400_fpu_fadd" 4 (and (eq_attr "cpu" "i6400") - (eq_attr "type" "fadd, fcvt")) + (eq_attr "type" "fadd, fcvt, frint")) "i6400_fpu_long, i6400_fpu_apu") ;; fmul @@ -244,6 +250,36 @@ (define_insn_reservation "i6400_fpu_div_sf" 22 (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")) "i6400_fpu_long+i6400_fpu_apu*22") +;; sdc1, swc1 +(define_insn_reservation "i6400_fpu_store" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fpstore")) + "i6400_agen_lsu") + +;; ldc1, lwc1 +(define_insn_reservation "i6400_fpu_load" 3 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fpload")) + "i6400_agen_lsu") + +;; mfc, mtc +(define_insn_reservation "i6400_fpu_move" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "move_type" "mfc, mtc")) + "i6400_control_alu0 | i6400_agen_alu1") + +;; fcmp +(define_insn_reservation "i6400_fpu_fcmp" 2 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fcmp")) + "i6400_fpu_short, i6400_fpu_apu") + +;; fmadd +(define_insn_reservation "i6400_fpu_fmadd" 8 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fmadd")) + "i6400_fpu_long, i6400_fpu_apu") + ;; ;; Integer pipe ;; @@ -272,32 +308,32 @@ (define_insn_reservation "i6400_int_nop" 0 (eq_attr "type" "nop")) "nothing") -;; mult, multu, mul +;; mul, mulu, muh, muhu (define_insn_reservation "i6400_int_mult" 4 (and (eq_attr "cpu" "i6400") - (eq_attr "type" "imul3,imul")) - "i6400_gpmuldiv") + (eq_attr "type" "imul3,imul,imul3nc")) + "i6400_gpmul") ;; divide (define_insn_reservation "i6400_int_div" 32 (and (eq_attr "cpu" "i6400") - (eq_attr "type" "idiv")) - "i6400_gpmuldiv*32") + (eq_attr "type" "idiv,idiv3")) + "i6400_gpdiv*32") ;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs (define_insn_reservation "i6400_int_load" 3 (and (eq_attr "cpu" "i6400") - (eq_attr "move_type" "load")) + (eq_attr "type" "load")) "i6400_agen_lsu") ;; store (define_insn_reservation "i6400_int_store" 1 (and (eq_attr "cpu" "i6400") - (eq_attr "move_type" "store")) + (eq_attr "type" "store")) "i6400_agen_lsu") ;; prefetch -(define_insn_reservation "i6400_int_prefetch" 3 +(define_insn_reservation "i6400_int_prefetch" 0 (and (eq_attr "cpu" "i6400") (eq_attr "type" "prefetch")) "i6400_agen_lsu")