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[69.42.5.101]) by smtp.gmail.com with ESMTPSA id h8-v6sm44886654pgq.56.2018.05.29.23.36.39 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 23:36:39 -0700 (PDT) From: Rosen Penev To: openwrt-devel@lists.openwrt.org Date: Tue, 29 May 2018 23:36:32 -0700 Message-Id: <20180530063639.31017-1-rosenp@gmail.com> X-Mailer: git-send-email 2.17.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180529_233652_497135_94FE9742 X-CRM114-Status: GOOD ( 19.45 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c05:0:0:0:242 listed in] [list.dnswl.org] 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rosenp[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Subject: [OpenWrt-Devel] [PATCH 1/8] ramips: mt7621-gpio: Move driver to files directory X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This will make porting staging changes easier. Signed-off-by: Rosen Penev --- .../files-4.14/drivers/gpio/gpio-mt7621.c | 354 +++++++++++++++++ ...IO-ralink-add-mt7621-gpio-controller.patch | 361 +----------------- 2 files changed, 355 insertions(+), 360 deletions(-) create mode 100644 target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c diff --git a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c new file mode 100644 index 0000000000..9ee4a0ea42 --- /dev/null +++ b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c @@ -0,0 +1,354 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2009-2011 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MTK_MAX_BANK 3 +#define MTK_BANK_WIDTH 32 + +enum mediatek_gpio_reg { + GPIO_REG_CTRL = 0, + GPIO_REG_POL, + GPIO_REG_DATA, + GPIO_REG_DSET, + GPIO_REG_DCLR, + GPIO_REG_REDGE, + GPIO_REG_FEDGE, + GPIO_REG_HLVL, + GPIO_REG_LLVL, + GPIO_REG_STAT, + GPIO_REG_EDGE, +}; + +static void __iomem *mediatek_gpio_membase; +static int mediatek_gpio_irq; +static struct irq_domain *mediatek_gpio_irq_domain; +static atomic_t irq_refcount = ATOMIC_INIT(0); + +struct mtk_gc { + struct gpio_chip chip; + spinlock_t lock; + int bank; + u32 rising; + u32 falling; +} *gc_map[MTK_MAX_BANK]; + +static inline struct mtk_gc +*to_mediatek_gpio(struct gpio_chip *chip) +{ + struct mtk_gc *mgc; + + mgc = container_of(chip, struct mtk_gc, chip); + + return mgc; +} + +static inline void +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val) +{ + iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4)); +} + +static inline u32 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg) +{ + return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4)); +} + +static void +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + + mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset)); +} + +static int +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + + return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset)); +} + +static int +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + unsigned long flags; + u32 t; + + spin_lock_irqsave(&rg->lock, flags); + t = mtk_gpio_r32(rg, GPIO_REG_CTRL); + t &= ~BIT(offset); + mtk_gpio_w32(rg, GPIO_REG_CTRL, t); + spin_unlock_irqrestore(&rg->lock, flags); + + return 0; +} + +static int +mediatek_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + unsigned long flags; + u32 t; + + spin_lock_irqsave(&rg->lock, flags); + t = mtk_gpio_r32(rg, GPIO_REG_CTRL); + t |= BIT(offset); + mtk_gpio_w32(rg, GPIO_REG_CTRL, t); + mediatek_gpio_set(chip, offset, value); + spin_unlock_irqrestore(&rg->lock, flags); + + return 0; +} + +static int +mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + unsigned long flags; + u32 t; + + spin_lock_irqsave(&rg->lock, flags); + t = mtk_gpio_r32(rg, GPIO_REG_CTRL); + spin_unlock_irqrestore(&rg->lock, flags); + + if (t & BIT(offset)) + return 0; + + return 1; +} + +static int +mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + + return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH)); +} + +static int +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank) +{ + const __be32 *id = of_get_property(bank, "reg", NULL); + struct mtk_gc *rg = devm_kzalloc(&pdev->dev, + sizeof(struct mtk_gc), GFP_KERNEL); + + if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK) + return -ENOMEM; + + gc_map[be32_to_cpu(*id)] = rg; + + memset(rg, 0, sizeof(struct mtk_gc)); + + spin_lock_init(&rg->lock); + + rg->chip.parent = &pdev->dev; + rg->chip.label = dev_name(&pdev->dev); + rg->chip.of_node = bank; + rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id); + rg->chip.ngpio = MTK_BANK_WIDTH; + rg->chip.direction_input = mediatek_gpio_direction_input; + rg->chip.direction_output = mediatek_gpio_direction_output; + rg->chip.get_direction = mediatek_gpio_get_direction; + rg->chip.get = mediatek_gpio_get; + rg->chip.set = mediatek_gpio_set; + if (mediatek_gpio_irq_domain) + rg->chip.to_irq = mediatek_gpio_to_irq; + rg->bank = be32_to_cpu(*id); + + /* set polarity to low for all gpios */ + mtk_gpio_w32(rg, GPIO_REG_POL, 0); + + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio); + + return gpiochip_add(&rg->chip); +} + +static void +mediatek_gpio_irq_handler(struct irq_desc *desc) +{ + int i; + + for (i = 0; i < MTK_MAX_BANK; i++) { + struct mtk_gc *rg = gc_map[i]; + unsigned long pending; + int bit; + + if (!rg) + continue; + + pending = mtk_gpio_r32(rg, GPIO_REG_STAT); + + for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { + u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit); + + generic_handle_irq(map); + mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); + } + } +} + +static void +mediatek_gpio_irq_unmask(struct irq_data *d) +{ + int pin = d->hwirq; + int bank = pin / 32; + struct mtk_gc *rg = gc_map[bank]; + unsigned long flags; + u32 rise, fall; + + if (!rg) + return; + + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); + + spin_lock_irqsave(&rg->lock, flags); + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising)); + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling)); + spin_unlock_irqrestore(&rg->lock, flags); +} + +static void +mediatek_gpio_irq_mask(struct irq_data *d) +{ + int pin = d->hwirq; + int bank = pin / 32; + struct mtk_gc *rg = gc_map[bank]; + unsigned long flags; + u32 rise, fall; + + if (!rg) + return; + + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); + + spin_lock_irqsave(&rg->lock, flags); + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq)); + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq)); + spin_unlock_irqrestore(&rg->lock, flags); +} + +static int +mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) +{ + int pin = d->hwirq; + int bank = pin / 32; + struct mtk_gc *rg = gc_map[bank]; + u32 mask = BIT(d->hwirq); + + if (!rg) + return -1; + + if (type == IRQ_TYPE_PROBE) { + if ((rg->rising | rg->falling) & mask) + return 0; + + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + } + + if (type & IRQ_TYPE_EDGE_RISING) + rg->rising |= mask; + else + rg->rising &= ~mask; + + if (type & IRQ_TYPE_EDGE_FALLING) + rg->falling |= mask; + else + rg->falling &= ~mask; + + return 0; +} + +static struct irq_chip mediatek_gpio_irq_chip = { + .name = "GPIO", + .irq_unmask = mediatek_gpio_irq_unmask, + .irq_mask = mediatek_gpio_irq_mask, + .irq_mask_ack = mediatek_gpio_irq_mask, + .irq_set_type = mediatek_gpio_irq_type, +}; + +static int +mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq); + irq_set_handler_data(irq, d); + + return 0; +} + +static const struct irq_domain_ops irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = mediatek_gpio_gpio_map, +}; + +static int +mediatek_gpio_probe(struct platform_device *pdev) +{ + struct device_node *bank, *np = pdev->dev.of_node; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mediatek_gpio_membase)) + return PTR_ERR(mediatek_gpio_membase); + + mediatek_gpio_irq = irq_of_parse_and_map(np, 0); + if (mediatek_gpio_irq) { + mediatek_gpio_irq_domain = irq_domain_add_linear(np, + MTK_MAX_BANK * MTK_BANK_WIDTH, + &irq_domain_ops, NULL); + if (!mediatek_gpio_irq_domain) + dev_err(&pdev->dev, "irq_domain_add_linear failed\n"); + } + + for_each_child_of_node(np, bank) + if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank")) + mediatek_gpio_bank_probe(pdev, bank); + + if (mediatek_gpio_irq_domain) + irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler); + + return 0; +} + +static const struct of_device_id mediatek_gpio_match[] = { + { .compatible = "mtk,mt7621-gpio" }, + {}, +}; +MODULE_DEVICE_TABLE(of, mediatek_gpio_match); + +static struct platform_driver mediatek_gpio_driver = { + .probe = mediatek_gpio_probe, + .driver = { + .name = "mt7621_gpio", + .owner = THIS_MODULE, + .of_match_table = mediatek_gpio_match, + }, +}; + +static int __init +mediatek_gpio_init(void) +{ + return platform_driver_register(&mediatek_gpio_driver); +} + +subsys_initcall(mediatek_gpio_init); diff --git a/target/linux/ramips/patches-4.14/0028-GPIO-ralink-add-mt7621-gpio-controller.patch b/target/linux/ramips/patches-4.14/0028-GPIO-ralink-add-mt7621-gpio-controller.patch index d657274efe..6f26775baa 100644 --- a/target/linux/ramips/patches-4.14/0028-GPIO-ralink-add-mt7621-gpio-controller.patch +++ b/target/linux/ramips/patches-4.14/0028-GPIO-ralink-add-mt7621-gpio-controller.patch @@ -8,9 +8,7 @@ Signed-off-by: John Crispin arch/mips/Kconfig | 3 + drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-mt7621.c | 354 ++++++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 364 insertions(+) - create mode 100644 drivers/gpio/gpio-mt7621.c + 3 files changed, 10 insertions(+) --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -46,360 +44,3 @@ Signed-off-by: John Crispin obj-$(CONFIG_GPIO_ZX) += gpio-zx.o obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o ---- /dev/null -+++ b/drivers/gpio/gpio-mt7621.c -@@ -0,0 +1,354 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2009-2011 Gabor Juhos -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MTK_MAX_BANK 3 -+#define MTK_BANK_WIDTH 32 -+ -+enum mediatek_gpio_reg { -+ GPIO_REG_CTRL = 0, -+ GPIO_REG_POL, -+ GPIO_REG_DATA, -+ GPIO_REG_DSET, -+ GPIO_REG_DCLR, -+ GPIO_REG_REDGE, -+ GPIO_REG_FEDGE, -+ GPIO_REG_HLVL, -+ GPIO_REG_LLVL, -+ GPIO_REG_STAT, -+ GPIO_REG_EDGE, -+}; -+ -+static void __iomem *mediatek_gpio_membase; -+static int mediatek_gpio_irq; -+static struct irq_domain *mediatek_gpio_irq_domain; -+static atomic_t irq_refcount = ATOMIC_INIT(0); -+ -+struct mtk_gc { -+ struct gpio_chip chip; -+ spinlock_t lock; -+ int bank; -+ u32 rising; -+ u32 falling; -+} *gc_map[MTK_MAX_BANK]; -+ -+static inline struct mtk_gc -+*to_mediatek_gpio(struct gpio_chip *chip) -+{ -+ struct mtk_gc *mgc; -+ -+ mgc = container_of(chip, struct mtk_gc, chip); -+ -+ return mgc; -+} -+ -+static inline void -+mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val) -+{ -+ iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4)); -+} -+ -+static inline u32 -+mtk_gpio_r32(struct mtk_gc *rg, u8 reg) -+{ -+ return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4)); -+} -+ -+static void -+mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -+{ -+ struct mtk_gc *rg = to_mediatek_gpio(chip); -+ -+ mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset)); -+} -+ -+static int -+mediatek_gpio_get(struct gpio_chip *chip, unsigned offset) -+{ -+ struct mtk_gc *rg = to_mediatek_gpio(chip); -+ -+ return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset)); -+} -+ -+static int -+mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -+{ -+ struct mtk_gc *rg = to_mediatek_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL); -+ t &= ~BIT(offset); -+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ return 0; -+} -+ -+static int -+mediatek_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ struct mtk_gc *rg = to_mediatek_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL); -+ t |= BIT(offset); -+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t); -+ mediatek_gpio_set(chip, offset, value); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ return 0; -+} -+ -+static int -+mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset) -+{ -+ struct mtk_gc *rg = to_mediatek_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ if (t & BIT(offset)) -+ return 0; -+ -+ return 1; -+} -+ -+static int -+mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin) -+{ -+ struct mtk_gc *rg = to_mediatek_gpio(chip); -+ -+ return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH)); -+} -+ -+static int -+mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank) -+{ -+ const __be32 *id = of_get_property(bank, "reg", NULL); -+ struct mtk_gc *rg = devm_kzalloc(&pdev->dev, -+ sizeof(struct mtk_gc), GFP_KERNEL); -+ -+ if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK) -+ return -ENOMEM; -+ -+ gc_map[be32_to_cpu(*id)] = rg; -+ -+ memset(rg, 0, sizeof(struct mtk_gc)); -+ -+ spin_lock_init(&rg->lock); -+ -+ rg->chip.parent = &pdev->dev; -+ rg->chip.label = dev_name(&pdev->dev); -+ rg->chip.of_node = bank; -+ rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id); -+ rg->chip.ngpio = MTK_BANK_WIDTH; -+ rg->chip.direction_input = mediatek_gpio_direction_input; -+ rg->chip.direction_output = mediatek_gpio_direction_output; -+ rg->chip.get_direction = mediatek_gpio_get_direction; -+ rg->chip.get = mediatek_gpio_get; -+ rg->chip.set = mediatek_gpio_set; -+ if (mediatek_gpio_irq_domain) -+ rg->chip.to_irq = mediatek_gpio_to_irq; -+ rg->bank = be32_to_cpu(*id); -+ -+ /* set polarity to low for all gpios */ -+ mtk_gpio_w32(rg, GPIO_REG_POL, 0); -+ -+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio); -+ -+ return gpiochip_add(&rg->chip); -+} -+ -+static void -+mediatek_gpio_irq_handler(struct irq_desc *desc) -+{ -+ int i; -+ -+ for (i = 0; i < MTK_MAX_BANK; i++) { -+ struct mtk_gc *rg = gc_map[i]; -+ unsigned long pending; -+ int bit; -+ -+ if (!rg) -+ continue; -+ -+ pending = mtk_gpio_r32(rg, GPIO_REG_STAT); -+ -+ for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { -+ u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit); -+ -+ generic_handle_irq(map); -+ mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); -+ } -+ } -+} -+ -+static void -+mediatek_gpio_irq_unmask(struct irq_data *d) -+{ -+ int pin = d->hwirq; -+ int bank = pin / 32; -+ struct mtk_gc *rg = gc_map[bank]; -+ unsigned long flags; -+ u32 rise, fall; -+ -+ if (!rg) -+ return; -+ -+ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); -+ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising)); -+ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling)); -+ spin_unlock_irqrestore(&rg->lock, flags); -+} -+ -+static void -+mediatek_gpio_irq_mask(struct irq_data *d) -+{ -+ int pin = d->hwirq; -+ int bank = pin / 32; -+ struct mtk_gc *rg = gc_map[bank]; -+ unsigned long flags; -+ u32 rise, fall; -+ -+ if (!rg) -+ return; -+ -+ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); -+ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq)); -+ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq)); -+ spin_unlock_irqrestore(&rg->lock, flags); -+} -+ -+static int -+mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) -+{ -+ int pin = d->hwirq; -+ int bank = pin / 32; -+ struct mtk_gc *rg = gc_map[bank]; -+ u32 mask = BIT(d->hwirq); -+ -+ if (!rg) -+ return -1; -+ -+ if (type == IRQ_TYPE_PROBE) { -+ if ((rg->rising | rg->falling) & mask) -+ return 0; -+ -+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; -+ } -+ -+ if (type & IRQ_TYPE_EDGE_RISING) -+ rg->rising |= mask; -+ else -+ rg->rising &= ~mask; -+ -+ if (type & IRQ_TYPE_EDGE_FALLING) -+ rg->falling |= mask; -+ else -+ rg->falling &= ~mask; -+ -+ return 0; -+} -+ -+static struct irq_chip mediatek_gpio_irq_chip = { -+ .name = "GPIO", -+ .irq_unmask = mediatek_gpio_irq_unmask, -+ .irq_mask = mediatek_gpio_irq_mask, -+ .irq_mask_ack = mediatek_gpio_irq_mask, -+ .irq_set_type = mediatek_gpio_irq_type, -+}; -+ -+static int -+mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -+{ -+ irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq); -+ irq_set_handler_data(irq, d); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops irq_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = mediatek_gpio_gpio_map, -+}; -+ -+static int -+mediatek_gpio_probe(struct platform_device *pdev) -+{ -+ struct device_node *bank, *np = pdev->dev.of_node; -+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(mediatek_gpio_membase)) -+ return PTR_ERR(mediatek_gpio_membase); -+ -+ mediatek_gpio_irq = irq_of_parse_and_map(np, 0); -+ if (mediatek_gpio_irq) { -+ mediatek_gpio_irq_domain = irq_domain_add_linear(np, -+ MTK_MAX_BANK * MTK_BANK_WIDTH, -+ &irq_domain_ops, NULL); -+ if (!mediatek_gpio_irq_domain) -+ dev_err(&pdev->dev, "irq_domain_add_linear failed\n"); -+ } -+ -+ for_each_child_of_node(np, bank) -+ if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank")) -+ mediatek_gpio_bank_probe(pdev, bank); -+ -+ if (mediatek_gpio_irq_domain) -+ irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler); -+ -+ return 0; -+} -+ -+static const struct of_device_id mediatek_gpio_match[] = { -+ { .compatible = "mtk,mt7621-gpio" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, mediatek_gpio_match); -+ -+static struct platform_driver mediatek_gpio_driver = { -+ .probe = mediatek_gpio_probe, -+ .driver = { -+ .name = "mt7621_gpio", -+ .owner = THIS_MODULE, -+ .of_match_table = mediatek_gpio_match, -+ }, -+}; -+ -+static int __init -+mediatek_gpio_init(void) -+{ -+ return platform_driver_register(&mediatek_gpio_driver); -+} -+ -+subsys_initcall(mediatek_gpio_init); From patchwork Wed May 30 06:36:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rosen Penev X-Patchwork-Id: 922565 X-Patchwork-Delegate: blogic@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[69.42.5.101]) by smtp.gmail.com with ESMTPSA id h8-v6sm44886654pgq.56.2018.05.29.23.36.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 23:36:41 -0700 (PDT) From: Rosen Penev To: openwrt-devel@lists.openwrt.org Date: Tue, 29 May 2018 23:36:33 -0700 Message-Id: <20180530063639.31017-2-rosenp@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530063639.31017-1-rosenp@gmail.com> References: <20180530063639.31017-1-rosenp@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180529_233653_145343_3A7AC451 X-CRM114-Status: GOOD ( 14.27 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c00:0:0:0:241 listed in] [list.dnswl.org] 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rosenp[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Subject: [OpenWrt-Devel] [PATCH 2/8] ramips: mt7621-gpio: Sync staging cleanup commits X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org remove redundant owner assignments of drivers mt7621: make symbol gc_map static Include the right header prefer unsigned int to bare unsigned fix some warnings because of lines exceeded 80 characters add SPDX identifier Signed-off-by: Rosen Penev --- .../files-4.14/drivers/gpio/gpio-mt7621.c | 42 ++++++++++--------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c index 9ee4a0ea42..a57738125b 100644 --- a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c +++ b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c @@ -1,15 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * * Copyright (C) 2009-2011 Gabor Juhos * Copyright (C) 2013 John Crispin */ #include #include -#include +#include #include #include #include @@ -37,9 +34,8 @@ enum mediatek_gpio_reg { static void __iomem *mediatek_gpio_membase; static int mediatek_gpio_irq; static struct irq_domain *mediatek_gpio_irq_domain; -static atomic_t irq_refcount = ATOMIC_INIT(0); -struct mtk_gc { +static struct mtk_gc { struct gpio_chip chip; spinlock_t lock; int bank; @@ -66,11 +62,13 @@ mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val) static inline u32 mtk_gpio_r32(struct mtk_gc *rg, u8 reg) { - return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4)); + u32 offset = (reg * 0x10) + (rg->bank * 0x4); + + return ioread32(mediatek_gpio_membase + offset); } static void -mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +mediatek_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct mtk_gc *rg = to_mediatek_gpio(chip); @@ -78,7 +76,7 @@ mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value) } static int -mediatek_gpio_get(struct gpio_chip *chip, unsigned offset) +mediatek_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct mtk_gc *rg = to_mediatek_gpio(chip); @@ -86,7 +84,7 @@ mediatek_gpio_get(struct gpio_chip *chip, unsigned offset) } static int -mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { struct mtk_gc *rg = to_mediatek_gpio(chip); unsigned long flags; @@ -103,7 +101,7 @@ mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset) static int mediatek_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) + unsigned int offset, int value) { struct mtk_gc *rg = to_mediatek_gpio(chip); unsigned long flags; @@ -120,7 +118,7 @@ mediatek_gpio_direction_output(struct gpio_chip *chip, } static int -mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct mtk_gc *rg = to_mediatek_gpio(chip); unsigned long flags; @@ -137,11 +135,12 @@ mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset) } static int -mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin) +mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) { struct mtk_gc *rg = to_mediatek_gpio(chip); - return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH)); + return irq_create_mapping(mediatek_gpio_irq_domain, + pin + (rg->bank * MTK_BANK_WIDTH)); } static int @@ -198,7 +197,8 @@ mediatek_gpio_irq_handler(struct irq_desc *desc) pending = mtk_gpio_r32(rg, GPIO_REG_STAT); for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { - u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit); + u32 map = irq_find_mapping(mediatek_gpio_irq_domain, + (MTK_BANK_WIDTH * i) + bit); generic_handle_irq(map); mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); @@ -288,9 +288,11 @@ static struct irq_chip mediatek_gpio_irq_chip = { }; static int -mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) { - irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq); + irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, + handle_level_irq); irq_set_handler_data(irq, d); return 0; @@ -325,7 +327,8 @@ mediatek_gpio_probe(struct platform_device *pdev) mediatek_gpio_bank_probe(pdev, bank); if (mediatek_gpio_irq_domain) - irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler); + irq_set_chained_handler(mediatek_gpio_irq, + mediatek_gpio_irq_handler); return 0; } @@ -340,7 +343,6 @@ static struct platform_driver mediatek_gpio_driver = { .probe = mediatek_gpio_probe, .driver = { .name = "mt7621_gpio", - .owner = THIS_MODULE, .of_match_table = mediatek_gpio_match, }, }; From patchwork Wed May 30 06:36:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rosen Penev X-Patchwork-Id: 922563 X-Patchwork-Delegate: blogic@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[69.42.5.101]) by smtp.gmail.com with ESMTPSA id h8-v6sm44886654pgq.56.2018.05.29.23.36.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 23:36:41 -0700 (PDT) From: Rosen Penev To: openwrt-devel@lists.openwrt.org Date: Tue, 29 May 2018 23:36:34 -0700 Message-Id: <20180530063639.31017-3-rosenp@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530063639.31017-1-rosenp@gmail.com> References: <20180530063639.31017-1-rosenp@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180529_233653_849149_344E1706 X-CRM114-Status: GOOD ( 13.14 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c00:0:0:0:242 listed in] [list.dnswl.org] 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rosenp[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Subject: [OpenWrt-Devel] [PATCH 3/8] staging: mt7621-gpio: replace 'mtk' to use correct one 'mediatek' X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org From: Sergio Paracuellos Gpio driver is using mtk and there is already 'mediatek' binding defined for this maker. Update driver to use it instead the custom one 'mtk'. Signed-off-by: Sergio Paracuellos Reviewed-by: NeilBrown Signed-off-by: Greg Kroah-Hartman --- target/linux/ramips/dts/mt7621.dtsi | 8 ++++---- target/linux/ramips/dts/mt7628an.dtsi | 8 ++++---- target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index f35e6a74fd..15a85fd4d1 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -73,26 +73,26 @@ #address-cells = <1>; #size-cells = <0>; - compatible = "mtk,mt7621-gpio"; + compatible = "mediatek,mt7621-gpio"; reg = <0x600 0x100>; gpio0: bank@0 { reg = <0>; - compatible = "mtk,mt7621-gpio-bank"; + compatible = "mediatek,mt7621-gpio-bank"; gpio-controller; #gpio-cells = <2>; }; gpio1: bank@1 { reg = <1>; - compatible = "mtk,mt7621-gpio-bank"; + compatible = "mediatek,mt7621-gpio-bank"; gpio-controller; #gpio-cells = <2>; }; gpio2: bank@2 { reg = <2>; - compatible = "mtk,mt7621-gpio-bank"; + compatible = "mediatek,mt7621-gpio-bank"; gpio-controller; #gpio-cells = <2>; }; diff --git a/target/linux/ramips/dts/mt7628an.dtsi b/target/linux/ramips/dts/mt7628an.dtsi index df2ed37c9a..d02250d01c 100644 --- a/target/linux/ramips/dts/mt7628an.dtsi +++ b/target/linux/ramips/dts/mt7628an.dtsi @@ -81,7 +81,7 @@ #address-cells = <1>; #size-cells = <0>; - compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; + compatible = "mtk,mt7628-gpio", "mediatek,mt7621-gpio"; reg = <0x600 0x100>; interrupt-parent = <&intc>; @@ -89,21 +89,21 @@ gpio0: bank@0 { reg = <0>; - compatible = "mtk,mt7621-gpio-bank"; + compatible = "mediatek,mt7621-gpio-bank"; gpio-controller; #gpio-cells = <2>; }; gpio1: bank@1 { reg = <1>; - compatible = "mtk,mt7621-gpio-bank"; + compatible = "mediatek,mt7621-gpio-bank"; gpio-controller; #gpio-cells = <2>; }; gpio2: bank@2 { reg = <2>; - compatible = "mtk,mt7621-gpio-bank"; + compatible = "mediatek,mt7621-gpio-bank"; gpio-controller; #gpio-cells = <2>; }; diff --git a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c index a57738125b..7d179492d8 100644 --- a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c +++ b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c @@ -323,7 +323,7 @@ mediatek_gpio_probe(struct platform_device *pdev) } for_each_child_of_node(np, bank) - if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank")) + if (of_device_is_compatible(bank, "mediatek,mt7621-gpio-bank")) mediatek_gpio_bank_probe(pdev, bank); if (mediatek_gpio_irq_domain) @@ -334,7 +334,7 @@ mediatek_gpio_probe(struct platform_device *pdev) } static const struct of_device_id mediatek_gpio_match[] = { - { .compatible = "mtk,mt7621-gpio" }, + { .compatible = "mediatek,mt7621-gpio" }, {}, }; MODULE_DEVICE_TABLE(of, mediatek_gpio_match); From patchwork Wed May 30 06:36:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rosen Penev X-Patchwork-Id: 922562 X-Patchwork-Delegate: blogic@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[69.42.5.101]) by smtp.gmail.com with ESMTPSA id h8-v6sm44886654pgq.56.2018.05.29.23.36.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 23:36:42 -0700 (PDT) From: Rosen Penev To: openwrt-devel@lists.openwrt.org Date: Tue, 29 May 2018 23:36:35 -0700 Message-Id: <20180530063639.31017-4-rosenp@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530063639.31017-1-rosenp@gmail.com> References: <20180530063639.31017-1-rosenp@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180529_233653_168978_3AF958D2 X-CRM114-Status: GOOD ( 17.23 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c00:0:0:0:241 listed in] [list.dnswl.org] 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rosenp[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Subject: [OpenWrt-Devel] [PATCH 4/8] staging: mt7621-gpio: avoid use of globals and use platform_data instead X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org From: Sergio Paracuellos Gpio driver have a some globals which can be avoided just using platform_data in a proper form. This commit adds a new struct mtk_data which includes all of those globals setting them using platform_set_drvdata and devm_gpiochip_add_data functions. With this properly set we are able to retrieve driver data along the code using kernel api's so globals are not needed anymore. Signed-off-by: Sergio Paracuellos Reviewed-by: NeilBrown Signed-off-by: Greg Kroah-Hartman --- .../files-4.14/drivers/gpio/gpio-mt7621.c | 90 +++++++++++++------ 1 file changed, 62 insertions(+), 28 deletions(-) diff --git a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c index 7d179492d8..077a7c24df 100644 --- a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c +++ b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c @@ -31,17 +31,20 @@ enum mediatek_gpio_reg { GPIO_REG_EDGE, }; -static void __iomem *mediatek_gpio_membase; -static int mediatek_gpio_irq; -static struct irq_domain *mediatek_gpio_irq_domain; - -static struct mtk_gc { +struct mtk_gc { struct gpio_chip chip; spinlock_t lock; int bank; u32 rising; u32 falling; -} *gc_map[MTK_MAX_BANK]; +}; + +struct mtk_data { + void __iomem *gpio_membase; + int gpio_irq; + struct irq_domain *gpio_irq_domain; + struct mtk_gc *gc_map[MTK_MAX_BANK]; +}; static inline struct mtk_gc *to_mediatek_gpio(struct gpio_chip *chip) @@ -56,15 +59,19 @@ static inline struct mtk_gc static inline void mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val) { - iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4)); + struct mtk_data *gpio_data = gpiochip_get_data(&rg->chip); + u32 offset = (reg * 0x10) + (rg->bank * 0x4); + + iowrite32(val, gpio_data->gpio_membase + offset); } static inline u32 mtk_gpio_r32(struct mtk_gc *rg, u8 reg) { + struct mtk_data *gpio_data = gpiochip_get_data(&rg->chip); u32 offset = (reg * 0x10) + (rg->bank * 0x4); - return ioread32(mediatek_gpio_membase + offset); + return ioread32(gpio_data->gpio_membase + offset); } static void @@ -137,23 +144,26 @@ mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) static int mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) { + struct mtk_data *gpio_data = gpiochip_get_data(chip); struct mtk_gc *rg = to_mediatek_gpio(chip); - return irq_create_mapping(mediatek_gpio_irq_domain, + return irq_create_mapping(gpio_data->gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH)); } static int mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank) { + struct mtk_data *gpio_data = dev_get_drvdata(&pdev->dev); const __be32 *id = of_get_property(bank, "reg", NULL); struct mtk_gc *rg = devm_kzalloc(&pdev->dev, sizeof(struct mtk_gc), GFP_KERNEL); + int ret; if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK) return -ENOMEM; - gc_map[be32_to_cpu(*id)] = rg; + gpio_data->gc_map[be32_to_cpu(*id)] = rg; memset(rg, 0, sizeof(struct mtk_gc)); @@ -169,25 +179,33 @@ mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank) rg->chip.get_direction = mediatek_gpio_get_direction; rg->chip.get = mediatek_gpio_get; rg->chip.set = mediatek_gpio_set; - if (mediatek_gpio_irq_domain) + if (gpio_data->gpio_irq_domain) rg->chip.to_irq = mediatek_gpio_to_irq; rg->bank = be32_to_cpu(*id); + ret = devm_gpiochip_add_data(&pdev->dev, &rg->chip, gpio_data); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpio %d, ret=%d\n", + rg->chip.ngpio, ret); + return ret; + } + /* set polarity to low for all gpios */ mtk_gpio_w32(rg, GPIO_REG_POL, 0); dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio); - return gpiochip_add(&rg->chip); + return 0; } static void mediatek_gpio_irq_handler(struct irq_desc *desc) { + struct mtk_data *gpio_data = irq_desc_get_handler_data(desc); int i; for (i = 0; i < MTK_MAX_BANK; i++) { - struct mtk_gc *rg = gc_map[i]; + struct mtk_gc *rg = gpio_data->gc_map[i]; unsigned long pending; int bit; @@ -197,7 +215,7 @@ mediatek_gpio_irq_handler(struct irq_desc *desc) pending = mtk_gpio_r32(rg, GPIO_REG_STAT); for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { - u32 map = irq_find_mapping(mediatek_gpio_irq_domain, + u32 map = irq_find_mapping(gpio_data->gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit); generic_handle_irq(map); @@ -209,9 +227,10 @@ mediatek_gpio_irq_handler(struct irq_desc *desc) static void mediatek_gpio_irq_unmask(struct irq_data *d) { + struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d); int pin = d->hwirq; int bank = pin / 32; - struct mtk_gc *rg = gc_map[bank]; + struct mtk_gc *rg = gpio_data->gc_map[bank]; unsigned long flags; u32 rise, fall; @@ -230,9 +249,10 @@ mediatek_gpio_irq_unmask(struct irq_data *d) static void mediatek_gpio_irq_mask(struct irq_data *d) { + struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d); int pin = d->hwirq; int bank = pin / 32; - struct mtk_gc *rg = gc_map[bank]; + struct mtk_gc *rg = gpio_data->gc_map[bank]; unsigned long flags; u32 rise, fall; @@ -251,9 +271,10 @@ mediatek_gpio_irq_mask(struct irq_data *d) static int mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) { + struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d); int pin = d->hwirq; int bank = pin / 32; - struct mtk_gc *rg = gc_map[bank]; + struct mtk_gc *rg = gpio_data->gc_map[bank]; u32 mask = BIT(d->hwirq); if (!rg) @@ -291,6 +312,11 @@ static int mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { + int ret; + + ret = irq_set_chip_data(irq, d->host_data); + if (ret < 0) + return ret; irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq); irq_set_handler_data(irq, d); @@ -308,27 +334,35 @@ mediatek_gpio_probe(struct platform_device *pdev) { struct device_node *bank, *np = pdev->dev.of_node; struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct mtk_data *gpio_data; - mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mediatek_gpio_membase)) - return PTR_ERR(mediatek_gpio_membase); + gpio_data = devm_kzalloc(&pdev->dev, sizeof(*gpio_data), GFP_KERNEL); + if (!gpio_data) + return -ENOMEM; + + gpio_data->gpio_membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(gpio_data->gpio_membase)) + return PTR_ERR(gpio_data->gpio_membase); - mediatek_gpio_irq = irq_of_parse_and_map(np, 0); - if (mediatek_gpio_irq) { - mediatek_gpio_irq_domain = irq_domain_add_linear(np, + gpio_data->gpio_irq = irq_of_parse_and_map(np, 0); + if (gpio_data->gpio_irq) { + gpio_data->gpio_irq_domain = irq_domain_add_linear(np, MTK_MAX_BANK * MTK_BANK_WIDTH, - &irq_domain_ops, NULL); - if (!mediatek_gpio_irq_domain) + &irq_domain_ops, gpio_data); + if (!gpio_data->gpio_irq_domain) dev_err(&pdev->dev, "irq_domain_add_linear failed\n"); } + platform_set_drvdata(pdev, gpio_data); + for_each_child_of_node(np, bank) if (of_device_is_compatible(bank, "mediatek,mt7621-gpio-bank")) mediatek_gpio_bank_probe(pdev, bank); - if (mediatek_gpio_irq_domain) - irq_set_chained_handler(mediatek_gpio_irq, - mediatek_gpio_irq_handler); + if (gpio_data->gpio_irq_domain) + irq_set_chained_handler_and_data(gpio_data->gpio_irq, + mediatek_gpio_irq_handler, + gpio_data); return 0; } From patchwork Wed May 30 06:36:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rosen Penev X-Patchwork-Id: 922564 X-Patchwork-Delegate: blogic@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; 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[69.42.5.101]) by smtp.gmail.com with ESMTPSA id h8-v6sm44886654pgq.56.2018.05.29.23.36.43 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 23:36:43 -0700 (PDT) From: Rosen Penev To: openwrt-devel@lists.openwrt.org Date: Tue, 29 May 2018 23:36:36 -0700 Message-Id: <20180530063639.31017-5-rosenp@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530063639.31017-1-rosenp@gmail.com> References: <20180530063639.31017-1-rosenp@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180529_233655_372070_90672868 X-CRM114-Status: GOOD ( 11.21 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c00:0:0:0:244 listed in] [list.dnswl.org] 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rosenp[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Subject: [OpenWrt-Devel] [PATCH 5/8] staging: mt7621-gpio: avoid devm_kzalloc() hidden inside declarations and refactor function a bit X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org From: Sergio Paracuellos Driver probe function includes an allocation using devm_kzalloc which is "hidden" a bit inside the declarations. Extract this to a better place to increase readability. Also because we are allocating zeroed memory 'memset' statement is not needed at all. Condition for checking for a valid gpio id is wrong and it should be greater or equal instead of only greater so update to be the good one. Signed-off-by: Sergio Paracuellos Reviewed-by: NeilBrown Signed-off-by: Greg Kroah-Hartman --- .../ramips/files-4.14/drivers/gpio/gpio-mt7621.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c index 077a7c24df..bbe6cce56d 100644 --- a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c +++ b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c @@ -156,17 +156,18 @@ mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank) { struct mtk_data *gpio_data = dev_get_drvdata(&pdev->dev); const __be32 *id = of_get_property(bank, "reg", NULL); - struct mtk_gc *rg = devm_kzalloc(&pdev->dev, - sizeof(struct mtk_gc), GFP_KERNEL); + struct mtk_gc *rg; int ret; - if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK) + if (!id || be32_to_cpu(*id) >= MTK_MAX_BANK) + return -EINVAL; + + rg = devm_kzalloc(&pdev->dev, sizeof(struct mtk_gc), GFP_KERNEL); + if (!rg) return -ENOMEM; gpio_data->gc_map[be32_to_cpu(*id)] = rg; - memset(rg, 0, sizeof(struct mtk_gc)); - spin_lock_init(&rg->lock); rg->chip.parent = &pdev->dev; From patchwork Wed May 30 06:36:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rosen Penev X-Patchwork-Id: 922568 X-Patchwork-Delegate: blogic@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="BCT4Y+Cd"; dkim=fail reason="signature verification failed" (2048-bit key; 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[69.42.5.101]) by smtp.gmail.com with ESMTPSA id h8-v6sm44886654pgq.56.2018.05.29.23.36.44 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 23:36:44 -0700 (PDT) From: Rosen Penev To: openwrt-devel@lists.openwrt.org Date: Tue, 29 May 2018 23:36:37 -0700 Message-Id: <20180530063639.31017-6-rosenp@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530063639.31017-1-rosenp@gmail.com> References: <20180530063639.31017-1-rosenp@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180529_233656_260059_C2279961 X-CRM114-Status: GOOD ( 10.43 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c05:0:0:0:243 listed in] [list.dnswl.org] 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rosenp[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Subject: [OpenWrt-Devel] [PATCH 6/8] staging: mt7621-gpio: use ternary operator in return in mediatek_gpio_get_direction X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org From: Sergio Paracuellos This commits replaces if statement and two returns in favour of a only one return using a ternary operator. Signed-off-by: Sergio Paracuellos Reviewed-by: NeilBrown Signed-off-by: Greg Kroah-Hartman --- target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c index bbe6cce56d..15a1003017 100644 --- a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c +++ b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c @@ -135,10 +135,7 @@ mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) t = mtk_gpio_r32(rg, GPIO_REG_CTRL); spin_unlock_irqrestore(&rg->lock, flags); - if (t & BIT(offset)) - return 0; - - return 1; + return (t & BIT(offset)) ? 0 : 1; } static int From patchwork Wed May 30 06:36:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rosen Penev X-Patchwork-Id: 922560 X-Patchwork-Delegate: blogic@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="MDSbQGKs"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="E60JAXkN"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wgqg4BZHz9s0q for ; Wed, 30 May 2018 16:37:03 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Subject:References: In-Reply-To:Message-Id:Date:To:From:Reply-To:Cc:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=GNZXfyvIQqAdxE/Cw7yxamDla7vG45r4cUqfkVeYUjc=; b=MDSbQGKsi34UpK3/PgDTV8ZDLm BHjW/zmNH1Z13+Kh/pdJoML86WJ4Vt29FXw6d/8A4LTsd2GJjtz31i3CHbhpJojsXizZmSvjKWL9U iSOTQNhggaQTGeGaUanhKsg6h7U2H33WhEaQiCieKI2FnX+ISdp/f8BSelmNAnjFFriLRCh5p4wFT rH7n1HrVSClTX7ISGsxPDUCzRzCGRzNSq0LB+Gt/UJdYXOFNDhjDUWB2vrUeq757884WXXtxhkUYF ofB2YAC5n3rNmH3JHhd6mjcWbtTxv9Y8LH4nsp0KJnN/1XifbWwOtGrCY5vWChDpv1wL5Bi1jAY1q 7xj9repw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fNujB-0005lu-9n; Wed, 30 May 2018 06:36:57 +0000 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fNuj7-0005ht-2Z for lede-dev@lists.infradead.org; Wed, 30 May 2018 06:36:54 +0000 Received: by mail-pf0-x241.google.com with SMTP id q22-v6so8497573pff.11 for ; Tue, 29 May 2018 23:36:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=ysAa3Uz6FGj3+l2VN06itjjcoPd97KQZRrKLDTxwKFE=; b=E60JAXkNCUJMlufFlKOQ9yhPYHaolwP+vWbN1HF6mHAhAfauhJTeqOI6AIvPqGeBwc yuv9Nf2GVXbeSEcfV+32kxvI4xNO4mJilS5XymFEu7KOagpc0t7vuoVSZlGjUvras6Nd 9zSjpreGTJVAvbXvmQQ2SLngSUXoqFO63NHZu+PMRPLBBZcHiiIsL3gnJolglilJHE5v h4RzyUdKZmr6gDDC/79WwGgJrfBnqXSPtOix08+Zd17vDNIsgtQdLeygb3UgdsKM6WBg OoGQK9WUp1vP5qrELQwrfRcA1uk/V8F9hNLFjBWOt6ZEUT9c+p0s6mjCDrFRs9f5/1tR zCHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=ysAa3Uz6FGj3+l2VN06itjjcoPd97KQZRrKLDTxwKFE=; b=pJlTu4geYUTatzrnOV5oKb3gdSFO1Mj4AD+L59GkGqSgWGrJq5MXm0+QShVV8kF1No an10dVMIgURjNy3G3QLuFgf+ew1slzqEU/Z4donVjkxZbszEwmaa2f5UdRcJUSf+w9VG PuZ4ihGoT3EBbLxjgNzLTxlBwbWy3dOJcQTgLB/h+JRhUn2uNbaVqfmsqkr200NGJGzp RI7JHY3WYPyxclkqICySlq6bVg6aY4Q1wL3DbX5TfucsCIYJTW9ecfmn+5rKKLuVDGDN /y1hcVlDbURQbVEic7o3AOXPfEm03eHSAfZ4HTC4CgeBicN6cRcY8+1HedCv8HYubiur 5RrQ== X-Gm-Message-State: ALKqPwe+DhGWfEm+y+PCqyYXMAv4uDJFCqVb56mNdV5v+4U3hlvaflnZ PgPWLsLYEknLonHUQjUFXf/3Ss2G X-Google-Smtp-Source: ADUXVKKnp0e+eNQ7zEsBHRp1fEE43jUjCKyj24oYLLIS/xmb+sk3mm4FT/01J1v0+BKctT+WOADE4A== X-Received: by 2002:a62:3ad8:: with SMTP id v85-v6mr1519854pfj.184.1527662206097; Tue, 29 May 2018 23:36:46 -0700 (PDT) Received: from clevo-mangix.lan (astound-69-42-5-101.ca.astound.net. [69.42.5.101]) by smtp.gmail.com with ESMTPSA id h8-v6sm44886654pgq.56.2018.05.29.23.36.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 23:36:45 -0700 (PDT) From: Rosen Penev To: openwrt-devel@lists.openwrt.org Date: Tue, 29 May 2018 23:36:38 -0700 Message-Id: <20180530063639.31017-7-rosenp@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530063639.31017-1-rosenp@gmail.com> References: <20180530063639.31017-1-rosenp@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180529_233653_142001_A3776FCA X-CRM114-Status: GOOD ( 12.35 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c00:0:0:0:241 listed in] [list.dnswl.org] 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rosenp[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Subject: [OpenWrt-Devel] [PATCH 7/8] staging: mt7621-gpio: use MTK_BANK_WIDTH instead of magic number X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org From: Sergio Paracuellos There are some places where magic number '32' is being used to get the gpio bank. There already exist a definition MTK_BANK_WIDTH with this value, so just use it instead. Signed-off-by: Sergio Paracuellos Reviewed-by: NeilBrown Signed-off-by: Greg Kroah-Hartman --- target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c index 15a1003017..5d923a7456 100644 --- a/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c +++ b/target/linux/ramips/files-4.14/drivers/gpio/gpio-mt7621.c @@ -227,7 +227,7 @@ mediatek_gpio_irq_unmask(struct irq_data *d) { struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d); int pin = d->hwirq; - int bank = pin / 32; + int bank = pin / MTK_BANK_WIDTH; struct mtk_gc *rg = gpio_data->gc_map[bank]; unsigned long flags; u32 rise, fall; @@ -249,7 +249,7 @@ mediatek_gpio_irq_mask(struct irq_data *d) { struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d); int pin = d->hwirq; - int bank = pin / 32; + int bank = pin / MTK_BANK_WIDTH; struct mtk_gc *rg = gpio_data->gc_map[bank]; unsigned long flags; u32 rise, fall; @@ -271,7 +271,7 @@ mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) { struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d); int pin = d->hwirq; - int bank = pin / 32; + int bank = pin / MTK_BANK_WIDTH; struct mtk_gc *rg = gpio_data->gc_map[bank]; u32 mask = BIT(d->hwirq); From patchwork Wed May 30 06:36:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rosen Penev X-Patchwork-Id: 922566 X-Patchwork-Delegate: blogic@openwrt.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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[69.42.5.101]) by smtp.gmail.com with ESMTPSA id h8-v6sm44886654pgq.56.2018.05.29.23.36.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 23:36:46 -0700 (PDT) From: Rosen Penev To: openwrt-devel@lists.openwrt.org Date: Tue, 29 May 2018 23:36:39 -0700 Message-Id: <20180530063639.31017-8-rosenp@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530063639.31017-1-rosenp@gmail.com> References: <20180530063639.31017-1-rosenp@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180529_233655_453476_72E05790 X-CRM114-Status: UNSURE ( 8.69 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c00:0:0:0:244 listed in] [list.dnswl.org] 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rosenp[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Subject: [OpenWrt-Devel] [PATCH 8/8] staging: mt7621-dts: add interrupt device tree nodes for the gpio controller X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org From: Sergio Paracuellos The GPIO controller of mt7621 can receive interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU using GIC INT12. Update device tree accordly. Signed-off-by: Sergio Paracuellos Reviewed-by: NeilBrown Signed-off-by: Greg Kroah-Hartman --- target/linux/ramips/dts/mt7621.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 15a85fd4d1..05f4f046f6 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -76,6 +76,9 @@ compatible = "mediatek,mt7621-gpio"; reg = <0x600 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + gpio0: bank@0 { reg = <0>; compatible = "mediatek,mt7621-gpio-bank";