From patchwork Sat Sep 23 06:17:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 817766 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="V2FHOSES"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xzgBc1v5sz9t67 for ; Sat, 23 Sep 2017 16:18:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750766AbdIWGR7 (ORCPT ); Sat, 23 Sep 2017 02:17:59 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:36651 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750741AbdIWGR6 (ORCPT ); Sat, 23 Sep 2017 02:17:58 -0400 Received: by mail-pf0-f193.google.com with SMTP id f84so1338869pfj.3; Fri, 22 Sep 2017 23:17:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=05eUZYVyW+p2e9ax03Dk8j3IJszT5Z3eJA6/dsGQKwE=; b=V2FHOSESyYjv8urR2gRtHJsj27mKdUHW0Ugr8noTBkcxE/xtyhg8Wz9TuUPQVGaZFw 8hWG+eAdb7zZKC1yTgMn4pjesga6woKGNX9l6FHYQ0okTESGsEg8bFtcZPKSIJ/vx/M6 3Cykw7fB+LyaKRjiAn4rzPhCRzIhs7jEqJt5J3R6ZE8fPkh1/8gR8s6jmdHJ5M8MmMvT JiLoLuO8z5iRZjymhZ2A7yfC9TNmIQvEdUUeE5v/mwOE+682ERYkLZM7CQTDnNgsuqhu qYkF1VWs3xtcYrLuscvCBn5htjzjStImGI2DpdltVPnjB1Y7dTbcF9+rtW7fXwwSwbbY lM7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=05eUZYVyW+p2e9ax03Dk8j3IJszT5Z3eJA6/dsGQKwE=; b=Z/M5PxsN/r8U+BAbSpa5o9HL7IGwQ1WWkgiACvCCLO8fX1C/FuFIWmr9/pZGQvz+YZ xyhvpT2zawc/e9ADPXKfaPEJXaMn1vK/b2/x7buMsImDLHJ94zSr+6CpC/m3h6FFKyXw kVzmGehMWFHCyw90lxVGji/1WelgyY24RPVztAx/WsBizpP6tfjx23YbfwhDvf3UJcMl 6I2vfyqhchi7Oj4lTXRoD3XMjcIGKlPOytI4alT2tZTGxuWO01ezbTvmWixkC39E/2LB lWzXERdKGMMqt9aP44n2bjCGBieY0AyzM9/4QyhqQdcqUH7APuTCNJV0jfxzzb2ISEdG xfUA== X-Gm-Message-State: AHPjjUhydw3uG01oXXKRvn3zNCS/dknTCzBIYCde7zFjUDGHniTtCecE nAm0zR9xNGrtajYTMR5NWtM= X-Google-Smtp-Source: AOwi7QD8UYT1Nf+C5jLQC8Y/yhF3YnnaOl9dDm3EC8Oas9spwAN4LhD3Qbvid29Xy66l1275+lcswA== X-Received: by 10.99.157.74 with SMTP id i71mr1381315pgd.238.1506147477692; Fri, 22 Sep 2017 23:17:57 -0700 (PDT) Received: from localhost (198-0-214-85-static.hfc.comcastbusiness.net. [198.0.214.85]) by smtp.gmail.com with ESMTPSA id 89sm2088621pfn.75.2017.09.22.23.17.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Sep 2017 23:17:56 -0700 (PDT) From: Thierry Reding X-Google-Original-From: Thierry Reding To: Bjorn Helgaas Cc: Thierry Reding , Jonathan Hunter , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] PCI: tegra: Use different MSI target address for Tegra20 Date: Fri, 22 Sep 2017 23:17:40 -0700 Message-Id: <20170923061740.6012-1-treding@nvidia.com> X-Mailer: git-send-email 2.14.1 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra20 PCIe controller has a different address range for MSI, so select a different target address. Fixes: d7bd554f27c9 ("PCI: tegra: Do not allocate MSI target memory") Signed-off-by: Thierry Reding Reported-by: Vidya Sagar Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index e8e1ddbaabc9..5b02ea59524b 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -1563,8 +1563,18 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) * none of the Tegra SoCs that contain this PCI host bridge can * address more than 16 GiB of system memory, the last 4 KiB of * these 1012 GiB is a good candidate. + * + * Unfortunately, Tegra20 is slightly different in that the physical + * address for this MSI region is limited to the lower 32 bits of the + * address map, so the address that we pick is going to have to be + * located somewhere within the region addressable by the CPU and + * on-SoC controllers. To be on the safe side, we select an address + * from a region that is marked unused (0xf0010000 - 0xfffeffff). */ - msi->phys = 0xfcfffff000; + if (soc->msi_base_shift > 0) + msi->phys = 0xfcfffff000; + else + msi->phys = 0x00f0010000; afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);