From patchwork Tue May 29 16:36:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 922238 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40wKC61wqxz9ry1 for ; Wed, 30 May 2018 02:37:38 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 076E9C21E50; Tue, 29 May 2018 16:37:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B36A7C21EA2; Tue, 29 May 2018 16:37:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5597DC21F02; Tue, 29 May 2018 16:37:03 +0000 (UTC) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by lists.denx.de (Postfix) with ESMTPS id 693E4C21F07 for ; Tue, 29 May 2018 16:37:01 +0000 (UTC) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 40wKBP1Pcpz1qxpN; Tue, 29 May 2018 18:37:01 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 40wKBP12RVz1qvSx; Tue, 29 May 2018 18:37:01 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id U3U1RfASgQco; Tue, 29 May 2018 18:36:59 +0200 (CEST) X-Auth-Info: JoH1EIJ/KHCWrqvIY1cro8HBl6u7OZkWlEnFgDnJrsQ= Received: from localhost.localdomain (cst-prg-12-21.cust.vodafone.cz [46.135.12.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Tue, 29 May 2018 18:36:59 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Tue, 29 May 2018 18:36:56 +0200 Message-Id: <20180529163656.29116-1-marex@denx.de> X-Mailer: git-send-email 2.17.0 Cc: Marek Vasut , Chin Liang See Subject: [U-Boot] [PATCH] ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only difference is the part which configures OCRAM as cachable, which doesn't really work as it covers more than the OCRAM. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Reviewed-by: Chin Liang See --- drivers/ddr/altera/sdram_arria10.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 706a038b88..1f2b7f4819 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -713,28 +713,3 @@ int ddr_calibration_sequence(void) return 0; } - -void dram_bank_mmu_setup(int bank) -{ - bd_t *bd = gd->bd; - int i; - - debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } - - /* same as above but just that we would want cacheable for ocram too */ - i = CONFIG_SYS_INIT_RAM_ADDR >> 20; -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif -}