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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id x26-v6sm6270818ljd.81.2018.05.29.03.50.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:14 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:34 +0200 Message-Id: <20180529105011.1914-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PULL v1 01/38] target-microblaze: dec_load: Use bool instead of unsigned int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Use bool instead of unsigned int to represent flags. No functional change. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0872dc9ded..a8a5eaebec 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -897,14 +897,15 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) static void dec_load(DisasContext *dc) { TCGv t, v, *addr; - unsigned int size, rev = 0, ex = 0; + unsigned int size; + bool rev = false, ex = false; TCGMemOp mop; mop = dc->opcode & 3; size = 1 << mop; if (!dc->type_b) { - rev = (dc->ir >> 9) & 1; - ex = (dc->ir >> 10) & 1; + rev = extract32(dc->ir, 9, 1); + ex = extract32(dc->ir, 10, 1); } mop |= MO_TE; if (rev) { From patchwork Tue May 29 10:49:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921957 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WH01lu6U"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9WL1qjgz9rxs for ; Tue, 29 May 2018 20:51:10 +1000 (AEST) Received: from localhost ([::1]:60086 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDb-0001F7-TZ for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:51:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcCq-00019z-EM for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcCp-0003jO-19 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:20 -0400 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:39938) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcCo-0003i4-Q1 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:18 -0400 Received: by mail-wm0-x235.google.com with SMTP id x2-v6so31856289wmh.5 for ; Tue, 29 May 2018 03:50:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7ATpslQKWd63w3UD7NML8p8c0FLP9bLh9tRI+SfFzVk=; b=WH01lu6UMY0UacQQhnwulE+WbAyOdq1x/0QVwlEvmXSWbpZOFV1SevhpHZaf0uV3a9 9GsKvAPO3XLWoMZmU/O80XwHXbNX0p3V+y7WL//erdR0On2mYh8Wo2ZmIe9MmKHe6OEc +5M2b4CApSOPL+GNZ4Vf93AxkgW3JtlCBYWIFUL73JTPBziWy1vepri0R7ktfvS7y/WC EXxd9Y+gP1YMIR57RtpPGFLt7k4LmSaPqmzhMPDLwo/X8VtIX9GVpoKGysrQA/sswM/u uZ7OU4iqaOhvfYDPy50AesDaNsxhus3H+tivLS8cqmQjHVkKw8EIEkb/CWetj/j/fm8a DXiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7ATpslQKWd63w3UD7NML8p8c0FLP9bLh9tRI+SfFzVk=; b=DqNDIGKWyp3JEaNOSljnXGKw+rtTJ8linetwGL95lqu4al0lJCdXH5BaKEJpKscsh/ IX2gHJ40oG60l9bQomIVffEH92DMvL4fk7HOyEP1bLErl2D44RzRUCVRbKZrVzA0GFEO 3ylv7O66o/pegzmAdUYIv/ITXNUmH1m+CRwXBZPEsIP5AoOLYT2l7+ycpcEsLByU4CYo peRjXtSzfFLHJ3jB9wisoDcHojZ+cwBs5fDxi8pv1IXoLIew4OmDlGi3oVVxTN1fejBR 5i2IHuHRqNQ1QGt2E3BAOKTdHRu2e0IvnbKMXvghxT80O6QykEjjrwKGANwpH2opiNaT E/YA== X-Gm-Message-State: ALKqPwcbRNXNu2QBbPfjPNoWV1JBqepDVBSZdIB4JHvyr2WQm4FK5Tap 0/D1CCdpLP8bN3jy2gUzK0Igww== X-Google-Smtp-Source: AB8JxZqWBtpgDIx+bXeZU4jUIpSWVJ5+UkeS84lXb4Yg7+9aKxqr135yl41zX7M5CE+XCmTtK/RioQ== X-Received: by 2002:a2e:997:: with SMTP id 145-v6mr10620965ljj.46.1527591016675; Tue, 29 May 2018 03:50:16 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id c6-v6sm6365977lja.22.2018.05.29.03.50.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:15 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:35 +0200 Message-Id: <20180529105011.1914-3-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [PULL v1 02/38] target-microblaze: dec_store: Use bool instead of unsigned int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Use bool instead of unsigned int to represent flags. Also, use extract32 instead of open coding the bit extract. No functional change. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a8a5eaebec..413e683aec 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1027,14 +1027,15 @@ static void dec_store(DisasContext *dc) { TCGv t, *addr, swx_addr; TCGLabel *swx_skip = NULL; - unsigned int size, rev = 0, ex = 0; + unsigned int size; + bool rev = false, ex = false; TCGMemOp mop; mop = dc->opcode & 3; size = 1 << mop; if (!dc->type_b) { - rev = (dc->ir >> 9) & 1; - ex = (dc->ir >> 10) & 1; + rev = extract32(dc->ir, 9, 1); + ex = extract32(dc->ir, 10, 1); } mop |= MO_TE; if (rev) { From patchwork Tue May 29 10:49:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921960 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IK8sKCZT"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9ZZ488Cz9ry1 for ; Tue, 29 May 2018 20:53:58 +1000 (AEST) Received: from localhost ([::1]:60093 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcGK-0003XL-5V for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:53:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcCr-0001AW-IS for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcCq-0003lZ-Mb for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:21 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:33535) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcCq-0003kn-HF for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:20 -0400 Received: by mail-wm0-x230.google.com with SMTP id x12-v6so47287717wmc.0 for ; Tue, 29 May 2018 03:50:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jRTJB7ZZ/3zTL+WIHH6mMI0kgyuPzDFACNn53TEunws=; b=IK8sKCZThIvfWq9Uw79HzpJyYdrdeaOe3xkftg+GOwXYYVew4tkKJ3acDCgIUM2PLY bO5IDAtnq03zJb2SSfwWcGjzqA4fFKrTR+gd1Y8DqpCrE+IQHSZAXgdRjo1Hm7Or2UWw h4TJqwALns1IxbuXrLKIt3jsSuDEt8f+TBPfO7QVA6CNtuMWEqD3imIsQauVv7usfmhy pL1lXQ16afK+43/R7dz+zlCDgeJqbEcE1opOlwWKuDNC2jUANnb9C8aHz1kgP4FD1yGw MKLQRtFfOmLX3D6xKLSwqn89bWqlipiGeDAI8VOK9+7tTUVBezWEISn5KnRJ05uJzYJN 9naw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jRTJB7ZZ/3zTL+WIHH6mMI0kgyuPzDFACNn53TEunws=; b=C/NO3226xJTBXoUjzE3q1qqwzcBqDl6nuZ1mq5TmCf0nIN4F+cPF0Ai4D7PgWNkLz4 RlhFw/V66ZDa6QzWb0tZRiaDgcS2Zz9ScWANzvim+jjIb/cE1A1mPLnIMy2vQTmL/28R 6VVQQtMB+QAWLJs9HKlSSWwKq3Sr4hErcPsKSynA8EXALciXryVV1fMKtcrCwoOEw7Jh shNXrGGymN8yUc9D6hYou5O8fIuZpYUDK7QbAPdaHWlaYX7suH7cevuLouAapAxzF9K3 oZx7AfFyCZyXBkTCusgFfnJB+Ib6/7/Rc3EuIVf6b5xaII4gMQicXx+WtAkXv1q4f+oT G67g== X-Gm-Message-State: ALKqPwcySv4RlXJLlALAswArholnm1nec2JvGaGl/ltgxuaTehug5xtk xtTMrrPP9UsjnQKOxoy1cAeV6g== X-Google-Smtp-Source: ADUXVKI3s7yCrwdoj92KraR0/hCEa/S1Djw/66xu3k+X17LjSgJGESG25JDOYAx8vw16oZFnWKY+SQ== X-Received: by 2002:a2e:89d7:: with SMTP id c23-v6mr10918389ljk.22.1527591019126; Tue, 29 May 2018 03:50:19 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id d5-v6sm7295629lfg.65.2018.05.29.03.50.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:17 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:36 +0200 Message-Id: <20180529105011.1914-4-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [PULL v1 03/38] target-microblaze: compute_ldst_addr: Use bool instead of int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Use bool instead of int to represent flags. No functional change. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 413e683aec..46595e6336 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -845,13 +845,13 @@ static void dec_imm(DisasContext *dc) static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) { - unsigned int extimm = dc->tb_flags & IMM_FLAG; - /* Should be set to one if r1 is used by loadstores. */ - int stackprot = 0; + bool extimm = dc->tb_flags & IMM_FLAG; + /* Should be set to true if r1 is used by loadstores. */ + bool stackprot = false; /* All load/stores use ra. */ if (dc->ra == 1 && dc->cpu->cfg.stackprot) { - stackprot = 1; + stackprot = true; } /* Treat the common cases first. */ @@ -864,7 +864,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) } if (dc->rb == 1 && dc->cpu->cfg.stackprot) { - stackprot = 1; + stackprot = true; } *t = tcg_temp_new(); From patchwork Tue May 29 10:49:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921964 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hbzMwB42"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9dp60D0z9s0W for ; Tue, 29 May 2018 20:56:46 +1000 (AEST) Received: from localhost ([::1]:60112 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcJ2-0005xh-DG for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:56:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcCs-0001B2-W7 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcCs-0003mY-AX for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:23 -0400 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:55101) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcCs-0003m2-3X for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:22 -0400 Received: by mail-wm0-x243.google.com with SMTP id f6-v6so39200773wmc.4 for ; Tue, 29 May 2018 03:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qYAZaF+5C1T/BAubKp0rEdGatli7l5tJiNqFkqUH0e8=; b=hbzMwB42nyA4jvk247zEdZ/6N1SzdpB03sSykb3CyDn70nqt4aLgFBIk1gDQMl+0t9 s5HGiT8sHfXHk8mYSHhZyZNNzKe27dPSeQ4MwlYyKg+1oa7G7KNP35ZVrBb9lQzsX9Ph PkzN7B7ROq99v+BSRvrSudfnjKHB/KOHZQbfKWXGowj18b22hh7x3k5ebDkfpegX+FsD P/Hh78fBq4jjSKKxKmtAIDS7q8g/YQI7En6rX0U9eSxb2/X42LftcGHEsd8ZicY/vu6t 1MSKJF+Fg4ny/fufNxcYSwKBi17aSfla/cklRJje4c05p79uzWLUffPXMYPBzx6B0SlJ dKGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qYAZaF+5C1T/BAubKp0rEdGatli7l5tJiNqFkqUH0e8=; b=Gi32sxDzK/ibG29lQiNIMTKrzue1Kdg4F0TzR7VXdb9UiiN19IeR3nkrLBOS5d8uDq U1vplhvetvWbo90+ulDnh+U2TePcwQe83cjvJdItZobLLCoF8EKNqqI/Ebecl9NHSSL9 U0jXe1BvylxwQa0nKNTVFBeQ/zrEEAaTN7igInUcNnBDjpeXJwbnPhAWYBK8hg7SHwrM YpJTUZ4XLAT8YVWCED3xI5QGSrI9CXKeev7CGFWdo83OhaaftPg1ys2LvBYaq6kajf+i 9iJ7KZ1gDfy1O+Ltyp+kUDSIYUV/rDsG4noLs/F44/gle0ayOMj6eQcSwJ6wCSvxLumn aJRA== X-Gm-Message-State: ALKqPwe88bz4Ki+iTjdwhnX8iLiSorqmyvPVUV4WFbGQqM5leKThxYgJ kJyqgVWDVyrCA6iE7xmjfa2WHg== X-Google-Smtp-Source: AB8JxZq4PK55JL0OYJQIXxD1c8G1yBC2q0D75I0A5+aJ26/ef1e+t9cRkR3tNZQ7E93PVSsckIAQUA== X-Received: by 2002:a2e:9d41:: with SMTP id y1-v6mr10646914ljj.112.1527591020718; Tue, 29 May 2018 03:50:20 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id j83-v6sm6331564lje.55.2018.05.29.03.50.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:19 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:37 +0200 Message-Id: <20180529105011.1914-5-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PULL v1 04/38] target-microblaze: Fallback to our latest CPU version X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Today, when running QEMU in linux-user or with boards that don't select a specific CPU version, we treat it as an invalid version and log a message. Instead, if no specific version was selected, fallback to our latest CPU version. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4dc1404800..06476f6efc 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -72,6 +72,9 @@ static const struct { {NULL, 0}, }; +/* If no specific version gets selected, default to the following. */ +#define DEFAULT_CPU_VERSION "10.0" + static void mb_cpu_set_pc(CPUState *cs, vaddr value) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); @@ -141,6 +144,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; uint8_t version_code = 0; + const char *version; int i = 0; Error *local_err = NULL; @@ -162,8 +166,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_FPU_EXC_MASK \ | 0; - for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) { - if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) { + version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; + for (i = 0; mb_cpu_lookup[i].name && version; i++) { + if (strcmp(mb_cpu_lookup[i].name, version) == 0) { version_code = mb_cpu_lookup[i].version_id; break; } From patchwork Tue May 29 10:49:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921958 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OdvR89fr"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9WN4KCZz9rxs for ; Tue, 29 May 2018 20:51:12 +1000 (AEST) Received: from localhost ([::1]:60087 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDe-0001HV-4s for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:51:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcCu-0001CJ-FY for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcCt-0003nR-Nb for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:24 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:55549) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcCt-0003md-HR for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:23 -0400 Received: by mail-wm0-x242.google.com with SMTP id a8-v6so39176742wmg.5 for ; Tue, 29 May 2018 03:50:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lU9gHChb8u2XTPHjLHseXLIYX0zoW/9g6fwRf52uqnw=; b=OdvR89fr+lgLT7ieOTk9F7EPztmqVeZqaGPFnT4/NDA4owPF88XKIpXAgfSvKrEwhi 6fpDV33IqOezj3laW1tyE0SbMtwmJy8MZV1hKARHJiPqU231ZY146EioZVYlWZCa5KKe v0QByKBJUHSPKFlF3g49Ptygx1PhkGGpXN8KB341sEk9INtJRJ1YmrHkK2UldEIPdAez a/SNrBvv8FSuMVa0qXypzTj82eA6tx9Qib7rrUvMv6J4FMDYYNxVGF7ivyT+OFEo1Hi1 INrc54KM6TNrOsJMN9e1C0mD1K161zxXzH9kG0pLM4toyWoYt8xLIpHN8tUWEFJM9vL2 CdUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lU9gHChb8u2XTPHjLHseXLIYX0zoW/9g6fwRf52uqnw=; b=fcPb2tLqZAm3YfChDBihLKAl3RXC+LHWPCGRbzXulSfJJ2HBuCofgb/qhAAVC5MhQw BLCt1BD7Z9ddfahuiC+6dbiNVufTAumn2UJTmREu1f/Bw4Mx/E7bCHJdEwoydyoiLOtD kIqOPQcDxn7Y57WYXx9bIoCcCfPN8+ccOUVaR+XX62M7NJv5X5UWm9feSXa5wtkmbGWB QIk/5VM62Isl6viqHQAfccu6Uiis3kVcReL1HbZoMxozW0XsQwfbX5N2/7LNHhEhTc3G X31Ww2flUeCdAXPdMO0ETjDT5vvk7SU977c8SeUZpCfYzj2IgXJ8cSm2IjWuMQ6HEs6X Y+lg== X-Gm-Message-State: ALKqPweN4afxGbCLdAsY9CDmPjSl2eddozAWlSIbWHDaCB5/zE6jkD5p LQ5beneu/M1dhUwgP4pP6wEfYg== X-Google-Smtp-Source: AB8JxZrL9KmgLeAVooAQRmZer2OpO9mjZTE8V6osankecjStW2fmqxYQSLD7sKuVncWqhSSACP0rCQ== X-Received: by 2002:a2e:997:: with SMTP id 145-v6mr10621205ljj.46.1527591022229; Tue, 29 May 2018 03:50:22 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id v9-v6sm7263833lfa.30.2018.05.29.03.50.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:21 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:38 +0200 Message-Id: <20180529105011.1914-6-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PULL v1 05/38] target-microblaze: Correct special register array sizes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Correct special register array sizes. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 4 ++-- target/microblaze/translate.c | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 5be71bc320..994496515f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,8 +242,8 @@ struct CPUMBState { uint32_t bimm; uint32_t imm; - uint32_t regs[33]; - uint32_t sregs[24]; + uint32_t regs[32]; + uint32_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 46595e6336..9614f15d58 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -54,7 +54,7 @@ static TCGv env_debug; static TCGv cpu_R[32]; -static TCGv cpu_SR[18]; +static TCGv cpu_SR[14]; static TCGv env_imm; static TCGv env_btaken; static TCGv env_btarget; @@ -106,8 +106,7 @@ static const char *regnames[] = static const char *special_regnames[] = { "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", - "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", - "sr16", "sr17", "sr18" + "sr8", "sr9", "sr10", "sr11", "sr12", "sr13" }; static inline void t_sync_flags(DisasContext *dc) From patchwork Tue May 29 10:49:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921962 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UNHzfIC0"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9Zj4Hh5z9s0y for ; Tue, 29 May 2018 20:54:05 +1000 (AEST) Received: from localhost ([::1]:60097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcGR-0003c4-9e for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:54:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcCw-0001Ft-5W for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcCv-0003oX-FT for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:26 -0400 Received: from mail-wr0-x22e.google.com ([2a00:1450:400c:c0c::22e]:34580) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcCv-0003o6-9V for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:25 -0400 Received: by mail-wr0-x22e.google.com with SMTP id j1-v6so24701615wrm.1 for ; Tue, 29 May 2018 03:50:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YBn3Wgah/pQdrv68LRAURNzVkLL05j2iflJyaXCqlWk=; b=UNHzfIC09MB/iw+TdRevNLvJcj9TowoOdVKCNZhugucd9MOLDhyDYMVC5dXLnJ1JBc ly/2VY8yl6LWTwVd7ZyL04lIFOnR10CTarbeu9MzFQHn4Afn1eIRDMZ0H9DMzFVdEzTL ew2NWc+agW3TkxsLjnc9HrbcMQR5+absg196YqtqSgPOo4TtTMummZkI2hV69F5fUh04 D6+VOfVFrAeUWeBAPTcKWgRvx5W+vbj3P+7ZfdnrPB8oYiwN+0KQttkIix8kxzGkmmpb TtzTOyxI15rTL0vBX4iRByCpFYcYhk1R0jpTF8JI556dhwqDP/N8esDw/bueTHV3U7v0 24GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YBn3Wgah/pQdrv68LRAURNzVkLL05j2iflJyaXCqlWk=; b=CgubJRhji11vhqRWGBwGOJGeEeHB0xS6l78Sl+5zaY2ZuIL0nfb4cFTpWkx2CbIrHC PTAlwdqEO9D7de3UqWY2Lmt6L15uuwDZ19nAWd3aAM9byjK0SHIYJdnbXmzPNOgwnZ2D M9Sqg9GSvB8U9Ir9vkgzjM1RRQ3OZnzc889eUfL6a9lH08Lgw90GNnHVwrL/doH0r2LO WB5zJUgHGn3NGMxW5QdPFlHfXnNTNxWPsfCCUqMNhvUXW0xkon9S3Ajv6LUVkMkGxTWI sjKc3hVqTnhN79vtaCjv6VVjfV1G87eSq0Z5kFQM8LYklxvORZ+qHbjH4pWjGpaUWuut cJ7A== X-Gm-Message-State: ALKqPwdeJwUnLQG1knqEQ74ObAQKmJMb7Alv4hg8ZQI8kgUwy3iWLGf1 WQ21dVEDGYxTh3jn0QakoJ3DAQ== X-Google-Smtp-Source: ADUXVKL+rJJ0PBc1j5Fx+XnWVBb07QQZ4F2Cy9iV7tPXZ4XGztdpIM38/wCMEMRdSXR0YFudMoYLuw== X-Received: by 2002:a19:a9d4:: with SMTP id s203-v6mr8953700lfe.37.1527591023891; Tue, 29 May 2018 03:50:23 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id f26-v6sm6295849lje.69.2018.05.29.03.50.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:22 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:39 +0200 Message-Id: <20180529105011.1914-7-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [PULL v1 06/38] target-microblaze: Correct the PVR array size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Correct the PVR array size, there are 13 PVR registers. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 994496515f..2304c24b7d 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -277,7 +277,7 @@ struct CPUMBState { /* These fields are preserved on reset. */ struct { - uint32_t regs[16]; + uint32_t regs[13]; } pvr; }; From patchwork Tue May 29 10:49:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921984 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="C7NC3M6h"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9rJ2grZz9s08 for ; Tue, 29 May 2018 21:05:52 +1000 (AEST) Received: from localhost ([::1]:60162 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcRp-0004tL-Ud for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:05:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36879) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcD3-0001N5-Hq for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcCy-0003q1-Gq for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:33 -0400 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:54709) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcCx-0003pO-Tg for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:28 -0400 Received: by mail-wm0-x22c.google.com with SMTP id f6-v6so39201506wmc.4 for ; Tue, 29 May 2018 03:50:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dreyb0whFGc1A0y2v/S8wQCBC+ukZBey2lPeukVAVrE=; b=C7NC3M6h3TdonhMEsPsXQU+lrak1rP3B5kmfpPK/Nvp/DzFGRuyz5t62pxOohKODEt 05DL1++WRA3PLDecsG35KONF2NT1lTw5By7zk33bNneUqcJXQt7IbiVX+Wpa7JYsw6s/ yeOfRxmsw+T+jpuCJ9TBRe4InEOPhjHgW2V8YWBrDRiZVgSkls4M8lqt52Zpj896d7F8 XlWYyurg+T7lghJGuRMKMZfapLTRBaq3UUf2h8SRIB11lXyKg978LvcROZe3xvXOO6i3 p9XEuT88N0mIWNgyh7BAuU0+P5RMdJX/RuFkNbFpLC6OmnJdqS9CodZtKw2NZTeoYLEV l5eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dreyb0whFGc1A0y2v/S8wQCBC+ukZBey2lPeukVAVrE=; b=sZNZ9yY+7q8I1cgJ3espqYEp8uFPivF4PnPSf8Ng9cjvRwb65o1YqrC93btF9y59Fs HQ1djuo3S3AQKyVE/AyEVZX+XS707WznI3YoTrVgZOwl8BxulZ3AwCPTCBiGQjT1a9dp znk35sdQ4m/0CVZaICCnIxhU1xbod/M2lqBWjHuZGXxdXKwuhCfpXifitr/Jcz+CB4kT icHVHMq390nSIhjcpfqQjZXMaYlOxMaZUi2kjEjidmEkRf7wdt1LR5qOXmslT+dG/Neb /juvVe3QYQNq4KKF6eilWqNd1dS5mKMNLgi6uO/o3j2ishrmFGl5i0rpbYlabOQww4Z3 y9HA== X-Gm-Message-State: ALKqPwc3N7ICtuWNiazHN9DufcesBzQtX5iW2HF4HX4K2knq9reSj7RX 4STsCUMwNX9CQXjZDkTSpSEk5w== X-Google-Smtp-Source: AB8JxZrcj8UkTDqjZtke14xO6NhR3ZB27mHQCmshce5ccP7+6nyOt6EdzPrp8IVCKcl7TOdsqRe1Kg== X-Received: by 2002:a2e:80c1:: with SMTP id r1-v6mr10860884ljg.85.1527591025647; Tue, 29 May 2018 03:50:25 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id q19-v6sm2893141lfa.10.2018.05.29.03.50.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:24 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:40 +0200 Message-Id: <20180529105011.1914-8-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [PULL v1 07/38] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when TCGv_i32 should be used. This is in preparation for adding 64bit addressing support. No functional change. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/helper.c | 2 +- target/microblaze/translate.c | 581 +++++++++++++++++++++--------------------- 2 files changed, 295 insertions(+), 288 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index fac6ee9263..387d4aca5a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -69,7 +69,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, /* Translate if the MMU is available and enabled. */ if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) { - target_ulong vaddr, paddr; + uint32_t vaddr, paddr; struct microblaze_mmu_lookup lu; hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9614f15d58..2e9a286af6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -52,22 +52,22 @@ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ -static TCGv env_debug; -static TCGv cpu_R[32]; -static TCGv cpu_SR[14]; -static TCGv env_imm; -static TCGv env_btaken; -static TCGv env_btarget; -static TCGv env_iflags; -static TCGv env_res_addr; -static TCGv env_res_val; +static TCGv_i32 env_debug; +static TCGv_i32 cpu_R[32]; +static TCGv_i32 cpu_SR[14]; +static TCGv_i32 env_imm; +static TCGv_i32 env_btaken; +static TCGv_i32 env_btarget; +static TCGv_i32 env_iflags; +static TCGv_i32 env_res_addr; +static TCGv_i32 env_res_val; #include "exec/gen-icount.h" /* This is the state at translation time. */ typedef struct DisasContext { MicroBlazeCPU *cpu; - target_ulong pc; + uint32_t pc; /* Decoder. */ int type_b; @@ -113,7 +113,7 @@ static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_tl(env_iflags, dc->tb_flags); + tcg_gen_movi_i32(env_iflags, dc->tb_flags); dc->synced_flags = dc->tb_flags; } } @@ -123,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) TCGv_i32 tmp = tcg_const_i32(index); t_sync_flags(dc); - tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; @@ -142,41 +142,41 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_SR[SR_PC], dest); + tcg_gen_movi_i32(cpu_SR[SR_PC], dest); tcg_gen_exit_tb((uintptr_t)dc->tb + n); } else { - tcg_gen_movi_tl(cpu_SR[SR_PC], dest); + tcg_gen_movi_i32(cpu_SR[SR_PC], dest); tcg_gen_exit_tb(0); } } -static void read_carry(DisasContext *dc, TCGv d) +static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31); + tcg_gen_shri_i32(d, cpu_SR[SR_MSR], 31); } /* * write_carry sets the carry bits in MSR based on bit 0 of v. * v[31:1] are ignored. */ -static void write_carry(DisasContext *dc, TCGv v) +static void write_carry(DisasContext *dc, TCGv_i32 v) { - TCGv t0 = tcg_temp_new(); - tcg_gen_shli_tl(t0, v, 31); - tcg_gen_sari_tl(t0, t0, 31); - tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC)); - tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], + TCGv_i32 t0 = tcg_temp_new_i32(); + tcg_gen_shli_i32(t0, v, 31); + tcg_gen_sari_i32(t0, t0, 31); + tcg_gen_andi_i32(t0, t0, (MSR_C | MSR_CC)); + tcg_gen_andi_i32(cpu_SR[SR_MSR], cpu_SR[SR_MSR], ~(MSR_C | MSR_CC)); - tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0); - tcg_temp_free(t0); + tcg_gen_or_i32(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0); + tcg_temp_free_i32(t0); } static void write_carryi(DisasContext *dc, bool carry) { - TCGv t0 = tcg_temp_new(); - tcg_gen_movi_tl(t0, carry); + TCGv_i32 t0 = tcg_temp_new_i32(); + tcg_gen_movi_i32(t0, carry); write_carry(dc, t0); - tcg_temp_free(t0); + tcg_temp_free_i32(t0); } /* True if ALU operand b is a small immediate that may deserve @@ -187,13 +187,13 @@ static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) return dc->type_b && !(dc->tb_flags & IMM_FLAG); } -static inline TCGv *dec_alu_op_b(DisasContext *dc) +static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_tl(env_imm, env_imm, dc->imm); + tcg_gen_ori_i32(env_imm, env_imm, dc->imm); else - tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm)); + tcg_gen_movi_i32(env_imm, (int32_t)((int16_t)dc->imm)); return &env_imm; } else return &cpu_R[dc->rb]; @@ -202,7 +202,7 @@ static inline TCGv *dec_alu_op_b(DisasContext *dc) static void dec_add(DisasContext *dc) { unsigned int k, c; - TCGv cf; + TCGv_i32 cf; k = dc->opcode & 4; c = dc->opcode & 2; @@ -216,15 +216,15 @@ static void dec_add(DisasContext *dc) /* k - keep carry, no need to update MSR. */ /* If rd == r0, it's a nop. */ if (dc->rd) { - tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); if (c) { /* c - Add carry into the result. */ - cf = tcg_temp_new(); + cf = tcg_temp_new_i32(); read_carry(dc, cf); - tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); + tcg_temp_free_i32(cf); } } return; @@ -232,31 +232,31 @@ static void dec_add(DisasContext *dc) /* From now on, we can assume k is zero. So we need to update MSR. */ /* Extract carry. */ - cf = tcg_temp_new(); + cf = tcg_temp_new_i32(); if (c) { read_carry(dc, cf); } else { - tcg_gen_movi_tl(cf, 0); + tcg_gen_movi_i32(cf, 0); } if (dc->rd) { - TCGv ncf = tcg_temp_new(); + TCGv_i32 ncf = tcg_temp_new_i32(); gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); write_carry(dc, ncf); - tcg_temp_free(ncf); + tcg_temp_free_i32(ncf); } else { gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); write_carry(dc, cf); } - tcg_temp_free(cf); + tcg_temp_free_i32(cf); } static void dec_sub(DisasContext *dc) { unsigned int u, cmp, k, c; - TCGv cf, na; + TCGv_i32 cf, na; u = dc->imm & 2; k = dc->opcode & 4; @@ -282,15 +282,15 @@ static void dec_sub(DisasContext *dc) /* k - keep carry, no need to update MSR. */ /* If rd == r0, it's a nop. */ if (dc->rd) { - tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); + tcg_gen_sub_i32(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); if (c) { /* c - Add carry into the result. */ - cf = tcg_temp_new(); + cf = tcg_temp_new_i32(); read_carry(dc, cf); - tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); + tcg_temp_free_i32(cf); } } return; @@ -298,30 +298,30 @@ static void dec_sub(DisasContext *dc) /* From now on, we can assume k is zero. So we need to update MSR. */ /* Extract carry. And complement a into na. */ - cf = tcg_temp_new(); - na = tcg_temp_new(); + cf = tcg_temp_new_i32(); + na = tcg_temp_new_i32(); if (c) { read_carry(dc, cf); } else { - tcg_gen_movi_tl(cf, 1); + tcg_gen_movi_i32(cf, 1); } /* d = b + ~a + c. carry defaults to 1. */ - tcg_gen_not_tl(na, cpu_R[dc->ra]); + tcg_gen_not_i32(na, cpu_R[dc->ra]); if (dc->rd) { - TCGv ncf = tcg_temp_new(); + TCGv_i32 ncf = tcg_temp_new_i32(); gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); - tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); - tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); + tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); write_carry(dc, ncf); - tcg_temp_free(ncf); + tcg_temp_free_i32(ncf); } else { gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); write_carry(dc, cf); } - tcg_temp_free(cf); - tcg_temp_free(na); + tcg_temp_free_i32(cf); + tcg_temp_free_i32(na); } static void dec_pattern(DisasContext *dc) @@ -331,7 +331,7 @@ static void dec_pattern(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && !dc->cpu->cfg.use_pcmp_instr) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } @@ -346,14 +346,14 @@ static void dec_pattern(DisasContext *dc) case 2: LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_R[dc->rd], + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); } break; case 3: LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { - tcg_gen_setcond_tl(TCG_COND_NE, cpu_R[dc->rd], + tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); } break; @@ -380,9 +380,9 @@ static void dec_and(DisasContext *dc) return; if (not) { - tcg_gen_andc_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } else - tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } static void dec_or(DisasContext *dc) @@ -394,7 +394,7 @@ static void dec_or(DisasContext *dc) LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm); if (dc->rd) - tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } static void dec_xor(DisasContext *dc) @@ -406,31 +406,31 @@ static void dec_xor(DisasContext *dc) LOG_DIS("xor r%d\n", dc->rd); if (dc->rd) - tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } -static inline void msr_read(DisasContext *dc, TCGv d) +static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_mov_tl(d, cpu_SR[SR_MSR]); + tcg_gen_mov_i32(d, cpu_SR[SR_MSR]); } -static inline void msr_write(DisasContext *dc, TCGv v) +static inline void msr_write(DisasContext *dc, TCGv_i32 v) { - TCGv t; + TCGv_i32 t; - t = tcg_temp_new(); + t = tcg_temp_new_i32(); dc->cpustate_changed = 1; /* PVR bit is not writable. */ - tcg_gen_andi_tl(t, v, ~MSR_PVR); - tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); + tcg_gen_andi_i32(t, v, ~MSR_PVR); + tcg_gen_andi_i32(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); + tcg_gen_or_i32(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); tcg_temp_free(t); } static void dec_msr(DisasContext *dc) { CPUState *cs = CPU(dc->cpu); - TCGv t0, t1; + TCGv_i32 t0, t1; unsigned int sr, to, rn; int mem_index = cpu_mmu_index(&dc->cpu->env, false); @@ -454,7 +454,7 @@ static void dec_msr(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -462,20 +462,20 @@ static void dec_msr(DisasContext *dc) if (dc->rd) msr_read(dc, cpu_R[dc->rd]); - t0 = tcg_temp_new(); - t1 = tcg_temp_new(); + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new_i32(); msr_read(dc, t0); - tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc))); + tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); if (clr) { - tcg_gen_not_tl(t1, t1); - tcg_gen_and_tl(t0, t0, t1); + tcg_gen_not_i32(t1, t1); + tcg_gen_and_i32(t0, t0, t1); } else - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_or_i32(t0, t0, t1); msr_write(dc, t0); - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4); + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); + tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc + 4); dc->is_jmp = DISAS_UPDATE; return; } @@ -483,7 +483,7 @@ static void dec_msr(DisasContext *dc) if (to) { if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -495,9 +495,9 @@ static void dec_msr(DisasContext *dc) sr &= 7; LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); if (to) - gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]); + gen_helper_mmu_write(cpu_env, tcg_const_i32(sr), cpu_R[dc->ra]); else - gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr)); + gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_i32(sr)); return; } #endif @@ -511,19 +511,21 @@ static void dec_msr(DisasContext *dc) msr_write(dc, cpu_R[dc->ra]); break; case 0x3: - tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]); + tcg_gen_mov_i32(cpu_SR[SR_EAR], cpu_R[dc->ra]); break; case 0x5: - tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]); + tcg_gen_mov_i32(cpu_SR[SR_ESR], cpu_R[dc->ra]); break; case 0x7: - tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31); + tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31); break; case 0x800: - tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr)); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, slr)); break; case 0x802: - tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr)); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, shr)); break; default: cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); @@ -534,28 +536,30 @@ static void dec_msr(DisasContext *dc) switch (sr) { case 0: - tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); break; case 1: msr_read(dc, cpu_R[dc->rd]); break; case 0x3: - tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_EAR]); break; case 0x5: - tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_ESR]); break; case 0x7: - tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_FSR]); break; case 0xb: - tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_BTR]); break; case 0x800: - tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr)); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, slr)); break; case 0x802: - tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr)); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, shr)); break; case 0x2000: case 0x2001: @@ -571,7 +575,7 @@ static void dec_msr(DisasContext *dc) case 0x200b: case 0x200c: rn = sr & 0xf; - tcg_gen_ld_tl(cpu_R[dc->rd], + tcg_gen_ld_i32(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, pvr.regs[rn])); break; default: @@ -581,20 +585,20 @@ static void dec_msr(DisasContext *dc) } if (dc->rd == 0) { - tcg_gen_movi_tl(cpu_R[0], 0); + tcg_gen_movi_i32(cpu_R[0], 0); } } /* Multiplier unit. */ static void dec_mul(DisasContext *dc) { - TCGv tmp; + TCGv_i32 tmp; unsigned int subcode; if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && !dc->cpu->cfg.use_hw_mul) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -603,7 +607,7 @@ static void dec_mul(DisasContext *dc) if (dc->type_b) { LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); - tcg_gen_mul_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); return; } @@ -612,29 +616,31 @@ static void dec_mul(DisasContext *dc) /* nop??? */ } - tmp = tcg_temp_new(); + tmp = tcg_temp_new_i32(); switch (subcode) { case 0: LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); - tcg_gen_mul_tl(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 1: LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); - tcg_gen_muls2_tl(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], + cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); - tcg_gen_mulsu2_tl(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], + cpu_R[dc->ra], cpu_R[dc->rb]); break; case 3: LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); - tcg_gen_mulu2_tl(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; default: cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); break; } - tcg_temp_free(tmp); + tcg_temp_free_i32(tmp); } /* Div unit. */ @@ -647,7 +653,7 @@ static void dec_div(DisasContext *dc) if ((dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && !dc->cpu->cfg.use_div) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } @@ -658,19 +664,19 @@ static void dec_div(DisasContext *dc) gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), cpu_R[dc->ra]); if (!dc->rd) - tcg_gen_movi_tl(cpu_R[dc->rd], 0); + tcg_gen_movi_i32(cpu_R[dc->rd], 0); } static void dec_barrel(DisasContext *dc) { - TCGv t0; + TCGv_i32 t0; unsigned int imm_w, imm_s; bool s, t, e = false, i = false; if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && !dc->cpu->cfg.use_barrel) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -709,28 +715,28 @@ static void dec_barrel(DisasContext *dc) imm_s, width); } } else { - t0 = tcg_temp_new(); + t0 = tcg_temp_new_i32(); - tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc))); - tcg_gen_andi_tl(t0, t0, 31); + tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc))); + tcg_gen_andi_i32(t0, t0, 31); if (s) { - tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); + tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); } else { if (t) { - tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); + tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); } else { - tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); + tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); } } - tcg_temp_free(t0); + tcg_temp_free_i32(t0); } } static void dec_bit(DisasContext *dc) { CPUState *cs = CPU(dc->cpu); - TCGv t0; + TCGv_i32 t0; unsigned int op; int mem_index = cpu_mmu_index(&dc->cpu->env, false); @@ -738,16 +744,16 @@ static void dec_bit(DisasContext *dc) switch (op) { case 0x21: /* src. */ - t0 = tcg_temp_new(); + t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_tl(t0, cpu_SR[SR_MSR], MSR_CC); + tcg_gen_andi_i32(t0, cpu_SR[SR_MSR], MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { - tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); - tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t0); + tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); + tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); } - tcg_temp_free(t0); + tcg_temp_free_i32(t0); break; case 0x1: @@ -759,9 +765,9 @@ static void dec_bit(DisasContext *dc) write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { if (op == 0x41) - tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); + tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); else - tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); + tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); } break; case 0x60: @@ -780,7 +786,7 @@ static void dec_bit(DisasContext *dc) LOG_DIS("wdc r%d\n", dc->ra); if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -790,7 +796,7 @@ static void dec_bit(DisasContext *dc) LOG_DIS("wic r%d\n", dc->ra); if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -799,7 +805,7 @@ static void dec_bit(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && !dc->cpu->cfg.use_pcmp_instr) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } if (dc->cpu->cfg.use_pcmp_instr) { @@ -827,22 +833,22 @@ static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_tl(env_btaken, 1); + tcg_gen_movi_i32(env_btaken, 1); } dc->jmp = JMP_INDIRECT; - tcg_gen_movi_tl(env_btarget, dc->jmp_pc); + tcg_gen_movi_i32(env_btarget, dc->jmp_pc); } } static void dec_imm(DisasContext *dc) { LOG_DIS("imm %x\n", dc->imm << 16); - tcg_gen_movi_tl(env_imm, (dc->imm << 16)); + tcg_gen_movi_i32(env_imm, (dc->imm << 16)); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; } -static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) +static inline TCGv_i32 *compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) { bool extimm = dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ @@ -866,8 +872,8 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) stackprot = true; } - *t = tcg_temp_new(); - tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]); + *t = tcg_temp_new_i32(); + tcg_gen_add_i32(*t, cpu_R[dc->ra], cpu_R[dc->rb]); if (stackprot) { gen_helper_stackprot(cpu_env, *t); @@ -879,12 +885,12 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) if (dc->imm == 0) { return &cpu_R[dc->ra]; } - *t = tcg_temp_new(); - tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm)); - tcg_gen_add_tl(*t, cpu_R[dc->ra], *t); + *t = tcg_temp_new_i32(); + tcg_gen_movi_i32(*t, (int32_t)((int16_t)dc->imm)); + tcg_gen_add_i32(*t, cpu_R[dc->ra], *t); } else { - *t = tcg_temp_new(); - tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); + *t = tcg_temp_new_i32(); + tcg_gen_add_i32(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); } if (stackprot) { @@ -895,7 +901,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) static void dec_load(DisasContext *dc) { - TCGv t, v, *addr; + TCGv_i32 t, v, *addr; unsigned int size; bool rev = false, ex = false; TCGMemOp mop; @@ -913,7 +919,7 @@ static void dec_load(DisasContext *dc) if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -939,20 +945,20 @@ static void dec_load(DisasContext *dc) 01 -> 10 10 -> 10 11 -> 00 */ - TCGv low = tcg_temp_new(); + TCGv_i32 low = tcg_temp_new_i32(); /* Force addr into the temp. */ if (addr != &t) { - t = tcg_temp_new(); - tcg_gen_mov_tl(t, *addr); + t = tcg_temp_new_i32(); + tcg_gen_mov_i32(t, *addr); addr = &t; } - tcg_gen_andi_tl(low, t, 3); - tcg_gen_sub_tl(low, tcg_const_tl(3), low); - tcg_gen_andi_tl(t, t, ~3); - tcg_gen_or_tl(t, t, low); - tcg_temp_free(low); + tcg_gen_andi_i32(low, t, 3); + tcg_gen_sub_i32(low, tcg_const_i32(3), low); + tcg_gen_andi_i32(t, t, ~3); + tcg_gen_or_i32(t, t, low); + tcg_temp_free_i32(low); break; } @@ -961,11 +967,11 @@ static void dec_load(DisasContext *dc) 10 -> 00. */ /* Force addr into the temp. */ if (addr != &t) { - t = tcg_temp_new(); - tcg_gen_xori_tl(t, *addr, 2); + t = tcg_temp_new_i32(); + tcg_gen_xori_i32(t, *addr, 2); addr = &t; } else { - tcg_gen_xori_tl(t, t, 2); + tcg_gen_xori_i32(t, t, 2); } break; default: @@ -978,11 +984,11 @@ static void dec_load(DisasContext *dc) if (ex) { /* Force addr into the temp. */ if (addr != &t) { - t = tcg_temp_new(); - tcg_gen_mov_tl(t, *addr); + t = tcg_temp_new_i32(); + tcg_gen_mov_i32(t, *addr); addr = &t; } - tcg_gen_andi_tl(t, t, ~3); + tcg_gen_andi_i32(t, t, ~3); } /* If we get a fault on a dslot, the jmpstate better be in sync. */ @@ -995,23 +1001,23 @@ static void dec_load(DisasContext *dc) * into v. If the load succeeds, we verify alignment of the * address and if that succeeds we write into the destination reg. */ - v = tcg_temp_new(); - tcg_gen_qemu_ld_tl(v, *addr, cpu_mmu_index(&dc->cpu->env, false), mop); + v = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(v, *addr, cpu_mmu_index(&dc->cpu->env, false), mop); if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { - tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); - gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd), - tcg_const_tl(0), tcg_const_tl(size - 1)); + tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); + gen_helper_memalign(cpu_env, *addr, tcg_const_i32(dc->rd), + tcg_const_i32(0), tcg_const_i32(size - 1)); } if (ex) { - tcg_gen_mov_tl(env_res_addr, *addr); - tcg_gen_mov_tl(env_res_val, v); + tcg_gen_mov_i32(env_res_addr, *addr); + tcg_gen_mov_i32(env_res_val, v); } if (dc->rd) { - tcg_gen_mov_tl(cpu_R[dc->rd], v); + tcg_gen_mov_i32(cpu_R[dc->rd], v); } - tcg_temp_free(v); + tcg_temp_free_i32(v); if (ex) { /* lwx */ /* no support for AXI exclusive so always clear C */ @@ -1019,12 +1025,12 @@ static void dec_load(DisasContext *dc) } if (addr == &t) - tcg_temp_free(t); + tcg_temp_free_i32(t); } static void dec_store(DisasContext *dc) { - TCGv t, *addr, swx_addr; + TCGv_i32 t, *addr, swx_addr; TCGLabel *swx_skip = NULL; unsigned int size; bool rev = false, ex = false; @@ -1043,7 +1049,7 @@ static void dec_store(DisasContext *dc) if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -1055,31 +1061,31 @@ static void dec_store(DisasContext *dc) sync_jmpstate(dc); addr = compute_ldst_addr(dc, &t); - swx_addr = tcg_temp_local_new(); + swx_addr = tcg_temp_local_new_i32(); if (ex) { /* swx */ - TCGv tval; + TCGv_i32 tval; /* Force addr into the swx_addr. */ - tcg_gen_mov_tl(swx_addr, *addr); + tcg_gen_mov_i32(swx_addr, *addr); addr = &swx_addr; /* swx does not throw unaligned access errors, so force alignment */ - tcg_gen_andi_tl(swx_addr, swx_addr, ~3); + tcg_gen_andi_i32(swx_addr, swx_addr, ~3); write_carryi(dc, 1); swx_skip = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, swx_addr, swx_skip); + tcg_gen_brcond_i32(TCG_COND_NE, env_res_addr, swx_addr, swx_skip); /* Compare the value loaded at lwx with current contents of the reserved location. FIXME: This only works for system emulation where we can expect this compare and the following write to be atomic. For user emulation we need to add atomicity between threads. */ - tval = tcg_temp_new(); - tcg_gen_qemu_ld_tl(tval, swx_addr, cpu_mmu_index(&dc->cpu->env, false), + tval = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tval, swx_addr, cpu_mmu_index(&dc->cpu->env, false), MO_TEUL); - tcg_gen_brcond_tl(TCG_COND_NE, env_res_val, tval, swx_skip); + tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip); write_carryi(dc, 0); - tcg_temp_free(tval); + tcg_temp_free_i32(tval); } if (rev && size != 4) { @@ -1091,20 +1097,20 @@ static void dec_store(DisasContext *dc) 01 -> 10 10 -> 10 11 -> 00 */ - TCGv low = tcg_temp_new(); + TCGv_i32 low = tcg_temp_new_i32(); /* Force addr into the temp. */ if (addr != &t) { - t = tcg_temp_new(); - tcg_gen_mov_tl(t, *addr); + t = tcg_temp_new_i32(); + tcg_gen_mov_i32(t, *addr); addr = &t; } - tcg_gen_andi_tl(low, t, 3); - tcg_gen_sub_tl(low, tcg_const_tl(3), low); - tcg_gen_andi_tl(t, t, ~3); - tcg_gen_or_tl(t, t, low); - tcg_temp_free(low); + tcg_gen_andi_i32(low, t, 3); + tcg_gen_sub_i32(low, tcg_const_i32(3), low); + tcg_gen_andi_i32(t, t, ~3); + tcg_gen_or_i32(t, t, low); + tcg_temp_free_i32(low); break; } @@ -1113,11 +1119,11 @@ static void dec_store(DisasContext *dc) 10 -> 00. */ /* Force addr into the temp. */ if (addr != &t) { - t = tcg_temp_new(); - tcg_gen_xori_tl(t, *addr, 2); + t = tcg_temp_new_i32(); + tcg_gen_xori_i32(t, *addr, 2); addr = &t; } else { - tcg_gen_xori_tl(t, t, 2); + tcg_gen_xori_i32(t, t, 2); } break; default: @@ -1125,51 +1131,52 @@ static void dec_store(DisasContext *dc) break; } } - tcg_gen_qemu_st_tl(cpu_R[dc->rd], *addr, cpu_mmu_index(&dc->cpu->env, false), mop); + tcg_gen_qemu_st_i32(cpu_R[dc->rd], *addr, + cpu_mmu_index(&dc->cpu->env, false), mop); /* Verify alignment if needed. */ if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { - tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put * the alignment checks in between the probe and the mem * access. */ - gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd), - tcg_const_tl(1), tcg_const_tl(size - 1)); + gen_helper_memalign(cpu_env, *addr, tcg_const_i32(dc->rd), + tcg_const_i32(1), tcg_const_i32(size - 1)); } if (ex) { gen_set_label(swx_skip); } - tcg_temp_free(swx_addr); + tcg_temp_free_i32(swx_addr); if (addr == &t) - tcg_temp_free(t); + tcg_temp_free_i32(t); } static inline void eval_cc(DisasContext *dc, unsigned int cc, - TCGv d, TCGv a, TCGv b) + TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { switch (cc) { case CC_EQ: - tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b); + tcg_gen_setcond_i32(TCG_COND_EQ, d, a, b); break; case CC_NE: - tcg_gen_setcond_tl(TCG_COND_NE, d, a, b); + tcg_gen_setcond_i32(TCG_COND_NE, d, a, b); break; case CC_LT: - tcg_gen_setcond_tl(TCG_COND_LT, d, a, b); + tcg_gen_setcond_i32(TCG_COND_LT, d, a, b); break; case CC_LE: - tcg_gen_setcond_tl(TCG_COND_LE, d, a, b); + tcg_gen_setcond_i32(TCG_COND_LE, d, a, b); break; case CC_GE: - tcg_gen_setcond_tl(TCG_COND_GE, d, a, b); + tcg_gen_setcond_i32(TCG_COND_GE, d, a, b); break; case CC_GT: - tcg_gen_setcond_tl(TCG_COND_GT, d, a, b); + tcg_gen_setcond_i32(TCG_COND_GT, d, a, b); break; default: cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); @@ -1177,13 +1184,13 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, } } -static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false) +static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) { TCGLabel *l1 = gen_new_label(); /* Conditional jmp. */ - tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false); - tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1); - tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true); + tcg_gen_mov_i32(cpu_SR[SR_PC], pc_false); + tcg_gen_brcondi_i32(TCG_COND_EQ, env_btaken, 0, l1); + tcg_gen_mov_i32(cpu_SR[SR_PC], pc_true); gen_set_label(l1); } @@ -1200,22 +1207,22 @@ static void dec_bcc(DisasContext *dc) if (dslot) { dc->delayed_branch = 2; dc->tb_flags |= D_FLAG; - tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), + tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), cpu_env, offsetof(CPUMBState, bimm)); } if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - tcg_gen_movi_tl(env_btarget, dc->pc + offset); + tcg_gen_movi_i32(env_btarget, dc->pc + offset); dc->jmp = JMP_DIRECT_CC; dc->jmp_pc = dc->pc + offset; } else { dc->jmp = JMP_INDIRECT; - tcg_gen_movi_tl(env_btarget, dc->pc); - tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_movi_i32(env_btarget, dc->pc); + tcg_gen_add_i32(env_btarget, env_btarget, *(dec_alu_op_b(dc))); } - eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0)); + eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_i32(0)); } static void dec_br(DisasContext *dc) @@ -1241,7 +1248,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1262,22 +1269,22 @@ static void dec_br(DisasContext *dc) if (dslot) { dc->delayed_branch = 2; dc->tb_flags |= D_FLAG; - tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), + tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), cpu_env, offsetof(CPUMBState, bimm)); } if (link && dc->rd) - tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); dc->jmp = JMP_INDIRECT; if (abs) { - tcg_gen_movi_tl(env_btaken, 1); - tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_mov_i32(env_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); if (dc->imm == 0) { if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -1290,63 +1297,63 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_DIRECT; dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); } else { - tcg_gen_movi_tl(env_btaken, 1); - tcg_gen_movi_tl(env_btarget, dc->pc); - tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(env_btarget, dc->pc); + tcg_gen_add_i32(env_btarget, env_btarget, *(dec_alu_op_b(dc))); } } } static inline void do_rti(DisasContext *dc) { - TCGv t0, t1; - t0 = tcg_temp_new(); - t1 = tcg_temp_new(); - tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1); - tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE); - tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); - - tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_tl(t1, t1, t0); + TCGv_i32 t0, t1; + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, cpu_SR[SR_MSR], 1); + tcg_gen_ori_i32(t1, cpu_SR[SR_MSR], MSR_IE); + tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + + tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); + tcg_gen_or_i32(t1, t1, t0); msr_write(dc, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t0); dc->tb_flags &= ~DRTI_FLAG; } static inline void do_rtb(DisasContext *dc) { - TCGv t0, t1; - t0 = tcg_temp_new(); - t1 = tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP); - tcg_gen_shri_tl(t0, t1, 1); - tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); - - tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_tl(t1, t1, t0); + TCGv_i32 t0, t1; + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new_i32(); + tcg_gen_andi_i32(t1, cpu_SR[SR_MSR], ~MSR_BIP); + tcg_gen_shri_i32(t0, t1, 1); + tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + + tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); + tcg_gen_or_i32(t1, t1, t0); msr_write(dc, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t0); dc->tb_flags &= ~DRTB_FLAG; } static inline void do_rte(DisasContext *dc) { - TCGv t0, t1; - t0 = tcg_temp_new(); - t1 = tcg_temp_new(); + TCGv_i32 t0, t1; + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new_i32(); - tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE); - tcg_gen_andi_tl(t1, t1, ~MSR_EIP); - tcg_gen_shri_tl(t0, t1, 1); - tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); + tcg_gen_ori_i32(t1, cpu_SR[SR_MSR], MSR_EE); + tcg_gen_andi_i32(t1, t1, ~MSR_EIP); + tcg_gen_shri_i32(t0, t1, 1); + tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); - tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_tl(t1, t1, t0); + tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); + tcg_gen_or_i32(t1, t1, t0); msr_write(dc, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t0); dc->tb_flags &= ~DRTE_FLAG; } @@ -1361,14 +1368,14 @@ static void dec_rts(DisasContext *dc) dc->delayed_branch = 2; dc->tb_flags |= D_FLAG; - tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), + tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), cpu_env, offsetof(CPUMBState, bimm)); if (i_bit) { LOG_DIS("rtid ir=%x\n", dc->ir); if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } dc->tb_flags |= DRTI_FLAG; @@ -1376,7 +1383,7 @@ static void dec_rts(DisasContext *dc) LOG_DIS("rtbd ir=%x\n", dc->ir); if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } dc->tb_flags |= DRTB_FLAG; @@ -1384,7 +1391,7 @@ static void dec_rts(DisasContext *dc) LOG_DIS("rted ir=%x\n", dc->ir); if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } dc->tb_flags |= DRTE_FLAG; @@ -1392,14 +1399,14 @@ static void dec_rts(DisasContext *dc) LOG_DIS("rts ir=%x\n", dc->ir); dc->jmp = JMP_INDIRECT; - tcg_gen_movi_tl(env_btaken, 1); - tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_add_i32(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc))); } static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK; @@ -1412,7 +1419,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && !dc->cpu->cfg.use_fpu) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -1514,7 +1521,7 @@ static void dec_null(DisasContext *dc) { if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -1533,29 +1540,29 @@ static void dec_stream(DisasContext *dc) dc->type_b ? "" : "d", dc->imm); if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } - t_id = tcg_temp_new(); + t_id = tcg_temp_new_i32(); if (dc->type_b) { - tcg_gen_movi_tl(t_id, dc->imm & 0xf); + tcg_gen_movi_i32(t_id, dc->imm & 0xf); ctrl = dc->imm >> 10; } else { - tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf); + tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf); ctrl = dc->imm >> 5; } - t_ctrl = tcg_const_tl(ctrl); + t_ctrl = tcg_const_i32(ctrl); if (dc->rd == 0) { gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); } else { gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); } - tcg_temp_free(t_id); - tcg_temp_free(t_ctrl); + tcg_temp_free_i32(t_id); + tcg_temp_free_i32(t_ctrl); } static struct decoder_info { @@ -1599,7 +1606,7 @@ static inline void decode(DisasContext *dc, uint32_t ir) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) && (dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) { - tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; } @@ -1637,7 +1644,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) struct DisasContext ctx; struct DisasContext *dc = &ctx; uint32_t page_start, org_flags; - target_ulong npc; + uint32_t npc; int num_insns; int max_insns; @@ -1680,7 +1687,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); gen_helper_debug(); } #endif @@ -1722,7 +1729,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) dc->tb_flags &= ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp == JMP_INDIRECT) { - eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc)); + eval_cond_jmp(dc, env_btarget, tcg_const_i32(dc->pc)); dc->is_jmp = DISAS_JUMP; } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); @@ -1732,7 +1739,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) TCGLabel *l1 = gen_new_label(); t_sync_flags(dc); /* Conditional jmp. */ - tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1); + tcg_gen_brcondi_i32(TCG_COND_NE, env_btaken, 0, l1); gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1755,7 +1762,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_tl(cpu_SR[SR_PC], npc); + tcg_gen_movi_i32(cpu_SR[SR_PC], npc); sync_jmpstate(dc); } else npc = dc->jmp_pc; @@ -1767,7 +1774,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_tl(cpu_SR[SR_PC], npc); + tcg_gen_movi_i32(cpu_SR[SR_PC], npc); } t_sync_flags(dc); @@ -1775,7 +1782,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { - tcg_gen_movi_tl(cpu_SR[SR_PC], npc); + tcg_gen_movi_i32(cpu_SR[SR_PC], npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1849,34 +1856,34 @@ void mb_tcg_init(void) { int i; - env_debug = tcg_global_mem_new(cpu_env, + env_debug = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, debug), "debug0"); - env_iflags = tcg_global_mem_new(cpu_env, + env_iflags = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); - env_imm = tcg_global_mem_new(cpu_env, + env_imm = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); - env_btarget = tcg_global_mem_new(cpu_env, + env_btarget = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); - env_btaken = tcg_global_mem_new(cpu_env, + env_btaken = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btaken), "btaken"); - env_res_addr = tcg_global_mem_new(cpu_env, + env_res_addr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); - env_res_val = tcg_global_mem_new(cpu_env, + env_res_val = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, res_val), "res_val"); for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { - cpu_R[i] = tcg_global_mem_new(cpu_env, + cpu_R[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, regs[i]), regnames[i]); } for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { - cpu_SR[i] = tcg_global_mem_new(cpu_env, + cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); } From patchwork Tue May 29 10:49:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921965 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="r4WIi361"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9ds63kQz9ry1 for ; Tue, 29 May 2018 20:56:49 +1000 (AEST) Received: from localhost ([::1]:60115 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcJ5-000616-E3 for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:56:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36848) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcD1-0001KZ-4x for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcCy-0003qG-Kd for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:31 -0400 Received: from mail-wm0-x232.google.com ([2a00:1450:400c:c09::232]:36578) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcCy-0003pX-EP for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:28 -0400 Received: by mail-wm0-x232.google.com with SMTP id v131-v6so20045550wma.1 for ; Tue, 29 May 2018 03:50:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OFDO64WorRhLtOjEHoVu0sDIiP8txqRKXmJIrq1zCNY=; b=r4WIi361TvSGJ7uMLIh9KKKQQU0o4usaiyITRBHFAcTXJb+AF6pZKoEhQSx9F81RIl cV07QpzwWxXS8LT5EO7q8Lu8A3waDkYKQc8VYezRSoPfa0+NHSRsU6zfRau8a4c7ZElK LSJeHVYDVztMo8TQQzGRQbgJ4SIcSGuV61lJszwbDgp6NvrfAUYwN9h9Kg6FGPUR0slU qXbThhqi1bAhdmD8oZAqm4tl0lZoWtd1tzdunAPMNz+u8UKIBUjssrxcs3B0CWkgJZmM kLtY6EzMOoyOWEMJGF13//VD/WyXE54z1Bcpz9K32LeRonwiBuONnvN3if9rrmjjDDr6 BM/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OFDO64WorRhLtOjEHoVu0sDIiP8txqRKXmJIrq1zCNY=; b=c253C7avJKGJ7CHdbaY3mD4hYhm6nVeVaMDs+y+4/vXgrsFZThEtJGeaiAtYcmK/UY +7rgE225pFoUfP7N5fEAfUkmH+F87sP4zevi1MctFHmxDW5iB964r5E6ZtO/eSawe1O4 XGTjunhWD7mhbzm00ftaWJtsPAQ3NVSFORsp5iXdUc2UwE9QeJ4Hw3vAJ/QjQX74v+Bi D9RPTQID/87vtcNwbhk5qat0ib3aaxaG1Bbhyv3EJuWY2NZrNwXWJV4QUccYm49sAQWb tapXzLIkofz5V3cPybiyyvOjgMPbXZp/J5tBontCquAlabZmEDt+ltpwqjZCA4kKPmnz /dxg== X-Gm-Message-State: ALKqPwfrFUt8KetDCjRLuCpLWgsbdITH7m5fZhk45rxuaRKnevjOPV2M ifBcyUsME5DzEScZnPKp/Nd8jA== X-Google-Smtp-Source: ADUXVKIv6yjLYruK/NM9KRl1B8Xm9u2f1vtGyEwxtZcrEVlY5w+jsfWHVgVxX8q3GLi+fcpZaJiIlA== X-Received: by 2002:a2e:8184:: with SMTP id e4-v6mr5736231ljg.93.1527591027078; Tue, 29 May 2018 03:50:27 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id u10-v6sm2260364ljh.23.2018.05.29.03.50.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:26 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:41 +0200 Message-Id: <20180529105011.1914-9-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [PULL v1 08/38] target-microblaze: Remove USE_MMU PVR checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" We already have a CPU property to control if a core has an MMU or not. Remove USE_MMU PVR checks in favor of looking at the property. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/helper.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 387d4aca5a..a9f4ca93e3 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -54,21 +54,11 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; unsigned int hit; - unsigned int mmu_available; int r = 1; int prot; - mmu_available = 0; - if (cpu->cfg.use_mmu) { - mmu_available = 1; - if ((cpu->cfg.pvr == C_PVR_FULL) && - (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { - mmu_available = 0; - } - } - /* Translate if the MMU is available and enabled. */ - if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) { + if (cpu->cfg.use_mmu && (env->sregs[SR_MSR] & MSR_VM)) { uint32_t vaddr, paddr; struct microblaze_mmu_lookup lu; From patchwork Tue May 29 10:49:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921972 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="INuOouiI"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9j50RWdz9ry1 for ; Tue, 29 May 2018 20:59:37 +1000 (AEST) Received: from localhost ([::1]:60127 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcLm-0008JP-K4 for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:59:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36853) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcD1-0001Ku-GU for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcD0-0003s0-Fl for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:31 -0400 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:35093) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcD0-0003qz-85 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:30 -0400 Received: by mail-wr0-x241.google.com with SMTP id i14-v6so24683519wre.2 for ; Tue, 29 May 2018 03:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VzigYZUet4AJDxdyrVRlaGKoOJouMbYbYJj7AAEtr9o=; b=INuOouiIlN+z2NDB8n/080A7xW5TlBa1wFeUnCQcX0B8uiTZ52rCKQvqXkfxnafRUj MLmq16+9W2y3J667+I9pFK5Qx1Uv8SiizYIyZqwx57s2b9aSwvcmqHbgdLeDMqHY582J PgCk2YGVV+R1vWSAIzL8Z9kbXhYn7Q9lko3TwXEDw/nWyFznE14ez2JzffmkD+FNFztq wTFBSOQyWbU5DK6tYIu4JPuYoRM0GAvsbx2JJOxBhPFx9eGmCbLfcTJMtvztdqDuPqqY BPZYijvkX3TxC1RclfztzUi4uuL+9DqLttG8rVqxH9YL+/YrJkQ843LIFAX2195FJKSh rpdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VzigYZUet4AJDxdyrVRlaGKoOJouMbYbYJj7AAEtr9o=; b=nLjhPO8Id+8JZygpLUpLKGMlyQshzHZInShxiSYKC6KelQRZ/m2vElN2p8gaBcJKYN pDY682jFZhY/MdsbRDI/FPg782DHQNgW8fVlppqtSwGsqouaS3VLKvzH3jZiEyngASPj JsNoZF6mJJbK9L18Qp3KLNZ4hUVbRhZeVJjCzE8ji1S3K0h0tY8ry2kcWzFOb8eupizN GhMcYdN2P4Z9PLHRqVA7OCvkSk+a0dmaKC8w9ktzTyQ+TNlc6D4z9jTsfeqL9iIYRz/a NVFJD+DjlzldQik7NDqHJzhE4O08AgC6tJdt5ChvcIdeERyZ214A8E7RBAUJ1QQflGx0 uEkw== X-Gm-Message-State: ALKqPwfDCf1DU5t03lMNqikQe9gTCB0gSO3UkACdHXzYS1O0ur+V09LF MJSzn38dhYvBHFMnU9OZlL/qTA== X-Google-Smtp-Source: ADUXVKLeIBSNXc0FV9Q94xua1BcH0J97h4PnZGbZ142rVYqxO2UldpKwCY9k3MmZvCXxlcOGHPt+VQ== X-Received: by 2002:a19:5701:: with SMTP id l1-v6mr9004980lfb.32.1527591028803; Tue, 29 May 2018 03:50:28 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id x134-v6sm419332lfd.0.2018.05.29.03.50.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:27 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:42 +0200 Message-Id: <20180529105011.1914-10-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PULL v1 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Conditionalize setting of PVR11_USE_MMU on the use_mmu CPU property, otherwise we may incorrectly advertise an MMU via PVR when the core in fact has none. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 06476f6efc..a6f1ce6549 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -201,7 +201,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) PVR5_DCACHE_WRITEBACK_MASK : 0; env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ - env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); + env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | + 16 << 17; mcc->parent_realize(dev, errp); } From patchwork Tue May 29 10:49:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rBUO9Fuv"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9Zj1P5Fz9s0W for ; Tue, 29 May 2018 20:54:05 +1000 (AEST) Received: from localhost ([::1]:60096 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcGQ-0003bE-Nm for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:54:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36869) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcD2-0001MW-Tc for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcD1-0003t3-PA for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:32 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:38742) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcD1-0003sW-JM for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:31 -0400 Received: by mail-wm0-x242.google.com with SMTP id m129-v6so39171334wmb.3 for ; Tue, 29 May 2018 03:50:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XcaBif2G1gHZNdGnfBcVzRnLzbEc47vn/TGeNHdxtBc=; b=rBUO9FuvKZ94l/8aMf2r46YfANIFxX0V5EBFJ+2QZ3F+7mhXCkRuQzr65QrzQoHfY9 dfownwHn0rzRrYjID2hYy6Gyu3beVXiuX/CdipPQprA7J6Ys5P6m+GtmgrYx6DAYiXCD WE6onTaipGjNWd28Sjvzpod34cVXEm2HXSgbVzOytJlY1doyhRnj5VnHeXbcRi7LrYbw 165tB8S11ZJUWIFtS5sbfv6MpAo2DJACpv1tafNx17C8q7RzuL1ZxPuLnO+Z7RP30cLY BMzlfouYYxytdlasXEwRrn3CUbN3dF8JCtqMD39C2i/dVlsWBTr1RXPXfGC2owI84+tI Sc/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XcaBif2G1gHZNdGnfBcVzRnLzbEc47vn/TGeNHdxtBc=; b=X8geXmR6m7a8xBehhSmVhQmK+uatrY4fAV6kjamj0WfNRnhpIzBk4QdnMDvRLsOBOE ouzdHQYoXwUHxBP2Y4BJkE8sb2gvJE9erHgucgHAC0wVTnFTY/VvQ9vKzQKQTCyyAseF KvfoYtNeMvHdNfVWphC6vkj8UZiItp93M2+Id1nMYfBB2J5Beb/CiLJQXD0pReAGEQpg zNU2Ds+SK8RzkbHdip18OOmQy73pU+/Rt8Okl8r0KblL+gN62eD8QvFBl8PxIJZR3A8Z eOPh7qASElf4KPECug0RRfoSVZi8G36iRmdytuVmXvsbE6WFo968JxnnrEcpBTENnVH2 7SLA== X-Gm-Message-State: ALKqPweaH4rbxDIXwu0lzAz0gT32WqV4jk4AHKiDUcjPe4/H/DPpNmo8 46EuCUAvC0d7FNyMvwUccBD99g== X-Google-Smtp-Source: AB8JxZoY+WS9EtTM4gxj3JU3IyEnkKPGLU5EXyxptg+YAWprYj6+KQI/FLBoKxI67gQF/oo7zwphHA== X-Received: by 2002:a2e:87d8:: with SMTP id v24-v6mr10714324ljj.69.1527591030311; Tue, 29 May 2018 03:50:30 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id u2-v6sm6408310lji.4.2018.05.29.03.50.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:29 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:43 +0200 Message-Id: <20180529105011.1914-11-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PULL v1 10/38] target-microblaze: Bypass MMU with MMU_NOMMU_IDX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a9f4ca93e3..261dcc74c7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -58,7 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int prot; /* Translate if the MMU is available and enabled. */ - if (cpu->cfg.use_mmu && (env->sregs[SR_MSR] & MSR_VM)) { + if (cpu->cfg.use_mmu && (env->sregs[SR_MSR] & MSR_VM) + && mmu_idx != MMU_NOMMU_IDX) { uint32_t vaddr, paddr; struct microblaze_mmu_lookup lu; From patchwork Tue May 29 10:49:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. 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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id a19-v6sm7338594lfi.86.2018.05.29.03.50.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:30 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:44 +0200 Message-Id: <20180529105011.1914-12-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PULL v1 11/38] target-microblaze: Make compute_ldst_addr always use a temp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Make compute_ldst_addr always use a temp. This simplifies the code a bit in preparation for adding support for 64bit addresses. No functional change. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 111 ++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 74 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2e9a286af6..2a4546ec3d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -848,7 +848,7 @@ static void dec_imm(DisasContext *dc) dc->clear_imm = 0; } -static inline TCGv_i32 *compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) +static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) { bool extimm = dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ @@ -861,47 +861,47 @@ static inline TCGv_i32 *compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) /* Treat the common cases first. */ if (!dc->type_b) { - /* If any of the regs is r0, return a ptr to the other. */ + /* If any of the regs is r0, set t to the value of the other reg. */ if (dc->ra == 0) { - return &cpu_R[dc->rb]; + tcg_gen_mov_i32(*t, cpu_R[dc->rb]); + return; } else if (dc->rb == 0) { - return &cpu_R[dc->ra]; + tcg_gen_mov_i32(*t, cpu_R[dc->ra]); + return; } if (dc->rb == 1 && dc->cpu->cfg.stackprot) { stackprot = true; } - *t = tcg_temp_new_i32(); tcg_gen_add_i32(*t, cpu_R[dc->ra], cpu_R[dc->rb]); if (stackprot) { gen_helper_stackprot(cpu_env, *t); } - return t; + return; } /* Immediate. */ if (!extimm) { if (dc->imm == 0) { - return &cpu_R[dc->ra]; + tcg_gen_mov_i32(*t, cpu_R[dc->ra]); + return; } - *t = tcg_temp_new_i32(); tcg_gen_movi_i32(*t, (int32_t)((int16_t)dc->imm)); tcg_gen_add_i32(*t, cpu_R[dc->ra], *t); } else { - *t = tcg_temp_new_i32(); tcg_gen_add_i32(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); } if (stackprot) { gen_helper_stackprot(cpu_env, *t); } - return t; + return; } static void dec_load(DisasContext *dc) { - TCGv_i32 t, v, *addr; + TCGv_i32 v, addr; unsigned int size; bool rev = false, ex = false; TCGMemOp mop; @@ -928,7 +928,8 @@ static void dec_load(DisasContext *dc) ex ? "x" : ""); t_sync_flags(dc); - addr = compute_ldst_addr(dc, &t); + addr = tcg_temp_new_i32(); + compute_ldst_addr(dc, &addr); /* * When doing reverse accesses we need to do two things. @@ -947,17 +948,10 @@ static void dec_load(DisasContext *dc) 11 -> 00 */ TCGv_i32 low = tcg_temp_new_i32(); - /* Force addr into the temp. */ - if (addr != &t) { - t = tcg_temp_new_i32(); - tcg_gen_mov_i32(t, *addr); - addr = &t; - } - - tcg_gen_andi_i32(low, t, 3); + tcg_gen_andi_i32(low, addr, 3); tcg_gen_sub_i32(low, tcg_const_i32(3), low); - tcg_gen_andi_i32(t, t, ~3); - tcg_gen_or_i32(t, t, low); + tcg_gen_andi_i32(addr, addr, ~3); + tcg_gen_or_i32(addr, addr, low); tcg_temp_free_i32(low); break; } @@ -965,14 +959,7 @@ static void dec_load(DisasContext *dc) case 2: /* 00 -> 10 10 -> 00. */ - /* Force addr into the temp. */ - if (addr != &t) { - t = tcg_temp_new_i32(); - tcg_gen_xori_i32(t, *addr, 2); - addr = &t; - } else { - tcg_gen_xori_i32(t, t, 2); - } + tcg_gen_xori_i32(addr, addr, 2); break; default: cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); @@ -982,13 +969,7 @@ static void dec_load(DisasContext *dc) /* lwx does not throw unaligned access errors, so force alignment */ if (ex) { - /* Force addr into the temp. */ - if (addr != &t) { - t = tcg_temp_new_i32(); - tcg_gen_mov_i32(t, *addr); - addr = &t; - } - tcg_gen_andi_i32(t, t, ~3); + tcg_gen_andi_i32(addr, addr, ~3); } /* If we get a fault on a dslot, the jmpstate better be in sync. */ @@ -1002,16 +983,16 @@ static void dec_load(DisasContext *dc) * address and if that succeeds we write into the destination reg. */ v = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, *addr, cpu_mmu_index(&dc->cpu->env, false), mop); + tcg_gen_qemu_ld_i32(v, addr, cpu_mmu_index(&dc->cpu->env, false), mop); if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); - gen_helper_memalign(cpu_env, *addr, tcg_const_i32(dc->rd), + gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), tcg_const_i32(0), tcg_const_i32(size - 1)); } if (ex) { - tcg_gen_mov_i32(env_res_addr, *addr); + tcg_gen_mov_i32(env_res_addr, addr); tcg_gen_mov_i32(env_res_val, v); } if (dc->rd) { @@ -1024,13 +1005,12 @@ static void dec_load(DisasContext *dc) write_carryi(dc, 0); } - if (addr == &t) - tcg_temp_free_i32(t); + tcg_temp_free_i32(addr); } static void dec_store(DisasContext *dc) { - TCGv_i32 t, *addr, swx_addr; + TCGv_i32 addr; TCGLabel *swx_skip = NULL; unsigned int size; bool rev = false, ex = false; @@ -1059,21 +1039,19 @@ static void dec_store(DisasContext *dc) t_sync_flags(dc); /* If we get a fault on a dslot, the jmpstate better be in sync. */ sync_jmpstate(dc); - addr = compute_ldst_addr(dc, &t); + /* SWX needs a temp_local. */ + addr = ex ? tcg_temp_local_new_i32() : tcg_temp_new_i32(); + compute_ldst_addr(dc, &addr); - swx_addr = tcg_temp_local_new_i32(); if (ex) { /* swx */ TCGv_i32 tval; - /* Force addr into the swx_addr. */ - tcg_gen_mov_i32(swx_addr, *addr); - addr = &swx_addr; /* swx does not throw unaligned access errors, so force alignment */ - tcg_gen_andi_i32(swx_addr, swx_addr, ~3); + tcg_gen_andi_i32(addr, addr, ~3); write_carryi(dc, 1); swx_skip = gen_new_label(); - tcg_gen_brcond_i32(TCG_COND_NE, env_res_addr, swx_addr, swx_skip); + tcg_gen_brcond_i32(TCG_COND_NE, env_res_addr, addr, swx_skip); /* Compare the value loaded at lwx with current contents of the reserved location. @@ -1081,8 +1059,8 @@ static void dec_store(DisasContext *dc) this compare and the following write to be atomic. For user emulation we need to add atomicity between threads. */ tval = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tval, swx_addr, cpu_mmu_index(&dc->cpu->env, false), - MO_TEUL); + tcg_gen_qemu_ld_i32(tval, addr, cpu_mmu_index(&dc->cpu->env, false), + MO_TEUL); tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip); write_carryi(dc, 0); tcg_temp_free_i32(tval); @@ -1099,17 +1077,10 @@ static void dec_store(DisasContext *dc) 11 -> 00 */ TCGv_i32 low = tcg_temp_new_i32(); - /* Force addr into the temp. */ - if (addr != &t) { - t = tcg_temp_new_i32(); - tcg_gen_mov_i32(t, *addr); - addr = &t; - } - - tcg_gen_andi_i32(low, t, 3); + tcg_gen_andi_i32(low, addr, 3); tcg_gen_sub_i32(low, tcg_const_i32(3), low); - tcg_gen_andi_i32(t, t, ~3); - tcg_gen_or_i32(t, t, low); + tcg_gen_andi_i32(addr, addr, ~3); + tcg_gen_or_i32(addr, addr, low); tcg_temp_free_i32(low); break; } @@ -1118,20 +1089,14 @@ static void dec_store(DisasContext *dc) /* 00 -> 10 10 -> 00. */ /* Force addr into the temp. */ - if (addr != &t) { - t = tcg_temp_new_i32(); - tcg_gen_xori_i32(t, *addr, 2); - addr = &t; - } else { - tcg_gen_xori_i32(t, t, 2); - } + tcg_gen_xori_i32(addr, addr, 2); break; default: cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); break; } } - tcg_gen_qemu_st_i32(cpu_R[dc->rd], *addr, + tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, cpu_mmu_index(&dc->cpu->env, false), mop); /* Verify alignment if needed. */ @@ -1143,17 +1108,15 @@ static void dec_store(DisasContext *dc) * the alignment checks in between the probe and the mem * access. */ - gen_helper_memalign(cpu_env, *addr, tcg_const_i32(dc->rd), + gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), tcg_const_i32(1), tcg_const_i32(size - 1)); } if (ex) { gen_set_label(swx_skip); } - tcg_temp_free_i32(swx_addr); - if (addr == &t) - tcg_temp_free_i32(t); + tcg_temp_free_i32(addr); } static inline void eval_cc(DisasContext *dc, unsigned int cc, From patchwork Tue May 29 10:49:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921971 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Uvp8jGCl"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9hy5q9zz9ry1 for ; Tue, 29 May 2018 20:59:30 +1000 (AEST) Received: from localhost ([::1]:60124 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcLg-0008Fx-FU for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:59:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcD6-0001QA-Af for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcD5-0003v2-A6 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:36 -0400 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:37012) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcD4-0003uY-O5 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:35 -0400 Received: by mail-wm0-x22d.google.com with SMTP id l1-v6so39330946wmb.2 for ; Tue, 29 May 2018 03:50:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IfQTzvo9IYvv3/ZGWT95WYfUYxPdt+5UQumn6Xxm2Eg=; b=Uvp8jGCljsuOiCneviOBLl19BstIZLxmb2QlHBF2W9dyebG9faJO8O+meOmH5T+mDj HsznUAohXXXm+bJi/gXu7CryGrb+0oRKTfMDMGM/tJssxG8EH/gpSnQ5tSFTtHJHxRHX D9EBjnVss2wRLkqZZfQesO806QUgdalSt4fvuNrnov9JMnq2oe7VN6iyJhx9n3pUGi2O Kn8dLVCtAuhcmFotrLA55UwyQFODzUEsDHn6fWAP/kuh/M4utl+tnPoaYieqmw9VImS1 NeWJ/qAIqhgcpbwMPAfS2wQf/ibETlnqdJRcQ6ruvXXctO1bQEA7JtBg6n0rMC8RHhc3 X48w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IfQTzvo9IYvv3/ZGWT95WYfUYxPdt+5UQumn6Xxm2Eg=; b=q7IGiYNPcVWDATtf6qjJpDiJRDWkhmcf66Ik8M/bVw+pJ4AlcRT5HkGCGuU2nJKGRV fGNewxFkVlvghA34dzczsJ6ZPGwy0ld5ruzmNCTtq5behmW3yPJC9TImap30Y7Vcl8As Fy1bmMNeruEtgWMwnDclrs3KzJ+cJoSXozo2FUR1aiu8yzLdVGHyXXeGaZN5svoQTSQf fFKr/rfbRfjGRm/Qdd6nUYtyaVWE8jtgNfpmT1Rdezwsx6V++awEXt8YYphPGbhErWTa QUDp55dN3zk3OjLgq0w9eH5scNeGjrqtYJLz6FWmoYn/Za65sbygQ+BxF2RBq3AZOrXz ptqg== X-Gm-Message-State: ALKqPwfNDpS++Yv1we0Qlqmb2r8+h3vxisM99yfGp2j8BS0Li8j92k1n L760Ndt/kdP8jxbSryzLqd1BWw== X-Google-Smtp-Source: AB8JxZqLWjGrvqci+yA1aROHdH+jPLicXCT2sXkOq5SxEqUpgB+npJHbKkQEALnlNDGTBrrzt2Vynw== X-Received: by 2002:a2e:2a45:: with SMTP id q66-v6mr10720411ljq.40.1527591033328; Tue, 29 May 2018 03:50:33 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id n26-v6sm6840223lfe.61.2018.05.29.03.50.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:32 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:45 +0200 Message-Id: <20180529105011.1914-13-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [PULL v1 12/38] target-microblaze: Remove pointer indirection for ld/st addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2a4546ec3d..ee17334959 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -848,7 +848,7 @@ static void dec_imm(DisasContext *dc) dc->clear_imm = 0; } -static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) +static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t) { bool extimm = dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ @@ -863,10 +863,10 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) if (!dc->type_b) { /* If any of the regs is r0, set t to the value of the other reg. */ if (dc->ra == 0) { - tcg_gen_mov_i32(*t, cpu_R[dc->rb]); + tcg_gen_mov_i32(t, cpu_R[dc->rb]); return; } else if (dc->rb == 0) { - tcg_gen_mov_i32(*t, cpu_R[dc->ra]); + tcg_gen_mov_i32(t, cpu_R[dc->ra]); return; } @@ -874,27 +874,27 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) stackprot = true; } - tcg_gen_add_i32(*t, cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_add_i32(t, cpu_R[dc->ra], cpu_R[dc->rb]); if (stackprot) { - gen_helper_stackprot(cpu_env, *t); + gen_helper_stackprot(cpu_env, t); } return; } /* Immediate. */ if (!extimm) { if (dc->imm == 0) { - tcg_gen_mov_i32(*t, cpu_R[dc->ra]); + tcg_gen_mov_i32(t, cpu_R[dc->ra]); return; } - tcg_gen_movi_i32(*t, (int32_t)((int16_t)dc->imm)); - tcg_gen_add_i32(*t, cpu_R[dc->ra], *t); + tcg_gen_movi_i32(t, (int32_t)((int16_t)dc->imm)); + tcg_gen_add_i32(t, cpu_R[dc->ra], t); } else { - tcg_gen_add_i32(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_add_i32(t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); } if (stackprot) { - gen_helper_stackprot(cpu_env, *t); + gen_helper_stackprot(cpu_env, t); } return; } @@ -929,7 +929,7 @@ static void dec_load(DisasContext *dc) t_sync_flags(dc); addr = tcg_temp_new_i32(); - compute_ldst_addr(dc, &addr); + compute_ldst_addr(dc, addr); /* * When doing reverse accesses we need to do two things. @@ -1041,7 +1041,7 @@ static void dec_store(DisasContext *dc) sync_jmpstate(dc); /* SWX needs a temp_local. */ addr = ex ? tcg_temp_local_new_i32() : tcg_temp_new_i32(); - compute_ldst_addr(dc, &addr); + compute_ldst_addr(dc, addr); if (ex) { /* swx */ TCGv_i32 tval; From patchwork Tue May 29 10:49:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. 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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id o18-v6sm7252931lfg.16.2018.05.29.03.50.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:33 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:46 +0200 Message-Id: <20180529105011.1914-14-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PULL v1 13/38] target-microblaze: Use TCGv for load/store addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Use TCGv for load/store addresses, allowing for future computation of 64-bit load/store address. No functional change. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 2 +- target/microblaze/helper.h | 4 +-- target/microblaze/op_helper.c | 11 +++--- target/microblaze/translate.c | 78 ++++++++++++++++++++++++------------------- 4 files changed, 53 insertions(+), 42 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 2304c24b7d..1593496997 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -250,7 +250,7 @@ struct CPUMBState { /* lwx/swx reserved address */ #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ - uint32_t res_addr; + target_ulong res_addr; uint32_t res_val; /* Internal flags. */ diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 71a6c0858d..ce70353936 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -29,8 +29,8 @@ DEF_HELPER_2(mmu_read, i32, env, i32) DEF_HELPER_3(mmu_write, void, env, i32, i32) #endif -DEF_HELPER_5(memalign, void, env, i32, i32, i32, i32) -DEF_HELPER_2(stackprot, void, env, i32) +DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) +DEF_HELPER_2(stackprot, void, env, tl) DEF_HELPER_2(get, i32, i32, i32) DEF_HELPER_3(put, void, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 1b4fe796e7..f5e851e38d 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -439,12 +439,14 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b) return 0; } -void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr, +void helper_memalign(CPUMBState *env, target_ulong addr, + uint32_t dr, uint32_t wr, uint32_t mask) { if (addr & mask) { qemu_log_mask(CPU_LOG_INT, - "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n", + "unaligned access addr=" TARGET_FMT_lx + " mask=%x, wr=%d dr=r%d\n", addr, mask, wr, dr); env->sregs[SR_EAR] = addr; env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ @@ -459,10 +461,11 @@ void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr, } } -void helper_stackprot(CPUMBState *env, uint32_t addr) +void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { - qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n", + qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " + TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); env->sregs[SR_EAR] = addr; env->sregs[SR_ESR] = ESR_EC_STACKPROT; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ee17334959..b36092b6fe 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,7 @@ static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 env_btarget; static TCGv_i32 env_iflags; -static TCGv_i32 env_res_addr; +static TCGv env_res_addr; static TCGv_i32 env_res_val; #include "exec/gen-icount.h" @@ -848,11 +848,12 @@ static void dec_imm(DisasContext *dc) dc->clear_imm = 0; } -static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t) +static inline void compute_ldst_addr(DisasContext *dc, TCGv t) { bool extimm = dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ bool stackprot = false; + TCGv_i32 t32; /* All load/stores use ra. */ if (dc->ra == 1 && dc->cpu->cfg.stackprot) { @@ -863,10 +864,10 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t) if (!dc->type_b) { /* If any of the regs is r0, set t to the value of the other reg. */ if (dc->ra == 0) { - tcg_gen_mov_i32(t, cpu_R[dc->rb]); + tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); return; } else if (dc->rb == 0) { - tcg_gen_mov_i32(t, cpu_R[dc->ra]); + tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]); return; } @@ -874,7 +875,10 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t) stackprot = true; } - tcg_gen_add_i32(t, cpu_R[dc->ra], cpu_R[dc->rb]); + t32 = tcg_temp_new_i32(); + tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_extu_i32_tl(t, t32); + tcg_temp_free_i32(t32); if (stackprot) { gen_helper_stackprot(cpu_env, t); @@ -882,16 +886,19 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t) return; } /* Immediate. */ + t32 = tcg_temp_new_i32(); if (!extimm) { if (dc->imm == 0) { - tcg_gen_mov_i32(t, cpu_R[dc->ra]); - return; + tcg_gen_mov_i32(t32, cpu_R[dc->ra]); + } else { + tcg_gen_movi_i32(t32, (int32_t)((int16_t)dc->imm)); + tcg_gen_add_i32(t32, cpu_R[dc->ra], t32); } - tcg_gen_movi_i32(t, (int32_t)((int16_t)dc->imm)); - tcg_gen_add_i32(t, cpu_R[dc->ra], t); } else { - tcg_gen_add_i32(t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); } + tcg_gen_extu_i32_tl(t, t32); + tcg_temp_free_i32(t32); if (stackprot) { gen_helper_stackprot(cpu_env, t); @@ -901,7 +908,8 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t) static void dec_load(DisasContext *dc) { - TCGv_i32 v, addr; + TCGv_i32 v; + TCGv addr; unsigned int size; bool rev = false, ex = false; TCGMemOp mop; @@ -928,7 +936,7 @@ static void dec_load(DisasContext *dc) ex ? "x" : ""); t_sync_flags(dc); - addr = tcg_temp_new_i32(); + addr = tcg_temp_new(); compute_ldst_addr(dc, addr); /* @@ -946,20 +954,20 @@ static void dec_load(DisasContext *dc) 01 -> 10 10 -> 10 11 -> 00 */ - TCGv_i32 low = tcg_temp_new_i32(); + TCGv low = tcg_temp_new(); - tcg_gen_andi_i32(low, addr, 3); - tcg_gen_sub_i32(low, tcg_const_i32(3), low); - tcg_gen_andi_i32(addr, addr, ~3); - tcg_gen_or_i32(addr, addr, low); - tcg_temp_free_i32(low); + tcg_gen_andi_tl(low, addr, 3); + tcg_gen_sub_tl(low, tcg_const_tl(3), low); + tcg_gen_andi_tl(addr, addr, ~3); + tcg_gen_or_tl(addr, addr, low); + tcg_temp_free(low); break; } case 2: /* 00 -> 10 10 -> 00. */ - tcg_gen_xori_i32(addr, addr, 2); + tcg_gen_xori_tl(addr, addr, 2); break; default: cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); @@ -969,7 +977,7 @@ static void dec_load(DisasContext *dc) /* lwx does not throw unaligned access errors, so force alignment */ if (ex) { - tcg_gen_andi_i32(addr, addr, ~3); + tcg_gen_andi_tl(addr, addr, ~3); } /* If we get a fault on a dslot, the jmpstate better be in sync. */ @@ -992,7 +1000,7 @@ static void dec_load(DisasContext *dc) } if (ex) { - tcg_gen_mov_i32(env_res_addr, addr); + tcg_gen_mov_tl(env_res_addr, addr); tcg_gen_mov_i32(env_res_val, v); } if (dc->rd) { @@ -1005,12 +1013,12 @@ static void dec_load(DisasContext *dc) write_carryi(dc, 0); } - tcg_temp_free_i32(addr); + tcg_temp_free(addr); } static void dec_store(DisasContext *dc) { - TCGv_i32 addr; + TCGv addr; TCGLabel *swx_skip = NULL; unsigned int size; bool rev = false, ex = false; @@ -1040,18 +1048,18 @@ static void dec_store(DisasContext *dc) /* If we get a fault on a dslot, the jmpstate better be in sync. */ sync_jmpstate(dc); /* SWX needs a temp_local. */ - addr = ex ? tcg_temp_local_new_i32() : tcg_temp_new_i32(); + addr = ex ? tcg_temp_local_new() : tcg_temp_new(); compute_ldst_addr(dc, addr); if (ex) { /* swx */ TCGv_i32 tval; /* swx does not throw unaligned access errors, so force alignment */ - tcg_gen_andi_i32(addr, addr, ~3); + tcg_gen_andi_tl(addr, addr, ~3); write_carryi(dc, 1); swx_skip = gen_new_label(); - tcg_gen_brcond_i32(TCG_COND_NE, env_res_addr, addr, swx_skip); + tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip); /* Compare the value loaded at lwx with current contents of the reserved location. @@ -1075,13 +1083,13 @@ static void dec_store(DisasContext *dc) 01 -> 10 10 -> 10 11 -> 00 */ - TCGv_i32 low = tcg_temp_new_i32(); + TCGv low = tcg_temp_new(); - tcg_gen_andi_i32(low, addr, 3); - tcg_gen_sub_i32(low, tcg_const_i32(3), low); - tcg_gen_andi_i32(addr, addr, ~3); - tcg_gen_or_i32(addr, addr, low); - tcg_temp_free_i32(low); + tcg_gen_andi_tl(low, addr, 3); + tcg_gen_sub_tl(low, tcg_const_tl(3), low); + tcg_gen_andi_tl(addr, addr, ~3); + tcg_gen_or_tl(addr, addr, low); + tcg_temp_free(low); break; } @@ -1089,7 +1097,7 @@ static void dec_store(DisasContext *dc) /* 00 -> 10 10 -> 00. */ /* Force addr into the temp. */ - tcg_gen_xori_i32(addr, addr, 2); + tcg_gen_xori_tl(addr, addr, 2); break; default: cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); @@ -1116,7 +1124,7 @@ static void dec_store(DisasContext *dc) gen_set_label(swx_skip); } - tcg_temp_free_i32(addr); + tcg_temp_free(addr); } static inline void eval_cc(DisasContext *dc, unsigned int cc, @@ -1834,7 +1842,7 @@ void mb_tcg_init(void) env_btaken = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btaken), "btaken"); - env_res_addr = tcg_global_mem_new_i32(cpu_env, + env_res_addr = tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); env_res_val = tcg_global_mem_new_i32(cpu_env, From patchwork Tue May 29 10:49:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bTWetCWR"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9mJ6sJjz9ry1 for ; Tue, 29 May 2018 21:02:24 +1000 (AEST) Received: from localhost ([::1]:60144 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcOU-0002Hj-LL for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:02:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36947) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDC-0001W8-Pq for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcD8-0003wa-2K for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:42 -0400 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:39280) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcD7-0003wP-R6 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:37 -0400 Received: by mail-wm0-x243.google.com with SMTP id f8-v6so39340388wmc.4 for ; Tue, 29 May 2018 03:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2TizWTNzqfkAMYWtiNa+uQRYByA7d/CZw1yy2cutPVo=; b=bTWetCWRJmnHA6IZtME/xt+0EULBWoVgB2B/LmV74xbBy8PmiSbojKgBwAtFV+vwMM QWuV32/a38N32CUSRJNffy4oxqs35PIhzkSY/Uqjha/CnMWVvnjuiJyvZI0oAVtndFsl Hs4kjTvZLL4KS5MwVeHNYnmuzG6pV5taR+pIAhoCcDMB9dv4UlJ/BGw9c6j/hUMo6L9X o5lHFtsSf0lAvUx+HUuC6TDWz5/ubuhfzJn4/9AoG8TmvsPB9DmFJbMbvWAK25CtSJUb lOx51ADq6Enq4EMDEALozzuVUHcZq9St/rb2tZglB+Sz8v+88MX7YS10u70/Oo7UCmLp UIHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2TizWTNzqfkAMYWtiNa+uQRYByA7d/CZw1yy2cutPVo=; b=XuZ7Xy0vI1V/oUuHUnP5PZZIJeW1UXyt7JwIe5tPNjx672VBTz8jerW0Ae/qqCfgdf Yy9GCK7AOVM00G+VisY5y/EKdQ3znsqJqAHC96qENpaEHFyPFk33FH9uLVX9h0r6LnEZ Iv7U4E7qU3g09Uluwt7x1+Zrj9RbH+ZXSXj+6pPf8Ja8VLf29nrjprrM7fNxxbjvQZsa NBZJ+sJYgmrmud/fP6+OpAXEAfgTOohHORdG0BoTirtR3a4Ewu85vBYBOYhXDf8TlZEm FYWO8ipgEaO4JaHAINa9bxDp5fQ/r2BcNDy282T2NwxMhSoT5MP/tZiZkWMe2Ae+19hx T41w== X-Gm-Message-State: ALKqPwcrc/vr0lgXrZFDXn3GTGTLKXzfc95Vq0kYhPe90uQA/GmV0qmI 47Y3mjcYc5EP/oZY9GM2Oi2KaA== X-Google-Smtp-Source: ADUXVKJuejrbSPC/s1IcOBBWVXWswfmcE+mo+/IfmNDW8OKq8ee0YuAdWBQ1BYHAsBPlsWDc8OvUkA== X-Received: by 2002:a2e:1dd9:: with SMTP id w86-v6mr4500636lje.110.1527591036493; Tue, 29 May 2018 03:50:36 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PULL v1 14/38] target-microblaze: Name special registers we support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Name special registers we support. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b36092b6fe..381f25348c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -105,8 +105,8 @@ static const char *regnames[] = static const char *special_regnames[] = { - "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", - "sr8", "sr9", "sr10", "sr11", "sr12", "sr13" + "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr", + "sr8", "sr9", "sr10", "rbtr", "sr12", "redr" }; static inline void t_sync_flags(DisasContext *dc) From patchwork Tue May 29 10:49:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. 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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id g24-v6sm6444660ljk.7.2018.05.29.03.50.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:37 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:48 +0200 Message-Id: <20180529105011.1914-16-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-devel] [PULL v1 15/38] target-microblaze: Break out trap_userspace() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Break out trap_userspace() to avoid open coding it everywhere. For privileged insns, we now always stop translation of the current insn for cores without exceptions. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 76 +++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 49 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 381f25348c..ffdb36cf94 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -179,6 +179,22 @@ static void write_carryi(DisasContext *dc, bool carry) tcg_temp_free_i32(t0); } +/* + * Returns true if the insn is illegal in userspace. + * If exceptions are enabled, an exception is raised. + */ +static bool trap_userspace(DisasContext *dc, bool cond) +{ + int mem_index = cpu_mmu_index(&dc->cpu->env, false); + bool cond_user = cond && mem_index == MMU_USER_IDX; + + if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + t_gen_raise_exception(dc, EXCP_HW_EXCP); + } + return cond_user; +} + /* True if ALU operand b is a small immediate that may deserve faster treatment. */ static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) @@ -432,7 +448,6 @@ static void dec_msr(DisasContext *dc) CPUState *cs = CPU(dc->cpu); TCGv_i32 t0, t1; unsigned int sr, to, rn; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); sr = dc->imm & ((1 << 14) - 1); to = dc->imm & (1 << 14); @@ -452,10 +467,7 @@ static void dec_msr(DisasContext *dc) return; } - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) { return; } @@ -480,13 +492,8 @@ static void dec_msr(DisasContext *dc) return; } - if (to) { - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index == MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + if (trap_userspace(dc, to)) { + return; } #if !defined(CONFIG_USER_ONLY) @@ -738,7 +745,6 @@ static void dec_bit(DisasContext *dc) CPUState *cs = CPU(dc->cpu); TCGv_i32 t0; unsigned int op; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); op = dc->ir & ((1 << 9) - 1); switch (op) { @@ -784,22 +790,12 @@ static void dec_bit(DisasContext *dc) case 0x76: /* wdc. */ LOG_DIS("wdc r%d\n", dc->ra); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index == MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + trap_userspace(dc, true); break; case 0x68: /* wic. */ LOG_DIS("wic r%d\n", dc->ra); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index == MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + trap_userspace(dc, true); break; case 0xe0: if ((dc->tb_flags & MSR_EE_FLAG) @@ -1199,7 +1195,6 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { unsigned int dslot, link, abs, mbar; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); dslot = dc->ir & (1 << 20); abs = dc->ir & (1 << 19); @@ -1254,9 +1249,7 @@ static void dec_br(DisasContext *dc) if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); if (dc->imm == 0) { - if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, true)) { return; } @@ -1331,12 +1324,15 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); i_bit = dc->ir & (1 << 21); b_bit = dc->ir & (1 << 22); e_bit = dc->ir & (1 << 23); + if (trap_userspace(dc, i_bit || b_bit || e_bit)) { + return; + } + dc->delayed_branch = 2; dc->tb_flags |= D_FLAG; tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), @@ -1344,27 +1340,12 @@ static void dec_rts(DisasContext *dc) if (i_bit) { LOG_DIS("rtid ir=%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index == MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |= DRTI_FLAG; } else if (b_bit) { LOG_DIS("rtbd ir=%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index == MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |= DRTB_FLAG; } else if (e_bit) { LOG_DIS("rted ir=%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index == MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |= DRTE_FLAG; } else LOG_DIS("rts ir=%x\n", dc->ir); @@ -1503,16 +1484,13 @@ static void dec_null(DisasContext *dc) /* Insns connected to FSL or AXI stream attached devices. */ static void dec_stream(DisasContext *dc) { - int mem_index = cpu_mmu_index(&dc->cpu->env, false); TCGv_i32 t_id, t_ctrl; int ctrl; LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put", dc->type_b ? "" : "d", dc->imm); - if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, true)) { return; } From patchwork Tue May 29 10:49:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921989 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KLtjGSSX"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9yp4dbtz9s0y for ; Tue, 29 May 2018 21:11:30 +1000 (AEST) Received: from localhost ([::1]:60199 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcXF-0000hq-5b for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:11:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDC-0001WB-Uh for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDB-0003zz-L4 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:42 -0400 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:54018) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDA-0003yh-VF for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:41 -0400 Received: by mail-wm0-x243.google.com with SMTP id a67-v6so39049824wmf.3 for ; Tue, 29 May 2018 03:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x5HdYiUdn32k2qvvqwC/pl+a6LYLObthPLNx5cVRsZo=; b=KLtjGSSX/fXvEWlPdO2z9jEhSgVr3pwG7Aq5RSd2s27QInIHHcfuXEvQhvtMMTScyK LNOFmYtM5oraQxvf5YVE8BM1NT2woJTl7NPl4biVTQFOWQLETm31cikEgLLNu89k3gBM eWJ3q7cDodG+iVqgQAuCx75X5RuvblRxTEgIfAfDnChkVWog2YCVYr3HfI+oG9y4h85g 7EpjfdIdLyNyUvS8KGbjNObVAgrGHmSua81ZQqDlVqvrC0NUu9q7OQqTWfZ/39zaa25T ml3/6MYHoNJMJ02Em52mTxaMZ/PftP1D8S8PUovT/+dFe1YnW8mRpDf69p5mvOQ6+Bx/ gsqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x5HdYiUdn32k2qvvqwC/pl+a6LYLObthPLNx5cVRsZo=; b=gpTfykf2OyQuUmBM3NpgavXYdtEA5xZFcg9xydqYh9eM89Rz6ZmQA4TUwh7WfgWdWx 6WrLuecVQqik1L4JvlvWFNnHSHdBdZw39q10YN6ggknhuzTXjUYJMJHTSinij/vs1TMG fIis+sBuxQbO7d1pVHd9uDvHV8iSiCQnKcNwxn4ll9/0zgiO3tseecmbkdhVmQrsFbmP Bp7mpr19JwugC8PkqQZEMNTt93PLV+gbjGitc6gAOVviPVu27/X4vQ5U6Go93Js6sYiK uWhMDknVJpreX+Wg42aoFKFoJjRE6pN9OZcNIfv70WaVoAGrenl5uQXGdbKPj3283x6c P1pA== X-Gm-Message-State: ALKqPwcqjYwCDvBunCLuk52XNGVUEY/GbD4dxKokfqjTL+fDWNN7hvP1 f0KNEn/8e4h5tR1dGuMANNQJMQ== X-Google-Smtp-Source: ADUXVKI2RHfz362WwaQmOhcjjw13c0s0CSDGSrFGfHoQ9GZWVtmnyPd1NtHt9Lu/h4xpIGMH6Dayyw== X-Received: by 2002:a2e:98d6:: with SMTP id s22-v6mr7336685ljj.19.1527591039585; Tue, 29 May 2018 03:50:39 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id q25-v6sm6318020ljj.68.2018.05.29.03.50.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:38 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:49 +0200 Message-Id: <20180529105011.1914-17-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PULL v1 16/38] target-microblaze: Break out trap_illegal() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Break out trap_illegal() to handle illegal operation traps. We now generally stop translation of the current insn if it's not valid. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 75 ++++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 48 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ffdb36cf94..d63226db8f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -179,6 +179,20 @@ static void write_carryi(DisasContext *dc, bool carry) tcg_temp_free_i32(t0); } +/* + * Returns true if the insn an illegal operation. + * If exceptions are enabled, an exception is raised. + */ +static bool trap_illegal(DisasContext *dc, bool cond) +{ + if (cond && (dc->tb_flags & MSR_EE_FLAG) + && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + t_gen_raise_exception(dc, EXCP_HW_EXCP); + } + return cond; +} + /* * Returns true if the insn is illegal in userspace. * If exceptions are enabled, an exception is raised. @@ -344,11 +358,8 @@ static void dec_pattern(DisasContext *dc) { unsigned int mode; - if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !dc->cpu->cfg.use_pcmp_instr) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { + return; } mode = dc->opcode & 3; @@ -602,11 +613,7 @@ static void dec_mul(DisasContext *dc) TCGv_i32 tmp; unsigned int subcode; - if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !dc->cpu->cfg.use_hw_mul) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) { return; } @@ -658,10 +665,8 @@ static void dec_div(DisasContext *dc) u = dc->imm & 2; LOG_DIS("div\n"); - if ((dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !dc->cpu->cfg.use_div) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { + return; } if (u) @@ -680,11 +685,7 @@ static void dec_barrel(DisasContext *dc) unsigned int imm_w, imm_s; bool s, t, e = false, i = false; - if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !dc->cpu->cfg.use_barrel) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) { return; } @@ -798,11 +799,8 @@ static void dec_bit(DisasContext *dc) trap_userspace(dc, true); break; case 0xe0: - if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !dc->cpu->cfg.use_pcmp_instr) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { + return; } if (dc->cpu->cfg.use_pcmp_instr) { tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); @@ -921,10 +919,7 @@ static void dec_load(DisasContext *dc) mop ^= MO_BSWAP; } - if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, size > 4)) { return; } @@ -1031,10 +1026,7 @@ static void dec_store(DisasContext *dc) mop ^= MO_BSWAP; } - if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, size > 4)) { return; } @@ -1368,11 +1360,7 @@ static void dec_fpu(DisasContext *dc) { unsigned int fpu_insn; - if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !dc->cpu->cfg.use_fpu) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) { return; } @@ -1471,10 +1459,7 @@ static void dec_fpu(DisasContext *dc) static void dec_null(DisasContext *dc) { - if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_illegal(dc, true)) { return; } qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode); @@ -1552,13 +1537,7 @@ static inline void decode(DisasContext *dc, uint32_t ir) if (dc->ir) dc->nr_nops = 0; else { - if ((dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && (dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK); LOG_DIS("nr_nops=%d\t", dc->nr_nops); dc->nr_nops++; From patchwork Tue May 29 10:49:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921966 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CvDhQHmz"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9dv063wz9ry1 for ; Tue, 29 May 2018 20:56:51 +1000 (AEST) Received: from localhost ([::1]:60114 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcJ6-00060z-Gl for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:56:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36961) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDD-0001WD-JS for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDC-000416-Nv for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:43 -0400 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]:39229) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDC-00040K-Gd for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:42 -0400 Received: by mail-wm0-x233.google.com with SMTP id f8-v6so39341022wmc.4 for ; Tue, 29 May 2018 03:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=haPNN6ycLEghWOSBgf9fgUxJqsAV1VssmBsi2JT1vUo=; b=CvDhQHmzb6kVRL3JuACjXOtBNBQBub9Kx4V6SX9FgwUNIE+mWKrFSe5jewNvx7bJpv 3FvH4oJIWi2g9V4StE/rsNQS/InkWu46QLQ1GWS8ImjNfZquWYJsxi1cAQG52fq+abKC Ypqinzg223bZqcTcg+UsUWa+jX91DoqQHE8lqvScpE3JjLShAE/joRVYEX6wKmax+rMG 6KJ6t70W9/VpZ2tJyePHKq9hLHXB9Lw3wksxZqmC8G+5kze5Oio+HWWY1PpGRWPmzKOG Q3PYRV2A/EBSePssyV2I91VKhZW2yyr/oOZd7Xj68c8oJHqne95FeTdwipLKzrdO8duV cdgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=haPNN6ycLEghWOSBgf9fgUxJqsAV1VssmBsi2JT1vUo=; b=k4JzP2BzYfSGEAkYxhuGTBgOGVrDGW+0dhSzD8xKdN73Xkmj9n6k7y1dvu3kolaex6 lZt/hrOP6blYYGSb/dw4yH7nySiSNgGeM+QWXD8x3nzFAI3ynH6uDfExo6jvWnGmUv4r QrgrpGQdMSUd4vQz8Cs7T9HoQQHzlJ0P9Vuyly7jHNKmPRQF/Yv73FKrOskdjSf3NlJy uBRc6EDO8ld10Q4OTMvQFD4O/uFehpuKoZiiRyIWAyPZr+U34lHz6cuKX0co0RIEEvVg MX0Dx93+I/wobin7sSNZ1VETDTs6v6K5Nrnfiy4D616o4k8j4zgjpfr6hvwGef7xnRes EGPA== X-Gm-Message-State: ALKqPwdWCnUyIoWHIhlYFcmYVlA+BJfCO6uEhCM9IlcBRtEjsU86loxP kO93MPx/rwsX38D7MGGlEoHfVQ== X-Google-Smtp-Source: AB8JxZoBjCR2BGcFDsBnXd0EGplEnNOVNNV5IYn9Eec4MNT5y2GaMNe0q07Rvveio5vib1Lqyb5GnQ== X-Received: by 2002:a2e:42d2:: with SMTP id h79-v6mr10769785ljf.26.1527591041118; Tue, 29 May 2018 03:50:41 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id 66-v6sm513563ljz.28.2018.05.29.03.50.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:40 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:50 +0200 Message-Id: <20180529105011.1914-18-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::233 Subject: [Qemu-devel] [PULL v1 17/38] target-microblaze: dec_msr: Use bool and extract32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Use bool and extract32 to represent the to, clr and clrset flags. No functional change. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d63226db8f..e322c82c06 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -458,17 +458,20 @@ static void dec_msr(DisasContext *dc) { CPUState *cs = CPU(dc->cpu); TCGv_i32 t0, t1; - unsigned int sr, to, rn; + unsigned int sr, rn; + bool to, clrset; - sr = dc->imm & ((1 << 14) - 1); - to = dc->imm & (1 << 14); + sr = extract32(dc->imm, 0, 14); + to = extract32(dc->imm, 14, 1); + clrset = extract32(dc->imm, 15, 1) == 0; dc->type_b = 1; - if (to) + if (to) { dc->cpustate_changed = 1; + } /* msrclr and msrset. */ - if (!(dc->imm & (1 << 15))) { - unsigned int clr = dc->ir & (1 << 16); + if (clrset) { + bool clr = extract32(dc->ir, 16, 1); LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", dc->rd, dc->imm); From patchwork Tue May 29 10:49:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921991 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZUBklRiB"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wB1K5YqSz9s0W for ; Tue, 29 May 2018 21:13:41 +1000 (AEST) Received: from localhost ([::1]:60215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcZO-0002Vb-Ev for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:13:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36984) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDF-0001WJ-3T for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDE-00042J-66 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:45 -0400 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:36638) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDD-00041q-VD for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:44 -0400 Received: by mail-wm0-x244.google.com with SMTP id v131-v6so20047731wma.1 for ; Tue, 29 May 2018 03:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iP9/dfdwQQzvrsNqx5vNhxrbYFdUnz0mglWxSwODAzI=; b=ZUBklRiBMvrRi0DexJVwdM0XChQb942M+jr1yVuBv+moN0suuiPYIu/sR8rJQY7wRF Qc97p+i5MtUVWKS1NCUSsYCLtqiz/gwwh+MaW3UPCCPDMPs/W7rZNo/Qa/0jqZo5sZnT 1rIHpFopSvH8As3EFCFT65JK53TAzZl3AF91gSbFqROwwsJ6nEoIRwKOy7XKQkYAlXdt nSE9bsEqtN/DZf8Bct/Exnw6ICuVkqS9PkbGykX8i+BnYCjsaA2ek6aAvw/CmVsBhZ/U bYwgSd9JCxO6hEPs8EvSsix/xtQTmQ25tgwV8KV37sHEIM8M+GV2/+mMxRlRXy8LQead /j8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iP9/dfdwQQzvrsNqx5vNhxrbYFdUnz0mglWxSwODAzI=; b=bTRLnmOtIQDiiP9jfGZCpX6ExaguIDXb68qJpmp92tE3b7uLDbGCbz/up/x2bNgvny JH0ITzv3cLXiaxzO33ag9U4iKerK1OPQfuJ8mfZs531Tv4SJZm8Q8upkXHSyuzOhkvFQ zH/l5GNnjbwUJWmzh6LrstbwhoksyakSEb4fxpYr40Vc7NywUdzhOk3HjtaA69KkcAn9 OqsOKXRSSH1pO3m9MO1Mu0PcAhujpf0EwV5x/7Ikuj2UavPUChNfCBZkC6d5mWwe0ajA 4xt74LXjNpViZi+BYbIZjgPVZ6FbzL7ZvxnvdIEI0KyK454Dl5GSNxn8zePJ5QaDqXfC XkIg== X-Gm-Message-State: ALKqPweSseSzkmPWQ2jcEHKe/dSF+neNrn+/kBLLfg0u1IwpXUBksars TUpOi/swp3/TsLqFikbuxWAwCw== X-Google-Smtp-Source: AB8JxZorF0rbQekqGDZTPp4pe3tIYt5AJCUPzTpTN5THXBqAgg9sLBenjqP/PSu43l77cN29zFnQKg== X-Received: by 2002:a2e:6a07:: with SMTP id f7-v6mr10699864ljc.145.1527591042655; Tue, 29 May 2018 03:50:42 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id e14-v6sm1835040ljg.78.2018.05.29.03.50.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:41 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:51 +0200 Message-Id: <20180529105011.1914-19-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PULL v1 18/38] target-microblaze: dec_msr: Reuse more code when reg-decoding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Reuse more code when decoding register numbers. No functional changes. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 38 +++++++++----------------------------- 1 file changed, 9 insertions(+), 29 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e322c82c06..6a270fbece 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -531,11 +531,9 @@ static void dec_msr(DisasContext *dc) case 1: msr_write(dc, cpu_R[dc->ra]); break; - case 0x3: - tcg_gen_mov_i32(cpu_SR[SR_EAR], cpu_R[dc->ra]); - break; - case 0x5: - tcg_gen_mov_i32(cpu_SR[SR_ESR], cpu_R[dc->ra]); + case SR_EAR: + case SR_ESR: + tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]); break; case 0x7: tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31); @@ -562,17 +560,11 @@ static void dec_msr(DisasContext *dc) case 1: msr_read(dc, cpu_R[dc->rd]); break; - case 0x3: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_EAR]); - break; - case 0x5: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_ESR]); - break; - case 0x7: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_FSR]); - break; - case 0xb: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_BTR]); + case SR_EAR: + case SR_ESR: + case SR_FSR: + case SR_BTR: + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[sr]); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -582,19 +574,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_ld_i32(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr)); break; - case 0x2000: - case 0x2001: - case 0x2002: - case 0x2003: - case 0x2004: - case 0x2005: - case 0x2006: - case 0x2007: - case 0x2008: - case 0x2009: - case 0x200a: - case 0x200b: - case 0x200c: + case 0x2000 ... 0x200c: rn = sr & 0xf; tcg_gen_ld_i32(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, pvr.regs[rn])); From patchwork Tue May 29 10:49:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CG4nFx3T"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wB3L3w9fz9s08 for ; Tue, 29 May 2018 21:15:26 +1000 (AEST) Received: from localhost ([::1]:60222 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcb5-0003iw-N8 for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:15:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36997) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDG-0001Y4-QG for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDF-00043J-U2 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:46 -0400 Received: from mail-wr0-x236.google.com ([2a00:1450:400c:c0c::236]:44546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDF-00042s-Mt for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:45 -0400 Received: by mail-wr0-x236.google.com with SMTP id y15-v6so24693169wrg.11 for ; Tue, 29 May 2018 03:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j/JijYHshyuFgdzhlDHNDCj3gS11pDBX/59HGg4E4Vc=; b=CG4nFx3TcvWDdcAgQ7GCslHOV03pKctIYrOlqiRGrlrXv1soRALgPn3AKAeTKHNpl0 wfJQ3HqTcDKpBMuI+9hwdjFRGMEgnB6tdpJq+/Z8qgXKkyXIJICeJ8FcqeDCOQ1fSxWG d2dIIQ6sjzf8kP4ZzKBPoKk0HEizycxNVP14ZD8dKstFX5R/NTCLuSW4claQuWfLT5XO /wHKBC/O7YWghi2fjhrAdSw39PiYfxYlHHldByIJ6mG7v4jMPOmkHZQ1iP4fTLr6ZHku EBifXLnj3zHl6m89XCS1S7+wySi9riH87Gq1n5+jiBlziqyUXOSwSCi+cmcaGKBl8GoD OM8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j/JijYHshyuFgdzhlDHNDCj3gS11pDBX/59HGg4E4Vc=; b=BpBVtw0rbvH+WKYlUSsqc2xEm8QpirFlAMB6roa2/0S2/tvwL7CWLtb+K0/ki80yL6 UgaVTucMJYJy6aGkAzmrqI0bTkUsMp2rFsopmwtYFmj5lPSMlE3yRkjjvC3l29N3PSBn +cLn7uZTjlu0LmbziLc6il/+b8LVw/3TKGV0sELw/F/xV54r0xiXh581F+YzsH9Zsk2n QMqfWbyyZsBD8f0VV+UdkuG0eil+jJ8lT2RAhWJs6w9lLAp9E+lug6EPCEqvgY1NOtdC EXEi5e+d5+yh2ItyTxOVgW9uStakMVSTQTYz1sM2oV8Apu55fpH0b2xDnaEP4/JQdH7p hF3g== X-Gm-Message-State: ALKqPwdjpBAv3ylvDXOR5StDwY/ZuTlQARIywAVxKniy2WW+mJrovsnZ 6jCiYDjCkUSpAWMSb7t3WWf7LQ== X-Google-Smtp-Source: ADUXVKK1fj7buw50oe8QP4j8YtNV3/BMhP0zQnk3ILXF0P6jJkVnH/rVQi4EkfhwYTCqyLzx/AgMBQ== X-Received: by 2002:a19:7383:: with SMTP id h3-v6mr8775768lfk.115.1527591044314; Tue, 29 May 2018 03:50:44 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id f26-v6sm6295994lje.69.2018.05.29.03.50.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:43 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:52 +0200 Message-Id: <20180529105011.1914-20-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [PULL v1 19/38] target-microblaze: dec_msr: Fix MTS to FSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Fix moves to FSR. Not only bit 31 is accessible. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6a270fbece..6f2cafa88a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -533,11 +533,9 @@ static void dec_msr(DisasContext *dc) break; case SR_EAR: case SR_ESR: + case SR_FSR: tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]); break; - case 0x7: - tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31); - break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr)); From patchwork Tue May 29 10:49:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921967 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mPpooJlc"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9gH548Yz9ry1 for ; Tue, 29 May 2018 20:58:03 +1000 (AEST) Received: from localhost ([::1]:60117 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcKH-0006yR-8X for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 06:58:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37024) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDN-0001d8-Ut for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDJ-00045k-8r for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:54 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:35478) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDI-000459-Tu for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:49 -0400 Received: by mail-wm0-x230.google.com with SMTP id o78-v6so39374369wmg.0 for ; Tue, 29 May 2018 03:50:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YHQxDWf8VfYPdqLlGS2XXe9sS7FE4t2sGV3PDFpw6Ao=; b=mPpooJlcceaLnrq7/w+KOsU89Cwe4o31XrZeXupZFMFSRXik4myjKMUBW7i4b53R5J 0mCj8JhjOi7WejnkUrvzUGUi/LurLcQ5mYOxNiEwYtj2RzQvuu6x1UQaOtYm/tscmt5a IcW8gvTZzvnpfzr/FE1+cILKaMj370ea4r6FO/UP+D2QrRXeHo6jvjiE20omlx73nvoh hweGUMdb0JyP6W8EOwETNz4FHxzKc8J8HpuMIrxDOsp2Uaec7NDwGGURSeQMAw59iiaJ 6f4gRfBXa+RGVRkgd8wxb9Njrq/5XMoIzmW6yAu9MUah+mIu32QE2DKkK3fO9HfNZZmr AJJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YHQxDWf8VfYPdqLlGS2XXe9sS7FE4t2sGV3PDFpw6Ao=; b=Nm0UAwWOHrCYB5nHWmnnKV5LEEa5WhXhudW8Bjasp8H70Nb+DqapjsdzP5Kt55qYGC mJEeQfrI6CFebTSWR4EIUIT73QU/Q7A9hLRDIZquIFJ9snFyu71F5msNO8gE3T991pWA pkyXy4jn97JxFZM3u+XU04VGk+kyh0j23uVll3hqHL9d+8y/311hSUnD8UI2p0VTLccY tQ9QyVwUDDv2WOGBk9QWDMtsRfvlv6XnIIB7DbqzT1AFYcaJH4Hipt0hYB50p9rPrkt5 7t87pk3oLR8BqLOYydpIhCdl5Mmyi/9tg0xNB9ZG6d+Tgm8F3+hXOAwkK3GYNh/Hd7Ak u9Xg== X-Gm-Message-State: ALKqPwexzP+5qmVN0WjkRa+/KsYHWwJLPj3puw7HxMTApT7CwzT3lRoX JLetuapyWBtaE9iKV0e437xzzQ== X-Google-Smtp-Source: ADUXVKL0GduzLTaV1lghm80E4pDrgN44KleqVWbS9OpJnAxR53PpbYwWTFN3yUUdBK9yxBD/fhbYuQ== X-Received: by 2002:a2e:4792:: with SMTP id u140-v6mr2485086lja.2.1527591045918; Tue, 29 May 2018 03:50:45 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id f67-v6sm6398141lfe.36.2018.05.29.03.50.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:44 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:53 +0200 Message-Id: <20180529105011.1914-21-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [PULL v1 20/38] target-microblaze: Make special registers 64-bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Extend special registers to 64-bits. This is in preparation for MFSE/MTSE, moves to and from extended special registers. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- linux-user/microblaze/cpu_loop.c | 4 +- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 15 ++++-- target/microblaze/mmu.c | 3 +- target/microblaze/op_helper.c | 9 ++-- target/microblaze/translate.c | 99 +++++++++++++++++++++------------------- 6 files changed, 72 insertions(+), 60 deletions(-) diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 5ffb83dea2..5af12d5b21 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -105,8 +105,8 @@ void cpu_loop(CPUMBState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; default: - printf ("Unhandled hw-exception: 0x%x\n", - env->sregs[SR_ESR] & ESR_EC_MASK); + printf("Unhandled hw-exception: 0x%" PRIx64 "\n", + env->sregs[SR_ESR] & ESR_EC_MASK); cpu_dump_state(cs, stderr, fprintf, 0); exit(EXIT_FAILURE); break; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 1593496997..215f42b384 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -243,7 +243,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; - uint32_t sregs[14]; + uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 261dcc74c7..985bdae8d1 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -143,7 +143,8 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, - "hw exception at pc=%x ear=%x esr=%x iflags=%x\n", + "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " + "esr=%" PRIx64 " iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); @@ -166,7 +167,8 @@ void mb_cpu_do_interrupt(CPUState *cs) /* was the branch immprefixed?. */ if (env->bimm) { qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=%x iflags=%x\n", + "bimm exception at pc=%" PRIx64 " " + "iflags=%x\n", env->sregs[SR_PC], env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); @@ -184,7 +186,8 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, - "exception at pc=%x ear=%x iflags=%x\n", + "exception at pc=%" PRIx64 " ear=%" PRIx64 " " + "iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); @@ -221,7 +224,8 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%x msr=%x %x iflags=%x\n", + "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " + "iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ @@ -239,7 +243,8 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=%x msr=%x %x iflags=%x\n", + "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " + "iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 9d5e6aa8a5..0019ebd18f 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -240,7 +240,8 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) i = env->mmu.regs[MMU_R_TLBX] & 0xff; if (rn == MMU_R_TLBHI) { if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) - qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%x\n", + qemu_log_mask(LOG_GUEST_ERROR, + "invalidating index %x at pc=%" PRIx64 "\n", i, env->sregs[SR_PC]); env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f5e851e38d..4dc3aff84b 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -94,16 +94,17 @@ void helper_debug(CPUMBState *env) { int i; - qemu_log("PC=%8.8x\n", env->sregs[SR_PC]); - qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n", + qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]); + qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + "debug[%x] imm=%x iflags=%x\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_EIP), - (env->sregs[SR_MSR] & MSR_IE)); + (bool)(env->sregs[SR_MSR] & MSR_EIP), + (bool)(env->sregs[SR_MSR] & MSR_IE)); for (i = 0; i < 32; i++) { qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); if ((i + 1) % 4 == 0) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6f2cafa88a..7db4bdcf09 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -54,7 +54,7 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i32 cpu_SR[14]; +static TCGv_i64 cpu_SR[14]; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 env_btarget; @@ -123,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) TCGv_i32 tmp = tcg_const_i32(index); t_sync_flags(dc); - tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; @@ -142,17 +142,18 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i32(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_SR[SR_PC], dest); tcg_gen_exit_tb((uintptr_t)dc->tb + n); } else { - tcg_gen_movi_i32(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_SR[SR_PC], dest); tcg_gen_exit_tb(0); } } static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_shri_i32(d, cpu_SR[SR_MSR], 31); + tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_shri_i32(d, d, 31); } /* @@ -161,14 +162,12 @@ static void read_carry(DisasContext *dc, TCGv_i32 d) */ static void write_carry(DisasContext *dc, TCGv_i32 v) { - TCGv_i32 t0 = tcg_temp_new_i32(); - tcg_gen_shli_i32(t0, v, 31); - tcg_gen_sari_i32(t0, t0, 31); - tcg_gen_andi_i32(t0, t0, (MSR_C | MSR_CC)); - tcg_gen_andi_i32(cpu_SR[SR_MSR], cpu_SR[SR_MSR], - ~(MSR_C | MSR_CC)); - tcg_gen_or_i32(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0); - tcg_temp_free_i32(t0); + TCGv_i64 t0 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(t0, v); + /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ + tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); + tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); + tcg_temp_free_i64(t0); } static void write_carryi(DisasContext *dc, bool carry) @@ -187,7 +186,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -203,7 +202,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -438,20 +437,21 @@ static void dec_xor(DisasContext *dc) static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_mov_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); } static inline void msr_write(DisasContext *dc, TCGv_i32 v) { - TCGv_i32 t; + TCGv_i64 t; - t = tcg_temp_new_i32(); + t = tcg_temp_new_i64(); dc->cpustate_changed = 1; /* PVR bit is not writable. */ - tcg_gen_andi_i32(t, v, ~MSR_PVR); - tcg_gen_andi_i32(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_i32(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); - tcg_temp_free(t); + tcg_gen_extu_i32_i64(t, v); + tcg_gen_andi_i64(t, t, ~MSR_PVR); + tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); + tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); + tcg_temp_free_i64(t); } static void dec_msr(DisasContext *dc) @@ -501,7 +501,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); dc->is_jmp = DISAS_UPDATE; return; } @@ -534,7 +534,7 @@ static void dec_msr(DisasContext *dc) case SR_EAR: case SR_ESR: case SR_FSR: - tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]); + tcg_gen_extu_i32_i64(cpu_SR[sr], cpu_R[dc->ra]); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -562,7 +562,7 @@ static void dec_msr(DisasContext *dc) case SR_ESR: case SR_FSR: case SR_BTR: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[sr]); + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -735,7 +735,8 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(t0, cpu_SR[SR_MSR], MSR_CC); + tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); + tcg_gen_andi_i32(t0, t0, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -966,7 +967,7 @@ static void dec_load(DisasContext *dc) tcg_gen_qemu_ld_i32(v, addr, cpu_mmu_index(&dc->cpu->env, false), mop); if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { - tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), tcg_const_i32(0), tcg_const_i32(size - 1)); } @@ -1078,7 +1079,7 @@ static void dec_store(DisasContext *dc) /* Verify alignment if needed. */ if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { - tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1124,13 +1125,13 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, } } -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) +static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i64 pc_false) { TCGLabel *l1 = gen_new_label(); /* Conditional jmp. */ - tcg_gen_mov_i32(cpu_SR[SR_PC], pc_false); + tcg_gen_mov_i64(cpu_SR[SR_PC], pc_false); tcg_gen_brcondi_i32(TCG_COND_EQ, env_btaken, 0, l1); - tcg_gen_mov_i32(cpu_SR[SR_PC], pc_true); + tcg_gen_extu_i32_i64(cpu_SR[SR_PC], pc_true); gen_set_label(l1); } @@ -1187,7 +1188,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1246,8 +1247,9 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_shri_i32(t0, cpu_SR[SR_MSR], 1); - tcg_gen_ori_i32(t1, cpu_SR[SR_MSR], MSR_IE); + tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_shri_i32(t0, t1, 1); + tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); @@ -1263,7 +1265,8 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_andi_i32(t1, cpu_SR[SR_MSR], ~MSR_BIP); + tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1281,7 +1284,8 @@ static inline void do_rte(DisasContext *dc) t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_ori_i32(t1, cpu_SR[SR_MSR], MSR_EE); + tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1331,7 +1335,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_FPU); + tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK; @@ -1596,7 +1600,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); gen_helper_debug(); } #endif @@ -1638,7 +1642,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) dc->tb_flags &= ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp == JMP_INDIRECT) { - eval_cond_jmp(dc, env_btarget, tcg_const_i32(dc->pc)); + eval_cond_jmp(dc, env_btarget, tcg_const_i64(dc->pc)); dc->is_jmp = DISAS_JUMP; } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); @@ -1671,7 +1675,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i32(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_SR[SR_PC], npc); sync_jmpstate(dc); } else npc = dc->jmp_pc; @@ -1683,7 +1687,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i32(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_SR[SR_PC], npc); } t_sync_flags(dc); @@ -1691,7 +1695,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { - tcg_gen_movi_i32(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_SR[SR_PC], npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1741,17 +1745,18 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, if (!env || !f) return; - cpu_fprintf(f, "IN: PC=%x %s\n", + cpu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); - cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n", + cpu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + "debug=%x imm=%x iflags=%x fsr=%" PRIx64 "\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_EIP), - (env->sregs[SR_MSR] & MSR_IE)); + (bool)(env->sregs[SR_MSR] & MSR_EIP), + (bool)(env->sregs[SR_MSR] & MSR_IE)); for (i = 0; i < 32; i++) { cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); @@ -1792,7 +1797,7 @@ void mb_tcg_init(void) regnames[i]); } for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { - cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, + cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); } From patchwork Tue May 29 10:49:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921985 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sWKGREAV"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9sQ1Vrqz9s08 for ; Tue, 29 May 2018 21:06:48 +1000 (AEST) Received: from localhost ([::1]:60168 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcSg-0005cm-L8 for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:06:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDO-0001dL-5V for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDK-00046n-HJ for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:54 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:51245) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDK-00046D-AY for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:50 -0400 Received: by mail-wm0-x230.google.com with SMTP id r15-v6so11622058wmc.1 for ; Tue, 29 May 2018 03:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QxHPRphfrp1A4BJf131arXzkiGzlE+tsmTlHEJslYYc=; b=sWKGREAV66jhW3i+sf8pvFnjoAw9nJwP+FKyahzxWN9CD/QgekaptMG2rax1myTxLj oWRTNgfcuinGKN557orgRVZHCQ9/09VmlWokamwrotHDzs4Kup5Hh/RwPeKqknAIGv4P Yr5Z/HMNb302jf66GSwtnVfRNxO87tL2DiNf+SIYwjEq0DTQScqWtLSg+ZwkwmXZh1gj lIRlgeuNg3O53TNB+xzjMAmvo8W+D1dvp3AM/8ahtdTPe3EP+UoFxcufuo9etumJaicP RM4/bXXI6/QA1rEil54ioz0edTbuVBU6scrfSSZaVTysRtIH2+rBT6BVk+YpNCVrf4gj Lj7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QxHPRphfrp1A4BJf131arXzkiGzlE+tsmTlHEJslYYc=; b=J+MYepGIi6K6uuiRWBXG2NLXZxV6K8jZ7mCXQdjUMMOxtZWYyG1go9YcAlZ3ddAE+7 LLsNYtzAtC0UgotMMgxFhmnikWQqb2ecW7mp9/K2akfEPxDoa3fB4ZyYPa5+XoD4znKz si/OkuPJ+N5mXqMRCUQPYtB3w4tL6Ykk518MNg1yr7aRDOgdS9nSW0xO5m4Y55bFT2k5 7KrfOHNUUQw1aTVFPHc889h2wGW7lmtFrV/NARvf2Bvmoqfl37bRmXaFxF8BZnerC9Rc jtQbIzigc5qqRIeXujBoeG7qgnyLq72E9Ea2EUC5CeB+hS1C1L87Fqsqp8xqE5lEkgKH 4Mrw== X-Gm-Message-State: ALKqPweqP1fYekbtPCOLBmnhyLej7R3kjECPKI5/fXC0A+BU/8yBycF2 bw2d4pde5QDw5/hFo2ouhfVmDQ== X-Google-Smtp-Source: AB8JxZrQ35MlXs6b7DSR0MupKxCJZJ2TyVv9l3gAFBm3b9//XhudUiZeYdI/Nm/MshLl4tgouKeORw== X-Received: by 2002:a2e:5559:: with SMTP id j86-v6mr10811242ljb.147.1527591048982; Tue, 29 May 2018 03:50:48 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id f67-v6sm6398151lfe.36.2018.05.29.03.50.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:47 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:54 +0200 Message-Id: <20180529105011.1914-22-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [PULL v1 21/38] target-microblaze: Setup for 64bit addressing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Setup MicroBlaze builds for 64bit addressing. No functional change since the translator does not yet emit 64bit addresses. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- configure | 1 + target/microblaze/cpu.h | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/configure b/configure index a8498ab393..a6a4616c3e 100755 --- a/configure +++ b/configure @@ -6844,6 +6844,7 @@ case "$target_name" in microblaze|microblazeel) TARGET_ARCH=microblaze bflt="yes" + echo "TARGET_ABI32=y" >> $config_target_mak ;; mips|mipsel) TARGET_ARCH=mips diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 215f42b384..b631b7dc4c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -23,7 +23,7 @@ #include "qemu-common.h" #include "cpu-qom.h" -#define TARGET_LONG_BITS 32 +#define TARGET_LONG_BITS 64 #define CPUArchState struct CPUMBState @@ -340,8 +340,8 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU From patchwork Tue May 29 10:49:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. 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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id 141-v6sm6313490ljf.29.2018.05.29.03.50.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:51 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:56 +0200 Message-Id: <20180529105011.1914-24-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22a Subject: [Qemu-devel] [PULL v1 23/38] target-microblaze: Implement MFSE EAR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Implement MFSE EAR to enable access to the upper part of EAR. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 504db88890..7475003847 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -459,7 +459,7 @@ static void dec_msr(DisasContext *dc) CPUState *cs = CPU(dc->cpu); TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset; + bool to, clrset, extended; sr = extract32(dc->imm, 0, 14); to = extract32(dc->imm, 14, 1); @@ -467,6 +467,9 @@ static void dec_msr(DisasContext *dc) dc->type_b = 1; if (to) { dc->cpustate_changed = 1; + extended = extract32(dc->imm, 24, 1); + } else { + extended = extract32(dc->imm, 19, 1); } /* msrclr and msrset. */ @@ -559,6 +562,10 @@ static void dec_msr(DisasContext *dc) msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: + if (extended) { + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); + break; + } case SR_ESR: case SR_FSR: case SR_BTR: From patchwork Tue May 29 10:49:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921995 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SxHvRIyG"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wB5m66XTz9s08 for ; Tue, 29 May 2018 21:17:31 +1000 (AEST) Received: from localhost ([::1]:60233 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcd6-00054i-AA for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:17:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37059) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDQ-0001fC-5b for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDP-0004AK-DI for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:56 -0400 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:42383) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDP-0004A5-66 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:55 -0400 Received: by mail-wr0-x244.google.com with SMTP id w10-v6so24707564wrk.9 for ; Tue, 29 May 2018 03:50:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PuhOytwb0WLmtnwVlDs0IWCCrXihpIuNF/JyaLK6K90=; b=SxHvRIyGxjby+SMWzoBwZBknlN+H8Sd0aAtxPxKNy45nBUFCQrwZ3S4eGr9KwEHbA2 avRlo6cvOTmskxtm84LbOg3GzLghwQudvXpBtBaLhmPp3kLiY2h3sMNsPSFsm/NoR9/5 D25J6xYyryoZf6wDtVYoF6v2jFQyzdsOZXaX7XtYmhSH75zEUG69ACTOtN2PCel7vybs NujNZTq/rc5nj7wflnoiKjQ/9PQWeyhEyfqVRwmvjS9NV5o+1Eh2CQkqBDw9rBApPEIy B2MVobPmamtCAY6pZ4vVnCZGBghOrS63s0cc3+z/OH0Jmy6CaiMH+cTtXOYFe3DI4PNM 2kPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PuhOytwb0WLmtnwVlDs0IWCCrXihpIuNF/JyaLK6K90=; b=RCslsXgUqZRE3bJgNm5XDnEaWDs7BFaGpXVBIbur+TGSmPSdp525ckX+v6cyuT66xv bat/UYnTkPvsBiC8Rg5lHQxuuQMJ1nwEDY6lXT24NH+596wt45l5FTL4WxhxKxfBSu/y 2q221VAHutU0vRxC0Xa/FssEGGxQ3fVLbZbZThRO4X67PgAxTj/ifb1qIGsLeMQuDqpk lU+M2quC+r0DkBVeM9lnGPJAMYdpee682OyEMH55Y6QSXYnTYThkCC2GDO0908jJpBYZ e1RqtfbpAYWPOtWcaNm2Ke2foRoEKJCzPWf8MXJ0YE4SgB6gi1bFFEmHsyysOwSNAMkX ht5Q== X-Gm-Message-State: ALKqPwe5lN1C9Vp5gVCH9dsQNsJE3olZLEz1oO62OVrFriTVQzeAs2ex 8OuCPfIQhxWsSh+PUDli1KmZqw== X-Google-Smtp-Source: ADUXVKLvwzjypIWOwDxoX4NvhfhURfgGF8hGHqhn6mXuJRlM5SqEyC7QGKLujr1xGHbtEPmpHZ1p9w== X-Received: by 2002:a19:7b11:: with SMTP id w17-v6mr8981262lfc.103.1527591053777; Tue, 29 May 2018 03:50:53 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id v3-v6sm6402988ljj.71.2018.05.29.03.50.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:52 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:57 +0200 Message-Id: <20180529105011.1914-25-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PULL v1 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add a R_TBLX_MISS MASK and SHIFT macros. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/mmu.c | 5 +++-- target/microblaze/mmu.h | 4 ++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 0019ebd18f..f4a4c339c9 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -292,8 +292,9 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false)); if (hit) { env->mmu.regs[MMU_R_TLBX] = lu.idx; - } else - env->mmu.regs[MMU_R_TLBX] |= 0x80000000; + } else { + env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK; + } break; } default: diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 3b7a9983d5..113539c6e9 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -54,6 +54,10 @@ #define TLB_M 0x00000002 /* Memory is coherent */ #define TLB_G 0x00000001 /* Memory is guarded from prefetch */ +/* TLBX */ +#define R_TBLX_MISS_SHIFT 31 +#define R_TBLX_MISS_MASK (1U << R_TBLX_MISS_SHIFT) + #define TLB_ENTRIES 64 struct microblaze_mmu From patchwork Tue May 29 10:49:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921997 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hokdvz40"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wB8D5GHSz9s08 for ; Tue, 29 May 2018 21:19:40 +1000 (AEST) Received: from localhost ([::1]:60240 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcfC-0006Gk-CQ for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:19:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37073) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDR-0001gr-MJ for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDQ-0004Aj-TY for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:57 -0400 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:53882) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDQ-0004AT-Mn for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:56 -0400 Received: by mail-wm0-x22d.google.com with SMTP id a67-v6so39051780wmf.3 for ; Tue, 29 May 2018 03:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rlntQFPuALqAogiNUQHM/vA4JB+rnCtH9f/W9D2BGzM=; b=hokdvz402+2PLfYX6GSSuL5dam0mLZD3N1ysjBKo9nsSuIIziFmRogpgB+Ml788J0/ ld2lb/2ZJ63ct9AOV5fvagEM4JFCtKBarD8wNEaSISAnn+MSpujkQrBbRTFvtVEg2IGD H9wdRnlxfFJ09B6DzkuU8VX//qDPfE0GFwZshifPYM5P0W1GOyCitCOOLbNQgb3R8Sya rC3f3DaDTxqDM8CG27muNdqskhKeA47eUETyh10wg5ZBp3WUyPjG/YYlf/drAsLDGXYH KS5pa0CztDfkJQRgN9/faQP4nuc2QVsoHrZEGZ/9tL9EqANzaHrJqKmsavcw7G/fjXU2 pXUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rlntQFPuALqAogiNUQHM/vA4JB+rnCtH9f/W9D2BGzM=; b=c5edEdDv9wZKtfpdKIqgZg00p2cEXV4Qr/CMwx3xLV9peMuosunf5vq7p3Tf9jeY7R 3iFv0HFQCXWH2emUpiMhuRHQGLVOYmimIq0y2p1UvCInLr8nsveK57u7ZBCvFoLsPxEd L8p57zJExXfj3Pc3Am/F5dYTWmikKg4O/opMq9PfgZ4dTF/e4gug4fhvtiBq2G9fZqV2 6BmFHsBX6+AhDEl8e1dcYL7R2DSFc6+Fogt0J7zGGccEoSfwPJnvsBqMsvl6LYDaG2Pq 9FGYGJTIB4scuPMqD2trPQzV/EXK8LUGM9IEZ3m6bWkiPo/qjliXoBiQycWUzkU+0L1a pB5w== X-Gm-Message-State: ALKqPwemswZuyLyvBDABoQop2kULzr5ZE32aCR25f3xQZg/k3O9sEDPQ OZb5jBSrHRlf3zUpjkv3Wqv20w== X-Google-Smtp-Source: ADUXVKJvT7AEGx047DLUcLvESRFOz895EsoGYX5o8Efg9v304url4NEPldCaTj3DL78YXsYkKiCDcg== X-Received: by 2002:a2e:1947:: with SMTP id p68-v6mr10726991lje.114.1527591055364; Tue, 29 May 2018 03:50:55 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id u2-v6sm6408510lji.4.2018.05.29.03.50.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:54 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:58 +0200 Message-Id: <20180529105011.1914-26-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [PULL v1 25/38] target-microblaze: mmu: Remove unused register state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add explicit handling for MMU_R_TLBX and log accesses to invalid MMU registers. We can now remove the state for all regs but PID, ZPR and TLBX (0 - 2). Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Edgar E. Iglesias --- target/microblaze/mmu.c | 7 +++++-- target/microblaze/mmu.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index f4a4c339c9..231803ceea 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -211,11 +211,14 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) } r = env->mmu.regs[rn]; break; + case MMU_R_TLBX: + r = env->mmu.regs[rn]; + break; case MMU_R_TLBSX: qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); break; default: - r = env->mmu.regs[rn]; + qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); break; } D(qemu_log("%s rn=%d=%x\n", __func__, rn, r)); @@ -298,7 +301,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) break; } default: - env->mmu.regs[rn] = v; + qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); break; } } diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 113539c6e9..624becfded 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -67,7 +67,7 @@ struct microblaze_mmu /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ uint8_t tids[TLB_ENTRIES]; /* Control flops. */ - uint32_t regs[8]; + uint32_t regs[3]; int c_mmu; int c_mmu_tlb_access; From patchwork Tue May 29 10:49:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921976 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aUbFtgF7"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9kS3cgdz9ry1 for ; Tue, 29 May 2018 21:00:48 +1000 (AEST) Received: from localhost ([::1]:60131 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcMw-0000yz-4A for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:00:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37090) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDT-0001j2-Np for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDS-0004CB-GB for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:59 -0400 Received: from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e]:54720) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDS-0004B6-9U for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:58 -0400 Received: by mail-wm0-x22e.google.com with SMTP id f6-v6so39205198wmc.4 for ; Tue, 29 May 2018 03:50:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qX1PEmeLBFPGq2zdwN6kiMMwoESHL+lKVoMVf6OgQ5U=; b=aUbFtgF7BWdDrhO6FP6LLMgvrVZmuXSvnuv8SAw95dJWB2WqmiXCDW+bFjNVJzYTth kSMTl5NKW+hoi4+0SSVgeVSdSNTCMrKpcih4sGKaMxUOf03X3+xmroihbAUgpLhk135Y pmjM0igZh5lVvxZ3yPmouNSmn6v4Pd8AYhnI2q7eYEOaEVF/c4mz5kitmy8p8n4jo8V+ 7+htBZkvzBlKjFoqrtTp90tsr2iN8YAlmcyuWXoXUi2PbJIC927rS+mICgw49KpjPztD W0lpS3fcmlmRL30k65AJTi2kYgGx0hAWI/H2FAaa9kZ3jrwqNI0+9x2+ZfUGPZJuohqb W+gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qX1PEmeLBFPGq2zdwN6kiMMwoESHL+lKVoMVf6OgQ5U=; b=nRtyE27AwKohnC3SR1mzFMNmxY05vnkB1raC+QPUnsnvlXc126LCatr6NY9F7ekX/m iEf+s0KDPblpZjKvZWCBQYLnebDDtTCxHdFqDamw2imze09cMl5iZs0zlbcNTm/wy9Hv aXKkMwfr/+yVyLNMRpAfgjSFtCvclqdy3ZLe7zFyg8SawgBiC2wht9QAuKjGYVYLykoV K23lCJKuKzJ9JH/en75LBt2bzo/sD2VXWbJ71cChYilHTLdHZWYHooXxPFSep5eE+xbO Fnfm65gQJyl9mvDsQA7CLX0LarM2c4Ry9xmu95ScWnL/L7UsOygWQ4mUf9kog77dKX4v NaTw== X-Gm-Message-State: ALKqPweU3xyhH7F3Kum8d7nwqGLV1LSnTQAFFRUm+qJ3WDH2q99809ow Km82TJZRGQOwVM4Pah0kIjIX0w== X-Google-Smtp-Source: ADUXVKIeVXcXxlU5IVyI95N7PoaUi0E16cfEUK7BtapysLm82D6JKVlGq2tR/i6wmU7ywd2PU+Q/DA== X-Received: by 2002:a2e:9a06:: with SMTP id o6-v6mr6360476lji.17.1527591056911; Tue, 29 May 2018 03:50:56 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id v1-v6sm6418356ljg.58.2018.05.29.03.50.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:55 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:49:59 +0200 Message-Id: <20180529105011.1914-27-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22e Subject: [Qemu-devel] [PULL v1 26/38] target-microblaze: mmu: Prepare for 64-bit addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Prepare for 64-bit addresses. This makes no functional difference as the upper parts of the 64-bit addresses are not yet reachable. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/mmu.c | 14 +++++++------- target/microblaze/mmu.h | 6 +++--- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 231803ceea..a379968618 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -81,16 +81,16 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, { unsigned int i, hit = 0; unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel; - unsigned int tlb_size; - uint32_t tlb_tag, tlb_rpn, mask, t0; + uint64_t tlb_tag, tlb_rpn, mask; + uint32_t tlb_size, t0; lu->err = ERR_MISS; for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { - uint32_t t, d; + uint64_t t, d; /* Lookup and decode. */ t = mmu->rams[RAM_TAG][i]; - D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID)); + D(qemu_log("TLB %d valid=%" PRId64 "\n", i, t & TLB_VALID)); if (t & TLB_VALID) { tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7); if (tlb_size < TARGET_PAGE_SIZE) { @@ -98,10 +98,10 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, abort(); } - mask = ~(tlb_size - 1); + mask = ~((uint64_t)tlb_size - 1); tlb_tag = t & TLB_EPN_MASK; if ((vaddr & mask) != (tlb_tag & mask)) { - D(qemu_log("TLB %d vaddr=%x != tag=%x\n", + D(qemu_log("TLB %d vaddr=%" PRIx64 " != tag=%" PRIx64 "\n", i, vaddr & mask, tlb_tag & mask)); continue; } @@ -173,7 +173,7 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, } } done: - D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n", + D(qemu_log("MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n", vaddr, rw, tlb_wr, tlb_ex, hit)); return hit; } diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 624becfded..1714caf82e 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -28,7 +28,7 @@ #define RAM_TAG 0 /* Tag portion */ -#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ +#define TLB_EPN_MASK MAKE_64BIT_MASK(10, 64 - 10) #define TLB_PAGESZ_MASK 0x00000380 #define TLB_PAGESZ(x) (((x) & 0x7) << 7) #define PAGESZ_1K 0 @@ -42,7 +42,7 @@ #define TLB_VALID 0x00000040 /* Entry is valid */ /* Data portion */ -#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ +#define TLB_RPN_MASK MAKE_64BIT_MASK(10, 64 - 10) #define TLB_PERM_MASK 0x00000300 #define TLB_EX 0x00000200 /* Instruction execution allowed */ #define TLB_WR 0x00000100 /* Writes permitted */ @@ -63,7 +63,7 @@ struct microblaze_mmu { /* Data and tag brams. */ - uint32_t rams[2][TLB_ENTRIES]; + uint64_t rams[2][TLB_ENTRIES]; /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ uint8_t tids[TLB_ENTRIES]; /* Control flops. */ From patchwork Tue May 29 10:50:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921988 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VSLOWVMs"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9wP0sXcz9s08 for ; Tue, 29 May 2018 21:09:25 +1000 (AEST) Received: from localhost ([::1]:60182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcVG-0007WP-Mo for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:09:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37116) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDY-0001nT-72 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDU-0004DJ-0V for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:04 -0400 Received: from mail-wr0-x22b.google.com ([2a00:1450:400c:c0c::22b]:46349) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDT-0004Cb-Pr for qemu-devel@nongnu.org; Tue, 29 May 2018 06:50:59 -0400 Received: by mail-wr0-x22b.google.com with SMTP id v13-v6so13000780wrp.13 for ; Tue, 29 May 2018 03:50:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MIkh3jvdbvNRVV8XMUmatpJYuuygfFkJjRxlf7IlfKw=; b=VSLOWVMshQQRK9jzxfaa/WnDmEj8Hr4ULDfF92kfzc1UBnSZTP8bMFmWDD9mb4oKft xY9t1hYCYHV+GYgzwSchHsKIfXkAJDw7Dq+3vsQBjGIOcbB4ABjhHHXPBFbbz7SAZYix h4fjtqNDT56sxrfdjAbyYpVpuwdSQ5ZlkLo6kSMqyq37anqog0XzIYhMPtX2LI/YLakU G/aiERv6hBSUKd9fcOSwxzTZEN2eFKe8Ir5kn3DzwnD4AJIxkwDw/N8EAnpvpU9bKXxv ETuwYFni7RxMQ7kJqz37oVuTm3e6wItOyaJs5zrBQIrQWknZ6hyxNacEx6+Co9a19tlO xoJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MIkh3jvdbvNRVV8XMUmatpJYuuygfFkJjRxlf7IlfKw=; b=OK9HDYQz4T7gsif0ftp8r6R3e8rMyj21nt1TM95Qnpc6h0gC++I1aJ7yo8JMi+bVI9 N97mmrPidInDL+B+jYYy1uo90EitNWwSD0KWVZ/G5rMZWe+sIvll+jPF9yiTbUp5bYnd 8lcRQdBiY7zg7GnOChA6+aHajl+lnzBMsgPswADFzfXSruZh7HFI5wuPbCy9y+XHUwU6 k9G2TKgu5wCPH06Rxft0sZN04g53RPgwSHtD3EFoe0nQ/qB/mkAv5IH6FWXSudcZl1aF +0JstcEyCbkI1LxUEDt8tot4nX2ZIfviGQG6qjsXFAEwP3eFvUegwSZgnvH4DJvUP0DY k8Dg== X-Gm-Message-State: ALKqPweSCoDkM5GoroEAVeBTyuTVash4XUgduyNKJE4ywQ0b4m418IoT V6jhB6kMPThURT8I53H2kdnJsg== X-Google-Smtp-Source: ADUXVKJC00/jFa4udpqV4y9+EFD7MxvJvqcv/OJGxmjn4oK3iemmdUvIIX1qjtohvaK3xuxN4qmQyw== X-Received: by 2002:a19:f205:: with SMTP id q5-v6mr8899919lfh.125.1527591058398; Tue, 29 May 2018 03:50:58 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id v3-v6sm6403027ljj.71.2018.05.29.03.50.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:57 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:00 +0200 Message-Id: <20180529105011.1914-28-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22b Subject: [Qemu-devel] [PULL v1 27/38] target-microblaze: mmu: Add a configurable output address mask X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add a configurable output address mask, used to mimic the configurable physical address bit width. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 1 + target/microblaze/mmu.c | 1 + target/microblaze/mmu.h | 1 + 3 files changed, 3 insertions(+) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6ee15ac800..71fc8d09fe 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -128,6 +128,7 @@ static void mb_cpu_reset(CPUState *s) env->mmu.c_mmu = 3; env->mmu.c_mmu_tlb_access = 3; env->mmu.c_mmu_zones = 16; + env->mmu.c_addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size); #endif } diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index a379968618..166c79908c 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -164,6 +164,7 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, tlb_rpn = d & TLB_RPN_MASK; lu->vaddr = tlb_tag; + lu->paddr = tlb_rpn & mmu->c_addr_mask; lu->paddr = tlb_rpn; lu->size = tlb_size; lu->err = ERR_HIT; diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 1714caf82e..9fbdf38f36 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -72,6 +72,7 @@ struct microblaze_mmu int c_mmu; int c_mmu_tlb_access; int c_mmu_zones; + uint64_t c_addr_mask; /* Mask to apply to physical addresses. */ }; struct microblaze_mmu_lookup From patchwork Tue May 29 10:50:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="F6NM1L+G"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wBBX26wMz9s0W for ; Tue, 29 May 2018 21:21:40 +1000 (AEST) Received: from localhost ([::1]:60265 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNch7-0007nL-UC for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:21:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDY-0001o2-RO for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDV-0004Es-G8 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:04 -0400 Received: from mail-wr0-x22a.google.com ([2a00:1450:400c:c0c::22a]:38301) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDV-0004EB-9S for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:01 -0400 Received: by mail-wr0-x22a.google.com with SMTP id 94-v6so24688382wrf.5 for ; Tue, 29 May 2018 03:51:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GRZeGHi0CRackZwvVvAMSL4+7UTu1CRrGMTnG6O9D4c=; b=F6NM1L+GqXAMArkRRw+idQV5IQbx+8e0Q5gpTNWpo6u7bJOBGgexzg5IHVW4XW+AFW 8JeRkmRYqz46/vxct2jyXanbmBMk+gvHqOEAkKbvNxgAJ0X6RRZYCFExwY0FYoz100JE QOeBgZ82moZFPPZRsFUlh15BFnn0hJNtBVjlua31W5CGP6Uv6NsJzFnX+HpT3NPLvxeR jd4wF8BKaL92wpzN/MdQznR+OzIK0u7QHReL+gqaExXMVoOtAwSjwk4U+mjlTLIgEjCI RcbByoMGgApC1NXYWiQq+NXSD23njhu29/m8jRTvMAyJafaAuemg19YDXjS+hJUrqRkz AQXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GRZeGHi0CRackZwvVvAMSL4+7UTu1CRrGMTnG6O9D4c=; b=bOIpXSSpKa3ATS9qDG0sZHdbl/hTJwGRTuOWXuXu4KuPfFZgkV8JFD0GXhYK/VN4CV JHLtpkZKHqArt1ZDTFngDF6Rmlj3ua7ZOCYWtejh2B3uadjZUWn0w7OUTS2mMX6VuNLB ENQVPUTgvYcbbl791nRA43JTqUJNt2CFCsfV9LAMuyhK4n1YrnXvoT0A5m32mqoJYweV H/eK2fvJrfD8qi7AVkBSSCwhkU0NDvyAvG2TM8Up6s0KtfOua6AhA8O5+V43dj4Sji4F eh3YumuQuSlcLSEUdLjyXJHnsDHnche4l5ioVpgpN2Qt2O6h3QlKFtVis+MVunylvv0X 1YOQ== X-Gm-Message-State: ALKqPwc+zrtpahwiqYDXagqYs1YQb7JarB08/HGnMKBkfCG/8vNhZhrE zw4tAKdwPK03G+TaC38cHGagwA== X-Google-Smtp-Source: ADUXVKIddtcnmGCxl1yi0EcSF/rABJVrWY+Bl35mvzLIjF/u9U3nj1XtM65seuKF66HN7TaHimA1RQ== X-Received: by 2002:a19:5004:: with SMTP id e4-v6mr9017010lfb.78.1527591059886; Tue, 29 May 2018 03:50:59 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id n3-v6sm6375578ljg.16.2018.05.29.03.50.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:50:58 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:01 +0200 Message-Id: <20180529105011.1914-29-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22a Subject: [Qemu-devel] [PULL v1 28/38] target-microblaze: dec_msr: Plug a temp leak X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Plug a temp leak. Reported-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7475003847..756d901eba 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -516,12 +516,17 @@ static void dec_msr(DisasContext *dc) #if !defined(CONFIG_USER_ONLY) /* Catch read/writes to the mmu block. */ if ((sr & ~0xff) == 0x1000) { + TCGv_i32 tmp_sr; + sr &= 7; + tmp_sr = tcg_const_i32(sr); LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); - if (to) - gen_helper_mmu_write(cpu_env, tcg_const_i32(sr), cpu_R[dc->ra]); - else - gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_i32(sr)); + if (to) { + gen_helper_mmu_write(cpu_env, tmp_sr, cpu_R[dc->ra]); + } else { + gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_sr); + } + tcg_temp_free_i32(tmp_sr); return; } #endif From patchwork Tue May 29 10:50:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921990 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="L3F0NWth"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9zL4q3Tz9s0W for ; Tue, 29 May 2018 21:11:58 +1000 (AEST) Received: from localhost ([::1]:60203 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcXk-00013h-81 for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:11:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37128) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDY-0001o4-Rp for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDX-0004Fj-77 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:04 -0400 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:37029) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDW-0004FE-TW for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:03 -0400 Received: by mail-wm0-x235.google.com with SMTP id l1-v6so39334701wmb.2 for ; Tue, 29 May 2018 03:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SMcS32XBvHwDjYqrTbF4JcGNQeWWF5CMrnwXttlzlPQ=; b=L3F0NWthgZ7tFeThCXP6PSHHIq9WQDZfQ66DAt6pJGhr+/QNbDGR0E7X0Y+lsB+HYC zFwXxCczSYaEpu47AVqusoZd/JrqihE2miK7fYK/T3I+Rb7DfiSMvxH9YZD2Uxn/RJC2 lVkp3RBPz0jJjBVSD3AKv9MlSQcliB/RTxlqQuTIC9rAHNHhuivvCjX93kD4hdK7XidZ tiJVGBQC0/z8BMcN1uz5V5iKUcsDdcAH//2mu3hl61dKr7t5MK6DKjS70sbkJcfotDcV OTz5cGI3WmcKT7edCzuFQuQae8RXTYejGvYgNdp0ZU5+F1KPmzysG83J9HHt1g9d1gCb gcow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SMcS32XBvHwDjYqrTbF4JcGNQeWWF5CMrnwXttlzlPQ=; b=TSPDACcQWZA4FMBuw7pUErU5Tky9RHJ9WfRF3ecj9YtB7r5dP39CD+ESiqbzvUJW44 LYlReyyTrG8a5l1TR9DYjvB193jdZ11alAufc4HWybDZKYqIQgs5s5ub9NBFNgjtIQYW 80MuayoDnCuR6BBPUq2TyMzHrnWyOHJde8tJHXMQdIzTt4pJlK54/NEPo4e/tcrzrqav NS7Zg+qUhYr4cRtyN0YGzNR0GiyIOwLP03lUBYYmks4+qoCwXVAWZKMQL8NC2DcJhGym mlHW080CxNcZxXIuE7CdFB5xnXVJQ+dAtSmSnoL0K204kMfVfE8DvBMXQZZ5o/r7i3aI D0+Q== X-Gm-Message-State: ALKqPwei8FfmRyHwjemmO6H1uPVib+F0lKI1LxTxfILJz9La0POYsWT9 gCN1gJ1QNKDGmwRES9eNY8TcZg== X-Google-Smtp-Source: AB8JxZplcTw43CbnElIckNB13oqvqdFC7AMjl5n5wejsckHjUue1t1uWLdfVLedtk7jcsxmMKEtmOA== X-Received: by 2002:a2e:9f06:: with SMTP id u6-v6mr10743042ljk.42.1527591061531; Tue, 29 May 2018 03:51:01 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id c6-v6sm6366280lja.22.2018.05.29.03.51.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:00 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:02 +0200 Message-Id: <20180529105011.1914-30-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [PULL v1 29/38] target-microblaze: Add support for extended access to TLBLO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add support for extended access to TLBLO's upper 32 bits. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/helper.h | 4 ++-- target/microblaze/mmu.c | 18 ++++++++++++++---- target/microblaze/mmu.h | 4 ++-- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 19 +++++++++++++------ 5 files changed, 35 insertions(+), 18 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index ce70353936..2f8bdea22b 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -25,8 +25,8 @@ DEF_HELPER_3(fcmp_ge, i32, env, i32, i32) DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_2(mmu_read, i32, env, i32) -DEF_HELPER_3(mmu_write, void, env, i32, i32) +DEF_HELPER_3(mmu_read, i32, env, i32, i32) +DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 166c79908c..9ecffb2c9c 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -180,7 +180,7 @@ done: } /* Writes/reads to the MMU's special regs end up here. */ -uint32_t mmu_read(CPUMBState *env, uint32_t rn) +uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) { unsigned int i; uint32_t r = 0; @@ -189,6 +189,10 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); return 0; } + if (ext && rn != MMU_R_TLBLO) { + qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n"); + return 0; + } switch (rn) { /* Reads to HI/LO trig reads from the mmu rams. */ @@ -200,7 +204,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) } i = env->mmu.regs[MMU_R_TLBX] & 0xff; - r = env->mmu.rams[rn & 1][i]; + r = extract64(env->mmu.rams[rn & 1][i], ext * 32, 32); if (rn == MMU_R_TLBHI) env->mmu.regs[MMU_R_PID] = env->mmu.tids[i]; break; @@ -226,9 +230,10 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) return r; } -void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) +void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) { MicroBlazeCPU *cpu = mb_env_get_cpu(env); + uint64_t tmp64; unsigned int i; D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn])); @@ -236,6 +241,10 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); return; } + if (ext && rn != MMU_R_TLBLO) { + qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n"); + return; + } switch (rn) { /* Writes to HI/LO trig writes to the mmu rams. */ @@ -250,7 +259,8 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } - env->mmu.rams[rn & 1][i] = v; + tmp64 = env->mmu.rams[rn & 1][i]; + env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v); D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v)); break; diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 9fbdf38f36..a4272b6356 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -90,6 +90,6 @@ struct microblaze_mmu_lookup unsigned int mmu_translate(struct microblaze_mmu *mmu, struct microblaze_mmu_lookup *lu, target_ulong vaddr, int rw, int mmu_idx); -uint32_t mmu_read(CPUMBState *env, uint32_t rn); -void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v); +uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); +void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); void mmu_init(struct microblaze_mmu *mmu); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 4dc3aff84b..ddc1f71d62 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -476,14 +476,14 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) #if !defined(CONFIG_USER_ONLY) /* Writes/reads to the MMU's special regs end up here. */ -uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn) +uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn) { - return mmu_read(env, rn); + return mmu_read(env, ext, rn); } -void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) +void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v) { - mmu_write(env, rn, v); + mmu_write(env, ext, rn, v); } void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr, diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 756d901eba..bb6b5176c1 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -459,7 +459,7 @@ static void dec_msr(DisasContext *dc) CPUState *cs = CPU(dc->cpu); TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset, extended; + bool to, clrset, extended = false; sr = extract32(dc->imm, 0, 14); to = extract32(dc->imm, 14, 1); @@ -467,9 +467,14 @@ static void dec_msr(DisasContext *dc) dc->type_b = 1; if (to) { dc->cpustate_changed = 1; - extended = extract32(dc->imm, 24, 1); - } else { - extended = extract32(dc->imm, 19, 1); + } + + /* Extended MSRs are only available if addr_size > 32. */ + if (dc->cpu->cfg.addr_size > 32) { + /* The E-bit is encoded differently for To/From MSR. */ + static const unsigned int e_bit[] = { 19, 24 }; + + extended = extract32(dc->imm, e_bit[to], 1); } /* msrclr and msrset. */ @@ -516,17 +521,19 @@ static void dec_msr(DisasContext *dc) #if !defined(CONFIG_USER_ONLY) /* Catch read/writes to the mmu block. */ if ((sr & ~0xff) == 0x1000) { + TCGv_i32 tmp_ext = tcg_const_i32(extended); TCGv_i32 tmp_sr; sr &= 7; tmp_sr = tcg_const_i32(sr); LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); if (to) { - gen_helper_mmu_write(cpu_env, tmp_sr, cpu_R[dc->ra]); + gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); } else { - gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_sr); + gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr); } tcg_temp_free_i32(tmp_sr); + tcg_temp_free_i32(tmp_ext); return; } #endif From patchwork Tue May 29 10:50:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921979 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="co7qhY3w"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9mP059Nz9s0W for ; Tue, 29 May 2018 21:02:29 +1000 (AEST) Received: from localhost ([::1]:60147 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcOY-0002L3-Nj for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:02:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDZ-0001oW-At for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDY-0004GS-JL for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:05 -0400 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:39229) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDY-0004G3-DV for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:04 -0400 Received: by mail-wm0-x22c.google.com with SMTP id f8-v6so39343918wmc.4 for ; Tue, 29 May 2018 03:51:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LwBwLfcHpDJ7rBwThy7deL0DHLaHXyc+u0rR66zJs3o=; b=co7qhY3wSKDL93+VjprYtr7FbTZcC+zW1whyViTmHMF3K3Caj/Ja9aVTwIaDSc2Q48 cEZ7VwVnrB/V/Dwj8cEd+Fz6+8PcaMUF7RqiJfYUZ1qXK3dNKfjuQN157Zj4l4zFazLI fW9QafDMkX9Q7fGg76A8y7F7d6n/maNGuCoqWWxqOf0hFp3v8P+NdcrLhFNFOwIh4o3J 7EJVoAj8xDYsQxDoFi3ED7RGZpPLeWkQS7ghcxIMrmd380O2q+X02khK2gu8eOY1rDKD ESDtCjhqUuY+b3IE6rQkXycZ4lBm5yBBNim0Z+VXtRZ9xfsIW8DNymFQceZO4yuiNg91 HNWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LwBwLfcHpDJ7rBwThy7deL0DHLaHXyc+u0rR66zJs3o=; b=TBmZL6NqfmI1bZNp2IEQYwgbveHwBBRoCeVPuRShdMHgCvR51iUX0B4r/FNjXg215l CcBiNChB3l/Qbi9eGMQjPGZtzW6jnmHZNEsGr2zYwOUcJSKIpRVKtL1bdpWVq5fmz7Zv Hlm8OCG9B4TDbTSjfcWv5eopiduKjxeESCEb0Zv8IzytYi0wGzIS91enG5oodnQ0y8F5 pFCXDXejne0U/xeB8UuuP10uqriE3PEIySJTxdgZDQ7OjIFlDahF13Xm7RMY9KTqY9gw 6pHYiVa9eQlKZPXvtgJdP4znjUaXujHqa6tM3QVJ8wdsp92cwdmXS12CXvK2plfgdKqW c1Vg== X-Gm-Message-State: ALKqPwdTh7VoagXtvGJvQQii7Tcl5/FCRxCxp6+BPWomwVZ/EF3ds/nY evISy225SQRCNHA3EJ/PF92sVg== X-Google-Smtp-Source: ADUXVKJNZSZuNZQI5YV3c6JnpfttLxAnsbucStdvYtpO5LeyGFutiTmu2VPV8iLrVx+PEXAMag1qFw== X-Received: by 2002:a2e:2286:: with SMTP id i128-v6mr2018623lji.47.1527591063112; Tue, 29 May 2018 03:51:03 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id i6-v6sm5451677lfc.12.2018.05.29.03.51.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:02 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:03 +0200 Message-Id: <20180529105011.1914-31-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [PULL v1 30/38] target-microblaze: Allow address sizes between 32 and 64 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Allow address sizes between 32 and 64 bits. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 71fc8d09fe..9b546a2c18 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -155,9 +155,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) return; } - if (cpu->cfg.addr_size != 32) { - error_setg(errp, "addr-size %d is out of range. " - "Only 32bit is supported.", + if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) { + error_setg(errp, "addr-size %d is out of range (32 - 64)", cpu->cfg.addr_size); return; } From patchwork Tue May 29 10:50:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921992 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Np6zZRe2"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wB1k28XPz9s08 for ; Tue, 29 May 2018 21:14:02 +1000 (AEST) Received: from localhost ([::1]:60217 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcZj-0002lY-Uc for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:13:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37166) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDa-0001qM-Ug for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDa-0004Hw-79 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:07 -0400 Received: from mail-wm0-x234.google.com ([2a00:1450:400c:c09::234]:39950) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDZ-0004HJ-W7 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:06 -0400 Received: by mail-wm0-x234.google.com with SMTP id x2-v6so31862588wmh.5 for ; Tue, 29 May 2018 03:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cc3+xpBos8NzE2Nb7GIEFsRnslr4t2plfgNWJYViiOg=; b=Np6zZRe2cpj0uPg1EOuOzEYy40N6V1QDuAPK9AWrGixL59sqMKs/m6ABHSUtDOMQFg jqwSqvdtVp1KTZGuYf0JN9mU0iyfFK+aMD3APLYamXcu6hc9GNMnPjHdklpp5nv3T6my EKkZysVe95lNzlFFJLU4HDcdP4FbpGK+5jjt8lDtyKhwQMDiOUtxjtJmhjCdu/N69jwg zxv7VMRWA5/LpCtovCxa27H/U6EeQSerbro0TWXf+OSZ5HW9IslKmp6GH2j9jIogp6GK VCh3VJQwnnDjGcqRY8n6boT5j/eg/AZg+XkezMo+v5zoMAuni7+TbUZCeIxlbeAku+U3 zRGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cc3+xpBos8NzE2Nb7GIEFsRnslr4t2plfgNWJYViiOg=; b=k4JDyAqtrPVj95Gk9ENopMlV8ZJmhzZmoQ92zv+CqHzHGN1vTfSz4MLAi+yzVFxd0G EEEhsLAo6nPnTGROoIPyJYMuuUZcJF8B9GRaWAWgFHMFk0+SpnJ+E/idtm9TZSPtyQ02 LL/uZmtMsB9vNySIMhnvQBQA3ZBm56VV9iGbdxaAW+tNxIf49GrXr9ZrVnZvOIni25dh l3L+jXqZGom2iK906b8bA4QPye3lyHTIe4WWWL7C2+136AfFrUbmVKFf/Sduj9u7F8EV dZrOdJEXPqheMgHUY57iOYgbJnHPe8WdkQi50NIkbOw8T5kocug4thSPQ/oFqIHFL4IO /wvQ== X-Gm-Message-State: ALKqPwfl/fdYGl0zvV26cb/iVIvtiFi2IbVqkA6DVhPwUiM1dyyJV9CI zrUkVsHs2W6WSi6MPXAzTl32wQ== X-Google-Smtp-Source: ADUXVKLYjsQESBNbaRmmtPlRHuWqygEZ7tyc5rgtaQ0joW33P3nDNuePnWvDIvLfTvMOa94PmxFIww== X-Received: by 2002:a2e:56cb:: with SMTP id k72-v6mr10678102lje.140.1527591064584; Tue, 29 May 2018 03:51:04 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id q1-v6sm6323537lje.43.2018.05.29.03.51.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:03 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:04 +0200 Message-Id: <20180529105011.1914-32-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::234 Subject: [Qemu-devel] [PULL v1 31/38] target-microblaze: Simplify address computation using tcg_gen_addi_i32() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Simplify address computation using tcg_gen_addi_i32(). tcg_gen_addi_i32() already optimizes the case when the immediate is zero. No functional change. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index bb6b5176c1..0d8ef77513 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -899,12 +899,7 @@ static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) /* Immediate. */ t32 = tcg_temp_new_i32(); if (!extimm) { - if (dc->imm == 0) { - tcg_gen_mov_i32(t32, cpu_R[dc->ra]); - } else { - tcg_gen_movi_i32(t32, (int32_t)((int16_t)dc->imm)); - tcg_gen_add_i32(t32, cpu_R[dc->ra], t32); - } + tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); } else { tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); } From patchwork Tue May 29 10:50:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921999 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="uHYEfwtV"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wBDQ2Mxkz9s08 for ; Tue, 29 May 2018 21:23:16 +1000 (AEST) Received: from localhost ([::1]:60275 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcif-0000Wb-T4 for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:23:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37187) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDd-0001sg-4O for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDb-0004JT-Rg for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:09 -0400 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:33950) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDb-0004Ig-IF for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:07 -0400 Received: by mail-wm0-x22d.google.com with SMTP id q4-v6so28269747wmq.1 for ; Tue, 29 May 2018 03:51:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=my3DHcS4n/JoPo+VczkBCUs8k7L9josQQNkE+lUR9zo=; b=uHYEfwtVYoieWX6xbXkpFN7zoMXd0DA5cWVevQgqiRANJ7oBV6pze70fB150tjPOlR cV/CP43sPKr3Nj6iC2TjNP9FMn97QwaSCFe4hKBrsHMumCW8lniE/u6yAWxsUerFx0lP a3lTw+4AwClp5CEFp3scUpW7Ke575ayTtZXxYZMpPRe+kVNRthXeFYczEoOmUGHAnmOf 8Y5pvYjALyx5dQWT9ytY0WitdiILmM9Q9o4kq9A+tyY+X2cbQgINWHsPkPN5Arrmagee 7hvrI0PgR8kK32uUxzz0QhlV+9/5Zh+nerglP7iIGDB317cGPAVlr7Du413ntQYiwT7m GhRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=my3DHcS4n/JoPo+VczkBCUs8k7L9josQQNkE+lUR9zo=; b=qF7PgaGo3C1fjqC9tmcpXXjR24KFLWDt9cA5D2mZ1CNeT4asY4+1yLEthInqedmcCq ptA4yFlSWZIBs3zXbcx3Yak35AGza3oMBTiI1DBdFeGTuSMn+FFSTj+1svRFIEQSWIh8 F2+Tlfm5d88Px0r47SD5H1WAB0yW4ziCcM5Kz8gURBC6mlkcvDPJY6gvSdaBApH2Q+UQ 3241qabyDhi/nI3honD21zQauB7oFnoRW+o3jC6u1Ju8jbDhfCp34q8BWZOdUwBlZyRa xqyb3ZOUfI9qnGwlOtjjKikTnAt995kCl5ch+CCZTbEQ2p+1rMjATSdY1FNKW4VJyd2W 5eww== X-Gm-Message-State: ALKqPwd+d02+VREVgHGvhmbzpckyXpI5a8lSWnTt/uq8e1rp4qv+2GAO mJXaKScFUbR+G5/iLZ7zcYCp/g== X-Google-Smtp-Source: ADUXVKLSL60Pf+GdX9e5Ppp5J+D4PrkWGZfob6KtjUFcVRF2ZU3m5u56WJ+HWkKgWRAeciAqXgpZbw== X-Received: by 2002:a2e:1947:: with SMTP id p68-v6mr10727358lje.114.1527591066215; Tue, 29 May 2018 03:51:06 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id i6-v6sm5451696lfc.12.2018.05.29.03.51.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:05 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:05 +0200 Message-Id: <20180529105011.1914-33-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [PULL v1 32/38] target-microblaze: mmu: Cleanup debug log messages X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Cleanup debug log messages: * Avoid long 80+ character lines. * Remove D() macro and use qemu_log_mask. * Remove logs that are not very useful Suggested-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/mmu.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 9ecffb2c9c..f4ceaea520 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -22,8 +22,6 @@ #include "cpu.h" #include "exec/exec-all.h" -#define D(x) - static unsigned int tlb_decode_size(unsigned int f) { static const unsigned int sizes[] = { @@ -90,25 +88,20 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, /* Lookup and decode. */ t = mmu->rams[RAM_TAG][i]; - D(qemu_log("TLB %d valid=%" PRId64 "\n", i, t & TLB_VALID)); if (t & TLB_VALID) { tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7); if (tlb_size < TARGET_PAGE_SIZE) { - qemu_log("%d pages not supported\n", tlb_size); + qemu_log_mask(LOG_UNIMP, "%d pages not supported\n", tlb_size); abort(); } mask = ~((uint64_t)tlb_size - 1); tlb_tag = t & TLB_EPN_MASK; if ((vaddr & mask) != (tlb_tag & mask)) { - D(qemu_log("TLB %d vaddr=%" PRIx64 " != tag=%" PRIx64 "\n", - i, vaddr & mask, tlb_tag & mask)); continue; } if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) { - D(qemu_log("TLB %d pid=%x != tid=%x\n", - i, mmu->regs[MMU_R_PID], mmu->tids[i])); continue; } @@ -123,7 +116,8 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, t0 &= 0x3; if (tlb_zsel > mmu->c_mmu_zones) { - qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range! %d\n", tlb_zsel); + qemu_log_mask(LOG_GUEST_ERROR, + "tlb zone select out of range! %d\n", tlb_zsel); t0 = 1; /* Ignore. */ } @@ -174,8 +168,9 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, } } done: - D(qemu_log("MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n", - vaddr, rw, tlb_wr, tlb_ex, hit)); + qemu_log_mask(CPU_LOG_MMU, + "MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n", + vaddr, rw, tlb_wr, tlb_ex, hit); return hit; } @@ -199,7 +194,8 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) case MMU_R_TLBLO: case MMU_R_TLBHI: if (!(env->mmu.c_mmu_tlb_access & 1)) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return 0; } @@ -211,7 +207,8 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) case MMU_R_PID: case MMU_R_ZPR: if (!(env->mmu.c_mmu_tlb_access & 1)) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return 0; } r = env->mmu.regs[rn]; @@ -226,7 +223,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); break; } - D(qemu_log("%s rn=%d=%x\n", __func__, rn, r)); + qemu_log_mask(CPU_LOG_MMU, "%s rn=%d=%x\n", __func__, rn, r); return r; } @@ -235,7 +232,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) MicroBlazeCPU *cpu = mb_env_get_cpu(env); uint64_t tmp64; unsigned int i; - D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn])); + qemu_log_mask(CPU_LOG_MMU, + "%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]); if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); @@ -261,12 +259,11 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) } tmp64 = env->mmu.rams[rn & 1][i]; env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v); - - D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v)); break; case MMU_R_ZPR: if (env->mmu.c_mmu_tlb_access <= 1) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return; } @@ -279,7 +276,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) break; case MMU_R_PID: if (env->mmu.c_mmu_tlb_access <= 1) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return; } @@ -298,7 +296,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) int hit; if (env->mmu.c_mmu_tlb_access <= 1) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return; } From patchwork Tue May 29 10:50:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921986 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DVT3v94e"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9vK2ZSVz9s08 for ; Tue, 29 May 2018 21:08:29 +1000 (AEST) Received: from localhost ([::1]:60178 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcUM-0006sY-Tw for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:08:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDe-0001u1-54 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDd-0004Kg-C5 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:10 -0400 Received: from mail-wr0-x230.google.com ([2a00:1450:400c:c0c::230]:45330) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDd-0004K4-5i for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:09 -0400 Received: by mail-wr0-x230.google.com with SMTP id w3-v6so24680245wrl.12 for ; Tue, 29 May 2018 03:51:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TC6W2A5ZCNupt6SjBAJ0xYHrP3d6Qs3gfDKnXiM8H8E=; b=DVT3v94eNuP1t3Wa/1sSbV7Ape3Trvs62TwsSq6ESN1gpQAAQSz+hkT9rUtZc1qTSG B7cP9XukY8HSj084a2xFqDU+0Om03xOSm6yZmisrXADPPmwyJQPqFVuB3hHB9eSQ6LKA VVBo3Ii3RdR86m7fHbtMR22toLOKwFFhnsi4HvI8MsSVCQOFFwmd5mOiB+1R+YYazENo jrwqru1ulZ0aK4tWnajtqCbRl/4HMtA/itTyFMsjGj1mXzsb8+Wn5gklg/JXR7HVnUEk GUyw505t1IBxfn4fWQw2u0Wy0LfLtPHBglJfrpKz6KDCmIe95eSBnPQdNNkpCRzlvldW RPuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TC6W2A5ZCNupt6SjBAJ0xYHrP3d6Qs3gfDKnXiM8H8E=; b=qQ/HoDk+0I+RF+ss3oCB1Dc6MhCHvoXT/SSCwSiLVsgmQ0askCW+M8eO3oJ69iseQV /ztuZMoKnE1xBiuLgcbYUCNS/zGyBxVrh0cCwAS8Vp+LAj3WQ2H7essV+VjG5iq4T3ja UQH3YQFe+jVvNwzseTWYv5vk66cm4l00T3D/8ntCfd3Xw23pek0iGr2Sg1b24CvAcNbD tQBBr5r19OhE3EhnudRS5AgpsE2IMl1ejSiTgBADeuyVKto9IWhrefZVvL4lFomOUWeY lDBGkRlhIYkhMP/j4rtlubMEnD+U5rZiwUJR7TL9Mq7REFvl7mKj67mS9tNmltHPKqyo vIDg== X-Gm-Message-State: ALKqPwc6u7J8ZIyyLgAG3oHf+a0VSBXPr6niDfQFKtJzInsKta/iW1ur jAp9GR5bAFPsVxQe53PhnUMDNQ== X-Google-Smtp-Source: ADUXVKLeU+5S4cy2m//C9B8QwcFjXspW0BUjMlZs6gfnypn3mfbVGpi4OHWLZbQM1ivovS0LSkwGyA== X-Received: by 2002:a19:16e1:: with SMTP id 94-v6mr9041694lfw.45.1527591067819; Tue, 29 May 2018 03:51:07 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id l10-v6sm6373370lja.62.2018.05.29.03.51.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:06 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:06 +0200 Message-Id: <20180529105011.1914-34-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::230 Subject: [Qemu-devel] [PULL v1 33/38] target-microblaze: Use table based condition-codes conversion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Use a table based conversion to map condition-codes between MicroBlaze ISA encoding and TCG. No functional change. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 41 ++++++++++++++++++++--------------------- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0d8ef77513..092e182c2f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1145,28 +1145,27 @@ static void dec_store(DisasContext *dc) static inline void eval_cc(DisasContext *dc, unsigned int cc, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { + static const int mb_to_tcg_cc[] = { + [CC_EQ] = TCG_COND_EQ, + [CC_NE] = TCG_COND_NE, + [CC_LT] = TCG_COND_LT, + [CC_LE] = TCG_COND_LE, + [CC_GE] = TCG_COND_GE, + [CC_GT] = TCG_COND_GT, + }; + switch (cc) { - case CC_EQ: - tcg_gen_setcond_i32(TCG_COND_EQ, d, a, b); - break; - case CC_NE: - tcg_gen_setcond_i32(TCG_COND_NE, d, a, b); - break; - case CC_LT: - tcg_gen_setcond_i32(TCG_COND_LT, d, a, b); - break; - case CC_LE: - tcg_gen_setcond_i32(TCG_COND_LE, d, a, b); - break; - case CC_GE: - tcg_gen_setcond_i32(TCG_COND_GE, d, a, b); - break; - case CC_GT: - tcg_gen_setcond_i32(TCG_COND_GT, d, a, b); - break; - default: - cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); - break; + case CC_EQ: + case CC_NE: + case CC_LT: + case CC_LE: + case CC_GE: + case CC_GT: + tcg_gen_setcond_i32(mb_to_tcg_cc[cc], d, a, b); + break; + default: + cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); + break; } } From patchwork Tue May 29 10:50:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 922000 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Lf00lv67"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wBFj3V2hz9s0y for ; Tue, 29 May 2018 21:24:25 +1000 (AEST) Received: from localhost ([::1]:60279 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcjn-00016h-5V for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:24:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDj-0001zN-5B for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDe-0004Lb-So for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:15 -0400 Received: from mail-wm0-x234.google.com ([2a00:1450:400c:c09::234]:36592) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDe-0004L4-MT for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:10 -0400 Received: by mail-wm0-x234.google.com with SMTP id v131-v6so20051229wma.1 for ; Tue, 29 May 2018 03:51:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EPXMHzWKqaEXhQn1ScZ+BaAab5LKhT+XVeFW/6oU/4g=; b=Lf00lv67a7ccwAT+3d5TcVmye9D1tdCC2ccbqAhqCuGpksIGlA4PVbUvtB7AaQZJ69 CRKhKs+H7P19hswl+enqp/OGzdBBcEsvQ1a/y1fvBN55NooxTyZkQvXdDd8xq58BBVy5 OCD/wC2W2TN5RUJeEPXi9M9pwCqYirJHK8mSD9T9eAzAsi/EWZm+DUOee4xjuz7DH1Tw gp2Ve8aDR7syfBxN6ppkdDhd4wMmCBny7HX0JCE9banJ/cXx5bCpJPtc/U9bBLETRcz0 WlP6JeHFymL4hVVJMyj1Aw7MXWvcOqtMR86AJjqpKzV73jDYazyNgAWSZUcBYQvRMNL4 ojHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EPXMHzWKqaEXhQn1ScZ+BaAab5LKhT+XVeFW/6oU/4g=; b=mQ+aW4O4fuYz53v8BAFdW5KCBHWC4CULcRahErTfBJSjOifKXrpfqH9NhkL+7bojl/ UDEHQfX7SfWt3ZDx3fbsy3JK9EXBQ9QWSppX1QDooKxdo1xok4h6qJWhg/Vud8B6allP MqAqwrX0JCdtNERC5LSOn4bchXFRzzkU14kBVU6EzPASC8cRCULwAtyUpf7tidnIDThJ iw/XynUlNcScKs481g1uEUK1K3yOw+ouDbju1Jn6IBusDkwD3QCILBUorRcQnWNj/ZdZ 1UzPfc8+dPVWFJXIXRqnJB6z4r+tigYlXWlUUA2bP95fX4ckBJOxw4EIcyljXZipY6rn 5opw== X-Gm-Message-State: ALKqPwe4SnSrEj1/ngAiVQp4OvtExA5Tp38qkF3tVITbGTeTpV2zoUMI DJZ4WXPEz0+ui7eSm0HDAtQHNw== X-Google-Smtp-Source: AB8JxZrQYYIza/0a9Wudb8TfPtdtiuR9bYAkh7oudOEXADvC0zuzY5VEqr8oYg9ALIKYxsqRLkTiSg== X-Received: by 2002:a2e:9756:: with SMTP id f22-v6mr10967060ljj.111.1527591069371; Tue, 29 May 2018 03:51:09 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id o8-v6sm2319877lji.0.2018.05.29.03.51.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:08 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:07 +0200 Message-Id: <20180529105011.1914-35-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::234 Subject: [Qemu-devel] [PULL v1 34/38] target-microblaze: Remove argument b in eval_cc() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Remove argument b in eval_cc() as it is always set to zero. No functional change. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 092e182c2f..d870cb7c43 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1143,7 +1143,7 @@ static void dec_store(DisasContext *dc) } static inline void eval_cc(DisasContext *dc, unsigned int cc, - TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) + TCGv_i32 d, TCGv_i32 a) { static const int mb_to_tcg_cc[] = { [CC_EQ] = TCG_COND_EQ, @@ -1161,7 +1161,7 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, case CC_LE: case CC_GE: case CC_GT: - tcg_gen_setcond_i32(mb_to_tcg_cc[cc], d, a, b); + tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0); break; default: cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); @@ -1207,7 +1207,7 @@ static void dec_bcc(DisasContext *dc) tcg_gen_movi_i32(env_btarget, dc->pc); tcg_gen_add_i32(env_btarget, env_btarget, *(dec_alu_op_b(dc))); } - eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_i32(0)); + eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); } static void dec_br(DisasContext *dc) From patchwork Tue May 29 10:50:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921982 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pTJneuEB"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40w9p43R3yz9s08 for ; Tue, 29 May 2018 21:03:56 +1000 (AEST) Received: from localhost ([::1]:60152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcPy-0003O5-20 for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:03:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDj-0001zM-4z for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDg-0004NC-La for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:15 -0400 Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]:37026) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDg-0004MU-BQ for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:12 -0400 Received: by mail-wm0-x22f.google.com with SMTP id l1-v6so39335783wmb.2 for ; Tue, 29 May 2018 03:51:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lxvx2kRsAbx55gv6Ho6eSYovgIhyKMpmm/3xwVDoBQU=; b=pTJneuEBkzzisdCgjIa458GkU8ZdjOsARLTj+jjGrUtuse1Fu5xyuQA0N4kw/bI/6j n/954jb0ml3/vfdpbQONDQB7j4MAUhLSxhTxsnvIDzgBB3K37ZaQiTpSgIyiQui5q8FQ lBE2TnGKiz5WxUhZ2ePSEfojGkr5CQ8Fyfm4HMnPo6ymrSdf6+0XEO2sbzcc8xvBvFvR ccjr21FJ447JKxqNvsDY2zWISZ3MZn4GNZkfJ4oD8r9P57zDkzIbUrqqHFF4j8Qr2mO6 f5lsy922rogTWVJSFs4UQKseufgPzxx7gak87jA6QpElYPj3OukkXcQXAelKq1RnWxrP ysYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lxvx2kRsAbx55gv6Ho6eSYovgIhyKMpmm/3xwVDoBQU=; b=mQ9GBe7VE1sRGeVUy5dtaJ2WutD7QJTAk90St8Yf9VlxNDF8WrdrJUS+cKEetHRA/a /tgHqHqUMR3DRv18LJy449Z1hl9yJs7N4zbZBeUralITHQVcO+qbgicWLkO4+C27ypNd a1TUrnljvsvABnif8wdWwO1XJkQ4FVmg2LGdSzLR5TBwycjmZz+YHIjxtg9L02mLMXv3 6vU6fWTRLko/X7LZvTIhfWjIeGwS88Je3+5fnRnU1bqK2DJZPBWfEJvAiuX26hVEloxL XvC3t52pGJNexeF92eTnZzZ4OV/MSs0RCH/+XJJoDNGjqbmfziaG6Ws1NuQNCO/n2dlu uW3Q== X-Gm-Message-State: ALKqPweKaIHo7TdPQvkKJGAejNStyjR2pE8tu7zTQJfTmJyjaMi+4k0g D0CTsS9WN9MTYjFQwmydQd+drw== X-Google-Smtp-Source: ADUXVKKcRzHMNBvr/T97Z7Wd56fNQ0w/I7xZlpFh7LKlhnzrEboWAXCwn1YtuZe41FQsu3qmtXnj2A== X-Received: by 2002:a2e:594d:: with SMTP id n74-v6mr4899930ljb.128.1527591070906; Tue, 29 May 2018 03:51:10 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id b136-v6sm4228434lfe.80.2018.05.29.03.51.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:09 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:08 +0200 Message-Id: <20180529105011.1914-36-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22f Subject: [Qemu-devel] [PULL v1 35/38] target-microblaze: Convert env_btarget to i64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Convert env_btarget to i64. No functional change. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 36 +++++++++++++++++++++++------------- 3 files changed, 25 insertions(+), 15 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e62c456ccf..e38580cd7f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,7 +239,7 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t debug; uint32_t btaken; - uint32_t btarget; + uint64_t btarget; uint32_t bimm; uint32_t imm; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index ddc1f71d62..7cdbbcccae 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -99,7 +99,7 @@ void helper_debug(CPUMBState *env) "debug[%x] imm=%x iflags=%x\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags); - qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", + qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d870cb7c43..591d232304 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i64 cpu_SR[14]; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; -static TCGv_i32 env_btarget; +static TCGv_i64 env_btarget; static TCGv_i32 env_iflags; static TCGv env_res_addr; static TCGv_i32 env_res_val; @@ -831,7 +831,7 @@ static inline void sync_jmpstate(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); } dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(env_btarget, dc->jmp_pc); + tcg_gen_movi_i64(env_btarget, dc->jmp_pc); } } @@ -1169,13 +1169,13 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, } } -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i64 pc_false) +static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false) { TCGLabel *l1 = gen_new_label(); /* Conditional jmp. */ tcg_gen_mov_i64(cpu_SR[SR_PC], pc_false); tcg_gen_brcondi_i32(TCG_COND_EQ, env_btaken, 0, l1); - tcg_gen_extu_i32_i64(cpu_SR[SR_PC], pc_true); + tcg_gen_mov_i64(cpu_SR[SR_PC], pc_true); gen_set_label(l1); } @@ -1199,13 +1199,14 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - tcg_gen_movi_i32(env_btarget, dc->pc + offset); + tcg_gen_movi_i64(env_btarget, dc->pc + offset); dc->jmp = JMP_DIRECT_CC; dc->jmp_pc = dc->pc + offset; } else { dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(env_btarget, dc->pc); - tcg_gen_add_i32(env_btarget, env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); + tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); } eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); } @@ -1262,7 +1263,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_INDIRECT; if (abs) { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_mov_i32(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); @@ -1280,8 +1281,9 @@ static void dec_br(DisasContext *dc) dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_movi_i32(env_btarget, dc->pc); - tcg_gen_add_i32(env_btarget, env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); + tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); } } } @@ -1345,6 +1347,7 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; + TCGv_i64 tmp64; i_bit = dc->ir & (1 << 21); b_bit = dc->ir & (1 << 22); @@ -1373,7 +1376,13 @@ static void dec_rts(DisasContext *dc) dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_add_i32(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc))); + + tmp64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_extu_i32_i64(tmp64, cpu_R[dc->ra]); + tcg_gen_add_i64(env_btarget, env_btarget, tmp64); + tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_temp_free_i64(tmp64); } static int dec_check_fpuv2(DisasContext *dc) @@ -1795,7 +1804,8 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, "debug=%x imm=%x iflags=%x fsr=%" PRIx64 "\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); - cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", + cpu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " + "eip=%d ie=%d\n", env->btaken, env->btarget, (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", @@ -1823,7 +1833,7 @@ void mb_tcg_init(void) env_imm = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); - env_btarget = tcg_global_mem_new_i32(cpu_env, + env_btarget = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btarget), "btarget"); env_btaken = tcg_global_mem_new_i32(cpu_env, From patchwork Tue May 29 10:50:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921994 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bM8xu59r"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wB3l59SFz9s08 for ; Tue, 29 May 2018 21:15:47 +1000 (AEST) Received: from localhost ([::1]:60226 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcbR-0003xY-C6 for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:15:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37253) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDj-0001zL-4r for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDh-0004O0-WB for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:15 -0400 Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]:55299) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDh-0004NV-P9 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:13 -0400 Received: by mail-wm0-x22f.google.com with SMTP id a8-v6so39183225wmg.5 for ; Tue, 29 May 2018 03:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6gS5dakbzi/Qoi2hMRV3+q4cQcdXxV2ENS7muhp21ik=; b=bM8xu59rvQjCyDlws6wcAvulsRaUL+zIUvjNY3PKdRFDdmi03zVZLpZtLNyx234Pu7 8XEoOzakqjjIjtRqUVsTJIiFw1YGB7tzZEwUQpSfeNWOErEWIp4YcBPz51K+bbEkpfyJ Ll4tc85aTV7AEadTcmO2km1xFkUEQaX9nZ1cSMh2WKEBrzQuKjcsHSugxec65zyPYj3z p5n0H/0+F9oUZ3MasPk175blByeRPVwazLJLIiSQBNFIyJngeZyHbddFr0ojpQJiakQ3 RDqJZQOI6CqXE8fTLZ39ZJYGWs2/zgRno1G4/LuXHpn5h2M5f86emCQUvmo54oLOSJd8 Zcbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6gS5dakbzi/Qoi2hMRV3+q4cQcdXxV2ENS7muhp21ik=; b=SjXfepfC7Lzvnnod/xO9bs/5AbTNI34SFYglkpgVcADHASCkLBBMjA3jtUPKjUmT/Q /p6SSDjrBLtl+cHeQ5OUQCU2P/t75e7GPbK6qb/HqkXDi6AnfZtouDCicD9RnSRbV5g9 MFD1a7NQqC5p2B1lAZTuzXqePZvel8hFnirxZrHHfy0CcRqG95i7+MSgNE2iMlNiAbz5 pr4kaZu931lvTHulUsYygeQBiQihkpnn+zE/1ntjLuDMZkoGN3QqV6iJeOJnkH1kZODC 4xBAsvNjOGtMhOMnBmYagiL6uaEDPrZXbuJhH3xiJ40m+q213AVrMkwFMdhlWPwiSv6d qkZg== X-Gm-Message-State: ALKqPweoWhX+/KQK6WabAxuVkE093rEnVtOQ2PCFjec/vLC/PklzTpdx IjQAcyCwXM6F6D8xIZh3k0KvLQ== X-Google-Smtp-Source: AB8JxZq8AvSj4bWNJN1pwhTIeXFrYUQjEptFyaUgPSd/s/RihKjxkt0boAOzyXL2hzzr9fpZ5aR1Gw== X-Received: by 2002:a2e:202:: with SMTP id 2-v6mr9426307ljc.117.1527591072442; Tue, 29 May 2018 03:51:12 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id x10-v6sm4922506lfe.39.2018.05.29.03.51.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:11 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:09 +0200 Message-Id: <20180529105011.1914-37-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22f Subject: [Qemu-devel] [PULL v1 36/38] target-microblaze: Use tcg_gen_movcond in eval_cond_jmp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Cleanup eval_cond_jmp to use tcg_gen_movcond_i64(). No functional change. Suggested-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 591d232304..b79600cba5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1171,12 +1171,16 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false) { - TCGLabel *l1 = gen_new_label(); - /* Conditional jmp. */ - tcg_gen_mov_i64(cpu_SR[SR_PC], pc_false); - tcg_gen_brcondi_i32(TCG_COND_EQ, env_btaken, 0, l1); - tcg_gen_mov_i64(cpu_SR[SR_PC], pc_true); - gen_set_label(l1); + TCGv_i64 tmp_btaken = tcg_temp_new_i64(); + TCGv_i64 tmp_zero = tcg_const_i64(0); + + tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); + tcg_gen_movcond_i64(TCG_COND_NE, cpu_SR[SR_PC], + tmp_btaken, tmp_zero, + pc_true, pc_false); + + tcg_temp_free_i64(tmp_btaken); + tcg_temp_free_i64(tmp_zero); } static void dec_bcc(DisasContext *dc) From patchwork Tue May 29 10:50:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 922003 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hGlgDS1O"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wBH637MXz9s0W for ; Tue, 29 May 2018 21:25:38 +1000 (AEST) Received: from localhost ([::1]:60290 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcky-0001ol-3y for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:25:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDk-00020c-C7 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDj-0004PU-Jw for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:16 -0400 Received: from mail-wr0-x233.google.com ([2a00:1450:400c:c0c::233]:36897) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDj-0004OP-D2 for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:15 -0400 Received: by mail-wr0-x233.google.com with SMTP id i12-v6so24714572wrc.4 for ; Tue, 29 May 2018 03:51:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pjJuGPh/sdSV/8JPrUjXBhqQA6Hwj/VEXz9PYM/PDa0=; b=hGlgDS1OTiqgKkrUlQLUXZW0/10c1+wZkHhGU9iCsHXqasl8+u2Xo/UMM2xlfZq9Dh 1iNjOu+X8bAC3Tg4o8HHoJTKjHrWD+xW6sZSPGX4uazFXwK5X57GQj2GhX8qxNfJq3Lx b5wfukmjxv4Q98Qyql+dbO6TlBOCWIEKgaLTsa/qncIwQXCamnB5BjDwoaTAACDg7J8s +breJNRZ1uP+hkxfcWbX2DCNFbfLzbH3k2Lx+4Dqb+KHy3ghRf6d4TzculNuhCzmprtb 7cuUbb3L2GMpQJAWYghrE0xhSX9j06s38gNMdglNDxBkVqemIalflda9cZNceK4TdM+w 76dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pjJuGPh/sdSV/8JPrUjXBhqQA6Hwj/VEXz9PYM/PDa0=; b=Vl7h/+z/vsltN5O2RkfNYqY5CO9L2BpmSzmG5/B/T80JxfpBJNp8k08l/gf43ewrMJ 2pouqSR4jqT6Ly5r4TLRLM03o44gXsGLU8WW42n/MjiyFPk87IZDW/FPs3znaUcupN26 4tRHypmF3kgafx1EvmspTSeGOH2w107XU47R6rMCBmOl6mWdd2lc8w57IfgZ5/paePRz 75S8eoxga0cEBth9tAr+ivtZ5Fu9oBsmXZ9WLsBe0VZ2UQEkvYFzIxeY8zXsvYDAfW4B 8I0yUN6yymKKlBd5Ctf/4HILm6hN/TdXTS9ysVXjHb8RQNCcGyHBYbRLGf4u2gR1UzxL oQfA== X-Gm-Message-State: ALKqPwd8C30Ndk7Rrn0UF0zADyO06Y9Hp/3Hpf7okM/SkTATRXIpipYo i3uh/D/1sI+gk6rKm21DX92jAQ== X-Google-Smtp-Source: ADUXVKLflT19nt4xVRa0mewO3W8dJmeRfCD+XIPvXcwq/P8xbkohePgYhWRXl32MEEtfwLK8i+IO4w== X-Received: by 2002:a19:1460:: with SMTP id k93-v6mr8945484lfi.23.1527591074044; Tue, 29 May 2018 03:51:14 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id y12-v6sm6398826lji.34.2018.05.29.03.51.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:13 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:10 +0200 Message-Id: <20180529105011.1914-38-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [PULL v1 37/38] target-microblaze: cpu_mmu_index: Fixup indentation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Fixup the indentation of cpu_mmu_index in preparation for future edits. No functional changes. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e38580cd7f..c77ca2d8f9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -360,13 +360,15 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) { - /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM)) - return MMU_NOMMU_IDX; - - if (env->sregs[SR_MSR] & MSR_UM) - return MMU_USER_IDX; - return MMU_KERNEL_IDX; + /* Are we in nommu mode?. */ + if (!(env->sregs[SR_MSR] & MSR_VM)) { + return MMU_NOMMU_IDX; + } + + if (env->sregs[SR_MSR] & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; } int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, From patchwork Tue May 29 10:50:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 921996 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IFHpdw58"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40wB7823ggz9s08 for ; Tue, 29 May 2018 21:18:44 +1000 (AEST) Received: from localhost ([::1]:60237 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNceH-0005jD-Sr for incoming@patchwork.ozlabs.org; Tue, 29 May 2018 07:18:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37302) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNcDl-000223-Md for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNcDk-0004Qg-Uw for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:17 -0400 Received: from mail-wr0-x233.google.com ([2a00:1450:400c:c0c::233]:38921) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNcDk-0004Pu-PC for qemu-devel@nongnu.org; Tue, 29 May 2018 06:51:16 -0400 Received: by mail-wr0-x233.google.com with SMTP id w7-v6so12758932wrn.6 for ; Tue, 29 May 2018 03:51:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eMjuQcfsZnB++oUbJKAM1+OQHTUybkPf00CSKZtq8Dk=; b=IFHpdw58RAYKcm55TMRBs+q7z0ZJuDdyr0ES5Pq3UZVvxzRBMPqZWAk+OlCO3PAjmg ztwWiUQUaRlA/n+oenDtmP0201JIKo21s/0D3Yw8U/H1hsBg0NU/z45xqb9rW0bto27F Srx+JMxqSf2FOhs8GxWJGiU/3Uz/tW+KZ92xMTZVyMAZ44lITtiIo+/GdQHxMwbsf2wL WoVj9/UYWF/oKBzi4Lsj7j4MZfqi2w1ampDD/UBrAjBxrBvKoEiKpCIk1iWU1Nit+NyD q/vFLTkvlFr+2yQ1+/fzvmH5/LxTkBgdDPD9jFmIez9C9/V+gE991dSiUvirh8z+UMV0 H7BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eMjuQcfsZnB++oUbJKAM1+OQHTUybkPf00CSKZtq8Dk=; b=TGw7bfgQZcmaQIiSF7hHgw2IWHS9wUWUTjoBDVoAa8iz/q4sQA1IXfvBQRg+sRLHWW 2bts75NyOpHr7EG8Y856WjeEW1pg0t/oifyphJGxpzQXloaJZqBRnf/J1bXyLALHuPtr LbHTl785v9iZ1Z0sM0rqX4LLS+r10ongM1D1eNq2OU60bkcbE9rOdITQ1W91qzpsEMYW sZA0wVeEpXdMudQa5j/HZYZpSxJf94icginHhSbViKsi/CRGS+2QzPAUmR3Pw2Jv6Qcz 04gdll/83suNek1XmvdSMHWlDjAH2YbSES2a+/w5r7/G3Nx48Em+Bf6GfjvBpMolzFBT NQPw== X-Gm-Message-State: ALKqPwc9wgpfjABXQx9fO+6Ip6FONB2tpOTPqfz3J0p/8qS8/RsPBJd5 rKLpUKWsAdwx6kd2W3uwyN4uyA== X-Google-Smtp-Source: ADUXVKJyNL1KY7IiD2rO1svLufitx7cWKJuWaX9Neg5AezXKoFBNSBTWvxKpaNzbijEKNs5BG+kyig== X-Received: by 2002:a19:f611:: with SMTP id x17-v6mr8788219lfe.116.1527591075469; Tue, 29 May 2018 03:51:15 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id r81-v6sm6299546lja.36.2018.05.29.03.51.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 03:51:14 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 29 May 2018 12:50:11 +0200 Message-Id: <20180529105011.1914-39-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180529105011.1914-1-edgar.iglesias@gmail.com> References: <20180529105011.1914-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [PULL v1 38/38] target-microblaze: Consolidate MMU enabled checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Consolidate MMU enabled checks to cpu_mmu_index(). No functional changes. Suggested-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 4 +++- target/microblaze/helper.c | 6 +++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c77ca2d8f9..3c4e0ba80a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -360,8 +360,10 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) { + MicroBlazeCPU *cpu = mb_env_get_cpu(env); + /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM)) { + if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { return MMU_NOMMU_IDX; } diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 985bdae8d1..bc753793ec 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -58,8 +58,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int prot; /* Translate if the MMU is available and enabled. */ - if (cpu->cfg.use_mmu && (env->sregs[SR_MSR] & MSR_VM) - && mmu_idx != MMU_NOMMU_IDX) { + if (mmu_idx != MMU_NOMMU_IDX) { uint32_t vaddr, paddr; struct microblaze_mmu_lookup lu; @@ -270,9 +269,10 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) CPUMBState *env = &cpu->env; target_ulong vaddr, paddr = 0; struct microblaze_mmu_lookup lu; + int mmu_idx = cpu_mmu_index(env, false); unsigned int hit; - if (env->sregs[SR_MSR] & MSR_VM) { + if (mmu_idx != MMU_NOMMU_IDX) { hit = mmu_translate(&env->mmu, &lu, addr, 0, 0); if (hit) { vaddr = addr & TARGET_PAGE_MASK;