From patchwork Mon May 21 20:57:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 917858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IKduv3cL"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40qWMB2cqRz9s19 for ; Tue, 22 May 2018 06:57:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751579AbeEUU54 (ORCPT ); Mon, 21 May 2018 16:57:56 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:45191 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751485AbeEUU5o (ORCPT ); Mon, 21 May 2018 16:57:44 -0400 Received: by mail-wr0-f196.google.com with SMTP id w3-v6so9579685wrl.12; Mon, 21 May 2018 13:57:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=R1uJsf6BvS/REaZUeLDKbp5xwEBVq6EWzJrQWUbub94=; b=IKduv3cLsEiVjbsYwxuxjT83X3BViQS8DYFLf/CUcUctQisBFTwA0keUeZ0Eqp4HmJ dxkXnTG6ftOrPVW5DeVq+nvFhiueL2dup7CvBaeqQ6vBuNpqi2gvqM4curUmqTkh9MrI RzRQaRbisCKP30T8ZoCCUkrNcmQfH1FxYSaUidlasBeyCA5ZfBYpcMn8accyB2Z74Ibj 8fefK5gcOGt3SVxJtKn2ksdSuQk7SP3Og4cDFWN/TU7UnuakBLb/s4ojd3fFbN8Rjwh6 MQkbb191Jo0N7AGGTmkSIvS9EaBAj5i7LYwr4FEegNLb1XxA6o6X9/BBU7iixwiRly4h 5XtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=R1uJsf6BvS/REaZUeLDKbp5xwEBVq6EWzJrQWUbub94=; b=Ytbo5snYKM3t1EUnaF/yKYOX2vjOJjY4SisUeJdbWcThJGaqBdeEEb/aPOxMtkaoQi VELVIW/OOac2zM4Ubwcr0IFyirNynuEO+Lm4MZ58aF/w+bSSMFqin61tLc2OkYqXNyga PZjfqotsyGp6FxB9/o+pddHPJi4TXog/glIJcFFKxi2PZz766Dhy/v7ZGWTVYQPXb5xe lMkGSNrC2w/MI5/aDe+Ok9oaBYjhRtWzLkwlVj55MMG8h2yVMgGqspb7PbYiTVabce8M uU0Kn0FxnqyNbbjCPE7BWUEO21E1rzOuksziwW5DYctUe1SM0gGvpXXIq3iEjsx+I+hX uGfQ== X-Gm-Message-State: ALKqPwf+DmWSp2mr+FkMPAQlCPF1lp75g5Gv2TrpOw/tDT33PHRkWIZK vz2/CXsTSF9cLhy167/qwHo= X-Google-Smtp-Source: AB8JxZpl/SeVUWXzoMnYrbk9l9JnF8R4241qpP60aYE3reSUduxCPSz41cjhN6FEArsVqbbCYK1mZA== X-Received: by 2002:adf:b004:: with SMTP id f4-v6mr17267046wra.75.1526936262797; Mon, 21 May 2018 13:57:42 -0700 (PDT) Received: from debian64.daheim (p5B0D7D7A.dip0.t-ipconnect.de. [91.13.125.122]) by smtp.gmail.com with ESMTPSA id y7-v6sm6043151wrh.86.2018.05.21.13.57.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 13:57:41 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.91) (envelope-from ) id 1fKrsB-00064q-Gq; Mon, 21 May 2018 22:57:39 +0200 From: Christian Lamparter To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Bjorn Andersson , Linus Walleij , Stephen Boyd , David Brown , Rob Herring , Mark Rutland , Andy Gross , Sven Eckelmann Subject: [PATCH v5 1/4] dt-bindings: pinctrl: qcom: add gpio-ranges, gpio-reserved-ranges Date: Mon, 21 May 2018 22:57:36 +0200 Message-Id: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> X-Mailer: git-send-email 2.17.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds the gpio-ranges and gpio-reserved-ranges property definitions to the binding text files supported by the pinctrl-msm driver framework. gpio-ranges: For DT-based platforms the pinctrl-msm framework currently relies on the deprecated-for-DT gpiochip_add_pin_range() function to add the range of GPIOs to be handled by the pin controller. Due to interactions within gpiolib code, this causes the pinctrl-msm driver to bail out (-517) during boot when a gpio-hog is declared. This can be fatal and cause the system to not boot or reset (for a detailed explanation and call-trace, refer to patch: "pinctrl: msm: fix gpio-hog related boot issues" in this series). gpio-reserved-ranges: The binding has been added as a precaution since the TrustZone firmware (aka QSEE), which is running as the hypervisor, might have reserved certain, but undisclosed pins. Hence reading or writing to the registers for those pins will cause an XPU violation and this subsequently crashes the kernel. Signed-off-by: Christian Lamparter --- .../bindings/pinctrl/qcom,apq8064-pinctrl.txt | 6 ++++++ .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 11 +++++++++++ .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt | 6 ++++++ .../bindings/pinctrl/qcom,ipq8064-pinctrl.txt | 6 ++++++ .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 10 ++++++++++ .../bindings/pinctrl/qcom,mdm9615-pinctrl.txt | 11 +++++++++++ .../bindings/pinctrl/qcom,msm8660-pinctrl.txt | 6 ++++++ .../bindings/pinctrl/qcom,msm8916-pinctrl.txt | 11 +++++++++++ .../bindings/pinctrl/qcom,msm8960-pinctrl.txt | 11 +++++++++++ .../bindings/pinctrl/qcom,msm8974-pinctrl.txt | 6 ++++++ .../bindings/pinctrl/qcom,msm8994-pinctrl.txt | 11 +++++++++++ .../bindings/pinctrl/qcom,msm8996-pinctrl.txt | 11 +++++++++++ 12 files changed, 106 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt index a752a4716486..7f78c6bb4e35 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt @@ -10,6 +10,11 @@ Required properties: - #gpio-cells : Should be two. The first cell is the gpio pin number and the second cell is used for optional parameters. +- gpio-ranges: Range of pins managed by the GPIO controller. + +Optional properties: + +- gpio-reserved-ranges: Range of pins reserved by the TrustZone TEE. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -67,6 +72,7 @@ Example: pinctrl-names = "default"; pinctrl-0 = <&gsbi5_uart_default>; + gpio-ranges = <&msmgpio 0 0 90>; gsbi5_uart_default: gsbi5_uart_default { mux { diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt index c4ea61ac56f2..362f32b945af 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt @@ -40,6 +40,16 @@ MSM8960 platform. Definition: must be 2. Specifying the pin number and flags, as defined in +- gpio-ranges: + Usage: required + Value type: + Definition: Range of pins managed by the GPIO controller. + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: Range of pins reserved by the TrustZone TEE. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -154,6 +164,7 @@ Example: gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 147>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0 208 0>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt index 93374f478b9e..7323bc54a1a0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt @@ -13,6 +13,11 @@ Required properties: - #gpio-cells : Should be two. The first cell is the gpio pin number and the second cell is used for optional parameters. +- gpio-ranges: Range of pins managed by the GPIO controller. + +Optional properties: + +- gpio-reserved-ranges: Range of pins reserved by the TrustZone TEE. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -64,6 +69,7 @@ Example: gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 100>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0 208 0>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt index 6e88e91feb11..e6843ef15169 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt @@ -10,6 +10,11 @@ Required properties: - #gpio-cells : Should be two. The first cell is the gpio pin number and the second cell is used for optional parameters. +- gpio-ranges: Range of pins managed by the GPIO controller. + +Optional properties: + +- gpio-reserved-ranges: Range of pins reserved by the TrustZone TEE. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -67,6 +72,7 @@ Example: gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinmux 0 0 69>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0 32 0x4>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt index 407b9443629d..e4d7ebcda0b0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt @@ -39,6 +39,15 @@ IPQ8074 platform. Value type: Definition: must be 2. Specifying the pin number and flags, as defined in +- gpio-ranges: + Usage: required + Value type: + Definition: Range of pins managed by the GPIO controller. + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: Range of pins reserved by the TrustZone TEE. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -148,6 +157,7 @@ Example: interrupts = ; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 70>; interrupt-controller; #interrupt-cells = <2>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt index 1b52f01ddcb7..6a104f7800f9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt @@ -40,6 +40,16 @@ MDM9615 platform. Definition: must be 2. Specifying the pin number and flags, as defined in +- gpio-ranges: + Usage: required + Value type: + Definition: Range of pins managed by the GPIO controller. + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: Range of pins reserved by the TrustZone TEE. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -127,6 +137,7 @@ Example: gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&msmgpio 0 0 88>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0 16 0x4>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt index df9a838ec5f9..311ea80a0101 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt @@ -10,6 +10,11 @@ Required properties: - #gpio-cells : Should be two. The first cell is the gpio pin number and the second cell is used for optional parameters. +- gpio-ranges: Range of pins managed by the GPIO controller. + +Optional properties: + +- gpio-reserved-ranges: Range of pins reserved by the TrustZone TEE. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -62,6 +67,7 @@ Example: gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&msmgpio 0 0 173>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0 16 0x4>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt index 498caff6029e..99d1629f0940 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt @@ -40,6 +40,16 @@ MSM8916 platform. Definition: must be 2. Specifying the pin number and flags, as defined in +- gpio-ranges: + Usage: required + Value type: + Definition: Range of pins managed by the GPIO controller. + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: Range of pins reserved by the TrustZone TEE. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -162,6 +172,7 @@ Example: interrupts = <0 208 0>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 122>; interrupt-controller; #interrupt-cells = <2>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt index eb8d8aa41f20..b1ad096ad60d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt @@ -40,6 +40,16 @@ MSM8960 platform. Definition: must be 2. Specifying the pin number and flags, as defined in +- gpio-ranges: + Usage: required + Value type: + Definition: Range of pins managed by the GPIO controller. + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: Range of pins reserved by the TrustZone TEE. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -156,6 +166,7 @@ Example: gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&msmgpio 0 0 152>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0 16 0x4>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt index 453bd7c76d6b..54eda96a0d95 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt @@ -10,6 +10,11 @@ Required properties: - #gpio-cells : Should be two. The first cell is the gpio pin number and the second cell is used for optional parameters. +- gpio-ranges: Range of pins managed by the GPIO controller. + +Optional properties: + +- gpio-reserved-ranges: Range of pins reserved by the TrustZone TEE. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -87,6 +92,7 @@ Example: gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&msmgpio 0 0 146>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0 208 0>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt index 13cd629f896e..58208f2eb455 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt @@ -42,6 +42,16 @@ MSM8994 platform. Definition: must be 2. Specifying the pin number and flags, as defined in +- gpio-ranges: + Usage: required + Value type: + Definition: Range of pins managed by the GPIO controller. + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: Range of pins reserved by the TrustZone TEE. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -160,6 +170,7 @@ Example: interrupts = ; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&msmgpio 0 0 146>; interrupt-controller; #interrupt-cells = <2>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt index aaf01e929eea..65f5e901ee1a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt @@ -40,6 +40,16 @@ MSM8996 platform. Definition: must be 2. Specifying the pin number and flags, as defined in +- gpio-ranges: + Usage: required + Value type: + Definition: Range of pins managed by the GPIO controller. + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: Range of pins reserved by the TrustZone TEE. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. @@ -180,6 +190,7 @@ Example: reg = <0x01010000 0x300000>; interrupts = <0 208 0>; gpio-controller; + gpio-ranges = <&tlmm 0 0 150>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From patchwork Mon May 21 20:57:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 917855 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="E/SrOxlB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40qWM52r7tz9s19 for ; Tue, 22 May 2018 06:57:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751524AbeEUU5u (ORCPT ); Mon, 21 May 2018 16:57:50 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:34239 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751214AbeEUU5o (ORCPT ); Mon, 21 May 2018 16:57:44 -0400 Received: by mail-wr0-f194.google.com with SMTP id j1-v6so6340873wrm.1; Mon, 21 May 2018 13:57:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=BppZUp8Muj/bD7c/+SlZsXKrwKEbkwqAs4P9e67lWTc=; b=E/SrOxlBTQwOl0uceuvAQCYOBoPO8zfA8QY8uDAmUnHVG1AlHMTDV/seQjLXPiMwj6 TObv/psYmkj4APscqhigxZ/CZJh4zmro2MCDp+BbDzIRMG+vHR80Gjpwhq97jhdi4jZ/ ZJJhWrAbhJmffO+LReSJXtc5enDyYmXwSRBPemJ/wk3HlkjHgl7/pNXaN1HMvmC9k0WU bM71HJdANmE6e3sOuyCCRM4ulBRmbPdhLdI3T8UN23K7N//J930ycxCJ5k5k9SOTo0iu UL+hJB+YhVCS/Ko6s+WvIITiGcowPB/RgQBAiyrFFoO9ff9WkkgDl4LWQnCSWQC/fKwl 4TVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=BppZUp8Muj/bD7c/+SlZsXKrwKEbkwqAs4P9e67lWTc=; b=gglrx4h3l6Lhog5goSAnshp6/JOXL2coTaglZppSfPVjXCjVYoG2F1iDKNj8DvaRjM CwACaQ6S1d2hgWegroSipHSG/JtFQYWHUz7Uc/ClaAVGvG/Ir5PlaSHzBSh28Qp0XgWQ ptpazWIbGWo5pTJYvsbRr+ewfgq3uEdLhRLqptguXXuVG6isrzoK0pZZakgjyf82CK76 FhgWCfbBypA3WA+b4Uy0jeezWfI30DxsstDrLKly1y2lAr5JUtHMo9yqnKAodgLqTekX 73GsYNLBGqHJOolklGdxHXguzfQDltvzvJ3/QyjQ4SmlnYL1YDDUWSXCt5gH6xFSGlup v6Xw== X-Gm-Message-State: ALKqPwcfD0dYaFDUCi92Hs0Gvq9LBBTM/df9hNs8l9eJhmLqt5vu8ZDP Bvb53AgmAAdFEHAEcAXAvVk= X-Google-Smtp-Source: AB8JxZqNTjHRoe1+JmMduAs1wftduilLvG1SnMSNmyvkSgHNaeJ63mPd0Jr2aKJp0kFpkBTDCfkaPQ== X-Received: by 2002:adf:b0e2:: with SMTP id j31-v6mr15365616wra.263.1526936262423; Mon, 21 May 2018 13:57:42 -0700 (PDT) Received: from debian64.daheim (p5B0D7D7A.dip0.t-ipconnect.de. [91.13.125.122]) by smtp.gmail.com with ESMTPSA id h8-v6sm11275007wmc.16.2018.05.21.13.57.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 13:57:41 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.91) (envelope-from ) id 1fKrsB-00064u-I4; Mon, 21 May 2018 22:57:39 +0200 From: Christian Lamparter To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Bjorn Andersson , Linus Walleij , Stephen Boyd , David Brown , Rob Herring , Mark Rutland , Andy Gross , Sven Eckelmann Subject: [PATCH v5 2/4] pinctrl: msm: fix gpio-hog related boot issues Date: Mon, 21 May 2018 22:57:37 +0200 Message-Id: <270904bcbf03a6b6ac3150f4a7daa15aa7e97586.1526935804.git.chunkeey@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> References: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> In-Reply-To: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> References: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Sven Eckelmann reported an issue with the current IPQ4019 pinctrl. Setting up any gpio-hog in the device-tree for his device would "kill the bootup completely": | [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe | [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe | [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517 | [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register | [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip | [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe | [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri This was also verified on a RT-AC58U (IPQ4018) which would no longer boot, if a gpio-hog was specified. (Tried forcing the USB LED PIN (GPIO0) to high.). The problem is that Pinctrl+GPIO registration is currently peformed in the following order in pinctrl-msm.c: 1. pinctrl_register() 2. gpiochip_add() 3. gpiochip_add_pin_range() The actual error code -517 == -EPROBE_DEFER is coming from pinctrl_get_device_gpio_range(), which is called through: gpiochip_add of_gpiochip_add of_gpiochip_scan_gpios gpiod_hog gpiochip_request_own_desc __gpiod_request chip->request gpiochip_generic_request pinctrl_gpio_request pinctrl_get_device_gpio_range pinctrl_get_device_gpio_range() is unable to find any valid pin ranges, since nothing has been added to the pinctrldev_list yet. so the range can't be found, and the operation fails with -EPROBE_DEFER. This patch fixes the issue by adding the "gpio-ranges" property to the pinctrl device node of all upstream Qcom SoC. The pin ranges are then added by the gpio core. In order to remain compatible with older, existing DTs (and ACPI) a check for the "gpio-ranges" property has been added to msm_gpio_init(). This prevents the driver of adding the same entry to the pinctrldev_list twice. Reported-by: Sven Eckelmann Tested-by: Sven Eckelmann [ipq4019] Reviewed-by: Bjorn Andersson Signed-off-by: Christian Lamparter --- drivers/pinctrl/qcom/pinctrl-msm.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index ad80a17c9990..ace2bfbf1bee 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -890,11 +890,24 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) return ret; } - ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); - if (ret) { - dev_err(pctrl->dev, "Failed to add pin range\n"); - gpiochip_remove(&pctrl->chip); - return ret; + /* + * For DeviceTree-supported systems, the gpio core checks the + * pinctrl's device node for the "gpio-ranges" property. + * If it is present, it takes care of adding the pin ranges + * for the driver. In this case the driver can skip ahead. + * + * In order to remain compatible with older, existing DeviceTree + * files which don't set the "gpio-ranges" property or systems that + * utilize ACPI the driver has to call gpiochip_add_pin_range(). + */ + if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { + ret = gpiochip_add_pin_range(&pctrl->chip, + dev_name(pctrl->dev), 0, 0, chip->ngpio); + if (ret) { + dev_err(pctrl->dev, "Failed to add pin range\n"); + gpiochip_remove(&pctrl->chip); + return ret; + } } ret = gpiochip_irqchip_add(chip, From patchwork Mon May 21 20:57:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 917856 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="F8+CFKSu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40qWM86r0qz9s4k for ; Tue, 22 May 2018 06:57:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751559AbeEUU5y (ORCPT ); Mon, 21 May 2018 16:57:54 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:33848 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751486AbeEUU5p (ORCPT ); Mon, 21 May 2018 16:57:45 -0400 Received: by mail-wm0-f68.google.com with SMTP id a137-v6so13475182wme.1; Mon, 21 May 2018 13:57:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=kl/ecqRPGFBMFyoceo7U94GwLWZLQkfVhJSJLbM7Bzk=; b=F8+CFKSuDynHFgUhOQfsJZ8YF2P59woaqY7/kd5eBwIy86LrVkw3cNJSEILufA6ga7 1r94ZcfM4ukDIyUmQ2JRK1RMJ+01QfwiQl2Lg9oDkjKqAxhscUKsFtJ0+bVTdaDfHQma btvqplV6gd8Bs4OX4ZlnmiHqmUSPYIfeFLCQ3IHrKUXF1+pbH+tN0Vr0A5n9CtYchXYp pQC3h1Yq/clZYCprMyeXxAnBHe08uPXG1DHQSnPMEPHf8E3KzrhYzeTdzlOLE8Y0hHmn BCtTq9UfW4bi/eZmakGFXQT0sLexVUSh0BqLF6ZyDUd8tP+n9FxQ/jurIjnHODY5C92j 43iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=kl/ecqRPGFBMFyoceo7U94GwLWZLQkfVhJSJLbM7Bzk=; b=XCZKSJVCvCWx2BpoeJAl6o5FcQmJEIetepLAXvXkfZN/LYsQFPKNZ1NbuQvxTqAEjl woWvf3Zl7ZrAyoupyHOdmdFX4Hu9pYj5TfsHM7ZstzVPEdesP/NY164Iaf0KrQXu3pXT 1eJzJKqLq+/tCXP0j4XzDLYPXxjSjzdGBw2FZERUlx7xwBt7gAN9fA6y0/OPYwWLWHir ksEjXFyFF9COHvY+vagRvZir6agOZuzQYa+iYy3V/gYh2jvnmQAU34qxFxa63jyGuQzu Cyf3oie3Sz0GPSIwWCjRTNNDbJS7ISXrfnYJ4fWIB/FD3uKUg3WpTPYpYWmnF3nGoHOr JaDw== X-Gm-Message-State: ALKqPwfBBjYtavTBMUxf1eiVEKDQSLqD7pl6TyUZ0y24RP7mfLmhZi0W l6afQKeOJuiWPUROkAD+HRHHTLr8 X-Google-Smtp-Source: AB8JxZpRubAFk8Yp/1MtUzQsGuiEloqlo+PO+vNOlZr4h6YAsntqfNRz1q1i3YTggpXs2di9pECNvA== X-Received: by 2002:a1c:6b57:: with SMTP id g84-v6mr209097wmc.127.1526936263164; Mon, 21 May 2018 13:57:43 -0700 (PDT) Received: from debian64.daheim (p5B0D7D7A.dip0.t-ipconnect.de. [91.13.125.122]) by smtp.gmail.com with ESMTPSA id 42-v6sm31634655wrx.24.2018.05.21.13.57.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 13:57:41 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.91) (envelope-from ) id 1fKrsB-00064y-J4; Mon, 21 May 2018 22:57:41 +0200 From: Christian Lamparter To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Bjorn Andersson , Linus Walleij , Stephen Boyd , David Brown , Rob Herring , Mark Rutland , Andy Gross , Sven Eckelmann Subject: [PATCH v5 3/4] ARM: dts: qcom: add gpio-ranges property Date: Mon, 21 May 2018 22:57:38 +0200 Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> References: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> In-Reply-To: <270904bcbf03a6b6ac3150f4a7daa15aa7e97586.1526935804.git.chunkeey@gmail.com> References: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> <270904bcbf03a6b6ac3150f4a7daa15aa7e97586.1526935804.git.chunkeey@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds the gpio-ranges property to almost all of the Qualcomm ARM platforms that utilize the pinctrl-msm framework. The gpio-ranges property is part of the gpiolib subsystem. As a result, the binding text is available in section "2.1 gpio- and pin-controller interaction" of Documentation/devicetree/bindings/gpio/gpio.txt For more information please see the patch titled: "pinctrl: msm: fix gpio-hog related boot issues" from this series. Reported-by: Sven Eckelmann Tested-by: Sven Eckelmann [ipq4019] Reviewed-by: Bjorn Andersson Signed-off-by: Christian Lamparter Reviewed-by: Linus Walleij --- To help with git bisect, the DT update patch has been intentionally placed after the "pinctrl: msm: fix gpio-hog related boot issues". Otherwise - if the order was reveresed - and bisect decides to split between these two patches, the gpiochip_add_pin_ranges() function will be executed twice with the same parameters for the same pinctrl. --- arch/arm/boot/dts/qcom-apq8064.dtsi | 1 + arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 + arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + arch/arm/boot/dts/qcom-msm8960.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 + 13 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 5341a39c0392..4001eeb52f20 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -344,6 +344,7 @@ reg = <0x800000 0x4000>; gpio-controller; + gpio-ranges = <&tlmm_pinmux 0 0 90>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 0e1e98707e3f..d9481d083802 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -396,6 +396,7 @@ compatible = "qcom,apq8084-pinctrl"; reg = <0xfd510000 0x4000>; gpio-controller; + gpio-ranges = <&tlmm 0 0 147>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 10d112a4078e..9a81d2da87a0 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -146,6 +146,7 @@ compatible = "qcom,ipq4019-pinctrl"; reg = <0x01000000 0x300000>; gpio-controller; + gpio-ranges = <&tlmm 0 0 100>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 1e0a3b446f7a..26eab9a68d90 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -108,6 +108,7 @@ reg = <0x800000 0x4000>; gpio-controller; + gpio-ranges = <&qcom_pinmux 0 0 69>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index c852b69229c9..cfdaca5f259a 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -128,6 +128,7 @@ msmgpio: pinctrl@800000 { compatible = "qcom,mdm9615-pinctrl"; gpio-controller; + gpio-ranges = <&msmgpio 0 0 88>; #gpio-cells = <2>; interrupts = ; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 33030f9419fe..47cf9c4ca062 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -110,6 +110,7 @@ reg = <0x800000 0x4000>; gpio-controller; + gpio-ranges = <&tlmm 0 0 173>; #gpio-cells = <2>; interrupts = <0 16 0x4>; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 1733d8f40ab1..f6d8b1af5a8a 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -102,6 +102,7 @@ msmgpio: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; gpio-controller; + gpio-ranges = <&msmgpio 0 0 152>; #gpio-cells = <2>; interrupts = <0 16 0x4>; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d9019a49b292..1250e071a6e2 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -696,6 +696,7 @@ compatible = "qcom,msm8974-pinctrl"; reg = <0xfd510000 0x4000>; gpio-controller; + gpio-ranges = <&msmgpio 0 0 146>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 2bc5dec5614d..d2c36b467466 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -24,11 +24,12 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; - pinctrl@1000000 { + tlmm: pinctrl@1000000 { compatible = "qcom,ipq8074-pinctrl"; reg = <0x1000000 0x300000>; interrupts = ; gpio-controller; + gpio-ranges = <&tlmm 0 0 70>; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 66b318e1de80..9d5320b26188 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -326,6 +326,7 @@ reg = <0x1000000 0x300000>; interrupts = ; gpio-controller; + gpio-ranges = <&msmgpio 0 0 122>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 171578747ed0..173b6bc60816 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -179,6 +179,7 @@ reg = <0xfd510000 0x4000>; interrupts = ; gpio-controller; + gpio-ranges = <&msmgpio 0 0 146>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index f33c41d01c86..68705db4696b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -141,6 +141,7 @@ reg = <0xfd510000 0x4000>; interrupts = ; gpio-controller; + gpio-ranges = <&msmgpio 0 0 146>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 410ae787ebb4..b9b57808fc67 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -541,6 +541,7 @@ reg = <0x01010000 0x300000>; interrupts = ; gpio-controller; + gpio-ranges = <&msmgpio 0 0 150>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From patchwork Mon May 21 20:57:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 917859 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Z32KdykS"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40qWMP4f0lz9s4k for ; Tue, 22 May 2018 06:58:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751645AbeEUU6B (ORCPT ); Mon, 21 May 2018 16:58:01 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34241 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751496AbeEUU5p (ORCPT ); Mon, 21 May 2018 16:57:45 -0400 Received: by mail-wr0-f195.google.com with SMTP id j1-v6so6340930wrm.1; Mon, 21 May 2018 13:57:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=eaizejlibJlYozTqdHPUtzY/WRFahGx1Bc8UcJQWkE4=; b=Z32KdykSOSXb5MDh6xVbdR0d+QXTWWcR5X/ybvWQHfmCb2AZ3uFdqKU+VulHpvGaJF egStLL1wyZlV+NlNQsW7JWYd0BFwniKcuz3NICEPsjkyHHJIi5Gz5z8+0VD32oIZB8gk J2jfBu0UAelh4KOF4vWiJOU07d6uwRQhjY7IqmDRFqaH5GZIEqyMMMe61Uy7Mei+HF/F 5pra731G+V7HiSgoP58PfNoTHWhluWtwjt8uqTZ2RAFLxEgbkwSFAbxY6+Fu6T4u14l2 Z7KEQb688t6LWLCgKTVjdl0HsoZJqwqt88N1mLc6IB552NeB4a+B95wqUjwVmOy/K7Bh Rmqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=eaizejlibJlYozTqdHPUtzY/WRFahGx1Bc8UcJQWkE4=; b=GVEKIX845F7OrLsup3livyojjcUb8/9pAIbx/AfVR2F/8iydfk2IIQ574rlNvjTHcr wK6MnVfbrsRvmUp877Lde4qrMOxZYvUmySfJneoiQSSLzGxq2/TPWmYOaOF+tb2QSajG c2dsD4yILlXnt8IC80Jl5G1ACc64h4+Uq6tQx7IF9eWHjoOm6L+SDcvY58fyKQk0Jt+B STVwKQeODy0PgudzYlSCd6FbnF5l0j9lk09b+CWBu5s0cyklI6kqYfESAv3oT+kyTNno 598IDRPTZiIbMz8S1b7hwOJ7I4k5HXb/8VATPWPIqV4kEXGg1LWKRj2JEtcvRhL9dD4x YW+Q== X-Gm-Message-State: ALKqPwdzgimk6lwe1/XweI8bECbrDQY+CtBxEVgOO4C6JP3MrbjLC5Cj roH60A+ywS0dymgUGrV8sUk= X-Google-Smtp-Source: AB8JxZr7Jw39xVyQVTKvS6gTC9Fr390hPVSYq9ekWlsU8VuKZkzAjkpFoRM86WlOE/ezrB+BVyo0Qg== X-Received: by 2002:adf:9125:: with SMTP id j34-v6mr4080636wrj.156.1526936263560; Mon, 21 May 2018 13:57:43 -0700 (PDT) Received: from debian64.daheim (p5B0D7D7A.dip0.t-ipconnect.de. [91.13.125.122]) by smtp.gmail.com with ESMTPSA id x16-v6sm5425513wmc.2.2018.05.21.13.57.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 May 2018 13:57:41 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.91) (envelope-from ) id 1fKrsD-000653-2A; Mon, 21 May 2018 22:57:41 +0200 From: Christian Lamparter To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Bjorn Andersson , Linus Walleij , Stephen Boyd , David Brown , Rob Herring , Mark Rutland , Andy Gross , Sven Eckelmann Subject: [PATCH v5 4/4] gpiolib: discourage gpiochip_add_pin[group]_range for DT pinctrls Date: Mon, 21 May 2018 22:57:39 +0200 Message-Id: <2969992a1005d7e7f4ea23d4c684d2f10d4a0aca.1526935804.git.chunkeey@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> References: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> In-Reply-To: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com> References: <910e5a85a6a8020069996e2ff397c93e9c5fe18c.1526935804.git.chunkeey@gmail.com> <270904bcbf03a6b6ac3150f4a7daa15aa7e97586.1526935804.git.chunkeey@gmail.com> <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds the stern warning to the kerneldoc text of both gpiochip_add_pin[group]_range() functions in hope of detering developers from ever using them in their DeviceTree-supported pinctrl drivers in the future. For anyone affected: Please refer to Section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind pinctrl and gpio drivers via the "gpio-ranges" property. Signed-off-by: Christian Lamparter --- As a (final?) follow-up to Stephen's request of adding a warning to notify devs and users alike about any potentially broken drivers: of_gpiochip_add_pin_range() - which parses the gpio-ranges property - calls both gpiochip_add_pin(group)_range functions. So adding a warning/debug message into the code will not really work (unless the DT-check will also take the call-trace into account... which is possible, but at this point it would make more sense to just refactor the code). --- drivers/gpio/gpiolib.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index d1171db66c30..387bf0677ca8 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -2117,6 +2117,11 @@ EXPORT_SYMBOL_GPL(gpiochip_generic_config); * @pctldev: the pin controller to map to * @gpio_offset: the start offset in the current gpio_chip number space * @pin_group: name of the pin group inside the pin controller + * + * Calling this function directly from a DeviceTree-supported + * pinctrl driver is DEPRECATED. Please see Section 2.1 of + * Documentation/devicetree/bindings/gpio/gpio.txt on how to + * bind pinctrl and gpio drivers via the "gpio-ranges" property. */ int gpiochip_add_pingroup_range(struct gpio_chip *chip, struct pinctrl_dev *pctldev, @@ -2170,6 +2175,11 @@ EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range); * * Returns: * 0 on success, or a negative error-code on failure. + * + * Calling this function directly from a DeviceTree-supported + * pinctrl driver is DEPRECATED. Please see Section 2.1 of + * Documentation/devicetree/bindings/gpio/gpio.txt on how to + * bind pinctrl and gpio drivers via the "gpio-ranges" property. */ int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, unsigned int gpio_offset, unsigned int pin_offset,