From patchwork Mon May 21 17:37:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 917761 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-92634-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="u+5n/F3l"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40qQwD6Ms1z9s1w for ; Tue, 22 May 2018 03:37:48 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:subject:message-id:reply-to :mime-version:content-type; q=dns; s=default; b=WrQARvC1dSNI/Nw4 lPOcgJTd76a5HozhsXJvpmv39DcW5H4/qiWx1Dl6vD8NBK+JtPLSGwwCas+MpU7x oOk5PoOQe1ED5sJksPlHVax8mmYKrMea/87qo5cYevA3tuTJfICRuK1z8Jbn+tOg QWOEfznsXVm3DlTioviZK5rhTqY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:subject:message-id:reply-to :mime-version:content-type; s=default; bh=FITf2jvyfM1QAPRV2MWle9 S4LJ4=; b=u+5n/F3lZjDDj0JdLokLTDrQmwhhxb1reoABpfX6l6j4YMeDViOrto q2kMLtH/GPXXBc6eSEiENf1hqAjwTSdOFnnb6QZaC4S/3O/WDFu5PFq3jP5+JQZQ 4yOao0mah7sZQ4NeTmpj9GDY1+klf5KwzpZStxBORNsaMSfmIj5Og= Received: (qmail 70908 invoked by alias); 21 May 2018 17:37:43 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 70722 invoked by uid 89); 21 May 2018 17:37:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM autolearn=ham version=3.3.2 spammy=Hx-languages-length:2480 X-HELO: mga05.intel.com X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False X-ExtLoop1: 1 Date: Mon, 21 May 2018 10:37:40 -0700 From: "H.J. Lu" To: GNU C Library Subject: [PATCH] x86-64: Check Prefer_FSRM in ifunc-memmove.h Message-ID: <20180521173740.GA12107@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.9.5 (2018-04-13) Although the Fast Short REP MOVSB (FSRM) implementations of memmove, memcpy and mempcpy aren't used by the current processors, this patch adds Prefer_FSRM check in ifunc-memmove.h so that they can be used in the future. * sysdeps/x86/cpu-features.h (bit_arch_Prefer_FSRM): New. (index_arch_Prefer_FSRM): Likewise. * sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)): Also check Prefer_FSRM. * sysdeps/x86_64/multiarch/ifunc-memmove.h (IFUNC_SELECTOR): Also return OPTIMIZE (erms) for Prefer_FSRM. --- sysdeps/x86/cpu-features.h | 2 ++ sysdeps/x86/cpu-tunables.c | 2 ++ sysdeps/x86_64/multiarch/ifunc-memmove.h | 3 ++- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index 2088bd73ee..624e681e96 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -40,6 +40,7 @@ #define bit_arch_Prefer_No_AVX512 (1 << 20) #define bit_arch_MathVec_Prefer_No_AVX512 (1 << 21) #define bit_arch_XSAVEC_Usable (1 << 22) +#define bit_arch_Prefer_FSRM (1 << 23) /* CPUID Feature flags. */ @@ -264,6 +265,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_arch_Prefer_No_AVX512 FEATURE_INDEX_1 # define index_arch_MathVec_Prefer_No_AVX512 FEATURE_INDEX_1 # define index_arch_XSAVEC_Usable FEATURE_INDEX_1 +# define index_arch_Prefer_FSRM FEATURE_INDEX_1 #endif /* !__ASSEMBLER__ */ diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c index a21a615ec2..af761dcbbc 100644 --- a/sysdeps/x86/cpu-tunables.c +++ b/sysdeps/x86/cpu-tunables.c @@ -241,6 +241,8 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp) CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH (n, cpu_features, Slow_SSE4_2, SSE4_2, disable, 11); + CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features, Prefer_FSRM, + disable, 11); break; case 13: if (disable) diff --git a/sysdeps/x86_64/multiarch/ifunc-memmove.h b/sysdeps/x86_64/multiarch/ifunc-memmove.h index a2ffba0531..5b1eb1c92c 100644 --- a/sysdeps/x86_64/multiarch/ifunc-memmove.h +++ b/sysdeps/x86_64/multiarch/ifunc-memmove.h @@ -41,7 +41,8 @@ IFUNC_SELECTOR (void) { const struct cpu_features* cpu_features = __get_cpu_features (); - if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_ERMS)) + if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_ERMS) + || CPU_FEATURES_ARCH_P (cpu_features, Prefer_FSRM)) return OPTIMIZE (erms); if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable)