From patchwork Thu May 17 04:40:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keerthy X-Patchwork-Id: 915067 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Rhk+1e67"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40mdsg0gfNz9s1d for ; Thu, 17 May 2018 14:40:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750815AbeEQEkx (ORCPT ); Thu, 17 May 2018 00:40:53 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:53400 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750801AbeEQEkx (ORCPT ); Thu, 17 May 2018 00:40:53 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w4H4ebQs018236; Wed, 16 May 2018 23:40:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1526532037; bh=SWWiA/GZipHs0Xwi/NZnTAcY2jdyDE6x1lkQwB3TChs=; h=From:To:CC:Subject:Date; b=Rhk+1e67yCM35uVZu+M5NUZpXicqF3wh+FyEWbocOZS5XarEsc6XJYOxM+jkqSbQs jtHi7qh03AE/OmW9IzmY0LUYLe9xGZ0j6a6fwzzae6yWaqqa3WR3io15V8ckwS5ncW KbQjX7+Ds2cSMWvgjTjR7EYCIb3JEYTEUB5MXCBg= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4H4ebiV011609; Wed, 16 May 2018 23:40:37 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 16 May 2018 23:40:36 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 16 May 2018 23:40:36 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4H4eWQM024852; Wed, 16 May 2018 23:40:33 -0500 From: Keerthy To: , CC: , , , , Subject: [PATCH v2] pinctrl: pinctrl-single: Add functions to save and restore pinctrl context Date: Thu, 17 May 2018 10:10:21 +0530 Message-ID: <1526532021-16387-1-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds a pair of context save/restore functions to save/restore the state of a set of pinctrl registers. The context is lost during rtc only suspend with ddr in self-refresh on am43xx. Currently the save/restore is being done unconditionally. This will be optimized later with a pdata-quirk function which will allow is to save/restore only when doing the rtc only mode with ddr in self refresh. Signed-off-by: Keerthy Acked-by: Tony Lindgren --- Changes in v2: * As this is needed only the in the suspend/resume path removed the cpu_pm notifier and added the save/restore in the suspend/resume calls. * Saving/Restoring unconditionally at the moment. This will be optimized later with the help of a pdata-quirk function. drivers/pinctrl/pinctrl-single.c | 72 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index a7c5eb3..9c3c005 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -144,6 +144,7 @@ struct pcs_soc_data { * struct pcs_device - pinctrl device instance * @res: resources * @base: virtual address of the controller + * @saved_vals: saved values for the controller * @size: size of the ioremapped area * @dev: device entry * @np: device tree node @@ -172,11 +173,13 @@ struct pcs_soc_data { struct pcs_device { struct resource *res; void __iomem *base; + void *saved_vals; unsigned size; struct device *dev; struct device_node *np; struct pinctrl_dev *pctl; unsigned flags; +#define PCS_CONTEXT_LOSS_OFF (1 << 3) #define PCS_QUIRK_SHARED_IRQ (1 << 2) #define PCS_FEAT_IRQ (1 << 1) #define PCS_FEAT_PINCONF (1 << 0) @@ -1576,6 +1579,67 @@ static int pcs_irq_init_chained_handler(struct pcs_device *pcs, } #ifdef CONFIG_PM +static int pcs_save_context(struct pcs_device *pcs) +{ + int i, mux_bytes; + u64 *regsl; + u32 *regsw; + u16 *regshw; + + mux_bytes = pcs->width / BITS_PER_BYTE; + + if (!pcs->saved_vals) + pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); + + switch (pcs->width) { + case 64: + regsl = (u64 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + regsl[i] = pcs->read(pcs->base + i * mux_bytes); + break; + case 32: + regsw = (u32 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + regsw[i] = pcs->read(pcs->base + i * mux_bytes); + break; + case 16: + regshw = (u16 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + regshw[i] = pcs->read(pcs->base + i * mux_bytes); + break; + } + + return 0; +} + +static void pcs_restore_context(struct pcs_device *pcs) +{ + int i, mux_bytes; + u64 *regsl; + u32 *regsw; + u16 *regshw; + + mux_bytes = pcs->width / BITS_PER_BYTE; + + switch (pcs->width) { + case 64: + regsl = (u64 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + pcs->write(regsl[i], pcs->base + i * mux_bytes); + break; + case 32: + regsw = (u32 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + pcs->write(regsw[i], pcs->base + i * mux_bytes); + break; + case 16: + regshw = (u16 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + pcs->write(regshw[i], pcs->base + i * mux_bytes); + break; + } +} + static int pinctrl_single_suspend(struct platform_device *pdev, pm_message_t state) { @@ -1585,6 +1649,9 @@ static int pinctrl_single_suspend(struct platform_device *pdev, if (!pcs) return -EINVAL; + if (pcs->flags & PCS_CONTEXT_LOSS_OFF) + pcs_save_context(pcs); + return pinctrl_force_sleep(pcs->pctl); } @@ -1596,6 +1663,9 @@ static int pinctrl_single_resume(struct platform_device *pdev) if (!pcs) return -EINVAL; + if (pcs->flags & PCS_CONTEXT_LOSS_OFF) + pcs_restore_context(pcs); + return pinctrl_force_default(pcs->pctl); } #endif @@ -1824,7 +1894,7 @@ static int pcs_remove(struct platform_device *pdev) }; static const struct pcs_soc_data pinctrl_single_am437x = { - .flags = PCS_QUIRK_SHARED_IRQ, + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */ .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ };