From patchwork Wed May 16 09:13:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 914280 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="F+pTIj6d"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40m7zc1wcWz9s2k for ; Wed, 16 May 2018 19:14:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E4652C21E16; Wed, 16 May 2018 09:14:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 18999C21C29; Wed, 16 May 2018 09:14:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 695B0C21C29; Wed, 16 May 2018 09:14:12 +0000 (UTC) Received: from mail-wr0-f194.google.com (mail-wr0-f194.google.com [209.85.128.194]) by lists.denx.de (Postfix) with ESMTPS id 36E47C21BE5 for ; Wed, 16 May 2018 09:14:11 +0000 (UTC) Received: by mail-wr0-f194.google.com with SMTP id y15-v6so57079wrg.11 for ; Wed, 16 May 2018 02:14:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=JNLEkNdxGh8QG9sl4T3JnXI0FVoiD4RVgSDZHRclEzY=; b=F+pTIj6dEE8N0MEojKSWel485u0JRT8H1IiycRl4Xfij9ClbYh19VV6lGBuf6ElPOA abE3kuhuLOA0E/6JBAcIgThRe2LzFauq+g4KBWP00OAbd7H9Kd7z6ZcX87N/V44ItRa7 BlT0JFPTf18Sx2a+d0MBkXPbeU99Z8/42utc8AFvVRpmlqZ81CuxGK9hhdjQO9XHThTO ccGacNku8Gi+ci0frxuvuVK238iA1D3xRCl0ukbn/rYMLITFByxJS6w4wutkk3IngKFf G75Ec/o0UldvICCmlCM3ea68sR0EKbPh69iGu73usrFJ44WQd0+7qwC9e56MjZn6avX/ xpkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=JNLEkNdxGh8QG9sl4T3JnXI0FVoiD4RVgSDZHRclEzY=; b=KQ/0kvH/NC1dqgjrbd5K/cHUmsUV2ajyaXPD086cWRWTnVyACQ8dSyOL1GbyCenpPG KqIheH1JjAkSKQwAcPvw7vi2RO5ubsQJc4y7dEVCrh2CXc9fJhrdgHuAtzlogAcZqWkc nJecXlTbUQLM4TtsO0LstPoXYgcY4CMuKBFHQt7clISHxcex/5GrfgGqfeVD+TrZVi0A wpGOq3VmJwDoeGrI5+/gpBxrTB37iuin1u6z91scmREoWuFQsExhxLd4DW2zSILUOKoq 6v4e1ocZfS1TcxhAUlT+7i+YGYRMDM2WcTfKYAMJ2Jobiozu3kZ65cEEgiOYBBsP5Jgj o5Yg== X-Gm-Message-State: ALKqPwdY/7HTPrQQH1YK22RCUzGSiQcn0zkZc3es6VtRPupEtJZxppTf nbCgFmm7Wy7YXIl23uf8nmI= X-Google-Smtp-Source: AB8JxZriPh1yL4tIgB3TnJMw8sCkWbe1+GbjWOHvvRxCuOeoL1wJAf6Ly35KmZs80yRiZHcLKQy5ng== X-Received: by 2002:adf:8ac5:: with SMTP id z5-v6mr80214wrz.22.1526462050788; Wed, 16 May 2018 02:14:10 -0700 (PDT) Received: from localhost.localdomain ([141.226.166.38]) by smtp.gmail.com with ESMTPSA id h12-v6sm1920655wmc.7.2018.05.16.02.14.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 May 2018 02:14:10 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Wed, 16 May 2018 12:13:36 +0300 Message-Id: <20180516091342.7509-1-ramon.fried@gmail.com> X-Mailer: git-send-email 2.17.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 1/7] db820c: set clk node to be probed before relocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The clock and serial nodes are needed before relocation. This patch ensures that the msm-serial driver will probe and provide uart output before relocation. Signed-off-by: Ramon Fried Reviewed-by: Simon Glass --- v2: fixed alignment arch/arm/dts/dragonboard820c-uboot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi index 88312b3fa1..97394cc5b0 100644 --- a/arch/arm/dts/dragonboard820c-uboot.dtsi +++ b/arch/arm/dts/dragonboard820c-uboot.dtsi @@ -5,6 +5,20 @@ * (C) Copyright 2017 Jorge Ramirez-Ortiz */ +/ { + soc { + u-boot,dm-pre-reloc; + + clock-controller@300000 { + u-boot,dm-pre-reloc; + }; + + serial@75b0000 { + u-boot,dm-pre-reloc; + }; + }; +}; + &pm8994_pon { key_vol_down { gpios = <&pm8994_pon 1 0>; From patchwork Wed May 16 09:13:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 914281 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 16 May 2018 02:14:11 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Wed, 16 May 2018 12:13:37 +0300 Message-Id: <20180516091342.7509-2-ramon.fried@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516091342.7509-1-ramon.fried@gmail.com> References: <20180516091342.7509-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 2/7] serial: serial_msm: fail probe if settings clocks fails X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Failure to set the clocks will causes data abort exception when trying to write to AHB uart registers. This patch ensures that we don't touch these registers if clock setting failed. Signed-off-by: Ramon Fried Reviewed-by: Simon Glass --- v2: on failure, return actual return code from msm_uart_clk_init drivers/serial/serial_msm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 119e6b9846..8b585deeeb 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -181,10 +181,12 @@ static int msm_uart_clk_init(struct udevice *dev) static int msm_serial_probe(struct udevice *dev) { + int ret; struct msm_serial_data *priv = dev_get_priv(dev); - msm_uart_clk_init(dev); /* Ignore return value and hope clock was - properly initialized by earlier loaders */ + ret = msm_uart_clk_init(dev); + if (ret) + return ret; if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); From patchwork Wed May 16 09:13:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 914282 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 16 May 2018 02:14:13 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Wed, 16 May 2018 12:13:38 +0300 Message-Id: <20180516091342.7509-3-ramon.fried@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516091342.7509-1-ramon.fried@gmail.com> References: <20180516091342.7509-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 3/7] serial: serial_msm: initialize uart only before relocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The uart is already initialized prior to relocation, reinitialization after relocation is unnecessary. Signed-off-by: Ramon Fried Reviewed-by: Simon Glass --- v2: removed extra parenthesis drivers/serial/serial_msm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 8b585deeeb..a4279accb4 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -184,6 +184,10 @@ static int msm_serial_probe(struct udevice *dev) int ret; struct msm_serial_data *priv = dev_get_priv(dev); + /* No need to reinitialize the UART after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + ret = msm_uart_clk_init(dev); if (ret) return ret; From patchwork Wed May 16 09:13:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 914284 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jcHlC1RA"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40m83d0YwZz9s2k for ; Wed, 16 May 2018 19:17:49 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id CAE71C21E07; Wed, 16 May 2018 09:15:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0ABFCC21DB6; Wed, 16 May 2018 09:14:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 52FFDC21E42; Wed, 16 May 2018 09:14:23 +0000 (UTC) Received: from mail-wr0-f180.google.com (mail-wr0-f180.google.com [209.85.128.180]) by lists.denx.de (Postfix) with ESMTPS id CDCB6C21DD9 for ; Wed, 16 May 2018 09:14:15 +0000 (UTC) Received: by mail-wr0-f180.google.com with SMTP id 94-v6so76683wrf.5 for ; Wed, 16 May 2018 02:14:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0HoCywKkj51ggnv8IHG9kOjypRksC2fiRQ54YnsLnKw=; b=jcHlC1RAx9i0vyclKa75PHBLqZ4Ym21IfMTjvz22R7osFbxbucDYf4o7wTIq9u+nV/ 9qPmd2ZP42w8itqkicmq8FNZcKlXxIuubK73j2OSGhYCvyIHQWgK++ez3PUEZ94qBWmf wqbgtt0XSd57FwtS32dqYU3Yq0enh13eZspDb68t3ltpkVQcD2pBLLEauyyqWQabEYUe P13NItnQrb8N3g1IP0C3QYEZ7NJ9G9YOG2ro8IVn6L2dRjABeEDZABmplCFT/twwGHTB sNS5KtJmfYWopHFo9S0PUyY93RHQ1Hsqwj1qoOH05RZqt6JhG3/IoZ9nBayGcIFxw4S4 bX5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0HoCywKkj51ggnv8IHG9kOjypRksC2fiRQ54YnsLnKw=; b=HXzeqlWi45lR0c/rjCtLECf5sn2poaZ97p8CD2h1NJ4KRiWbQNO1af0/OeGmVlmDel GQmeb98LAK36ZP1plCSPJkgYXZbEsmfR7EsOeAzXVLRSH1U72NkTI35ggTGPEJBtXDia KWFn1zp/o76QI+hvegVb+9e7azYUasi2MPGwmNO5+m3LR+egQh+RvceyronG5fqMfFrA rbMZTZgGK3yAXA9Hm+a7G0SqDd7/3fyvi/n+LWCQ9pNsJpCQiFh3kiXCxNeizUj2FLYQ M7Ldp+09EvlRvco9FdYCAl+p4kgz6IBxNTbOH3yofiocFj++kJ/oNghBotR6/zrs+sKG 8/Gw== X-Gm-Message-State: ALKqPwd5/5TPVukLZ/x6diEPbdU8P3v9zBDrgP5TSmoBXlbjDXL4eeiX VBwxha6LuxK1YLkdbft6iJY= X-Google-Smtp-Source: AB8JxZocu3+S0r8CdMlMLRMt9Yb3J0A/BKNkg7ofaHlaiNR0YW+/IBqHR6X15MxRXeCteXDrRsJV8A== X-Received: by 2002:adf:c613:: with SMTP id n19-v6mr35844wrg.177.1526462055260; Wed, 16 May 2018 02:14:15 -0700 (PDT) Received: from localhost.localdomain ([141.226.166.38]) by smtp.gmail.com with ESMTPSA id h12-v6sm1920655wmc.7.2018.05.16.02.14.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 May 2018 02:14:14 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Wed, 16 May 2018 12:13:39 +0300 Message-Id: <20180516091342.7509-4-ramon.fried@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516091342.7509-1-ramon.fried@gmail.com> References: <20180516091342.7509-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 4/7] mach-snapdragon: Fix UART clock flow X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" UART clock enabling flow was wrong. Changed the flow according to downstream implementation in LK. Signed-off-by: Ramon Fried --- arch/arm/mach-snapdragon/clock-apq8016.c | 23 +++++++++++++------ arch/arm/mach-snapdragon/clock-apq8096.c | 4 ++-- arch/arm/mach-snapdragon/clock-snapdragon.c | 17 +++++++++++++- arch/arm/mach-snapdragon/clock-snapdragon.h | 9 ++++++-- .../include/mach/sysmap-apq8016.h | 1 + 5 files changed, 42 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c index 9c0cc1c22c..6e4a0ccb90 100644 --- a/arch/arm/mach-snapdragon/clock-apq8016.c +++ b/arch/arm/mach-snapdragon/clock-apq8016.c @@ -17,7 +17,6 @@ /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) -#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) static const struct bcr_regs sdc_regs[] = { { @@ -36,11 +35,17 @@ static const struct bcr_regs sdc_regs[] = { } }; -static struct gpll0_ctrl gpll0_ctrl = { +static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, - .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, + .vote_bit = BIT(0), +}; + +static struct vote_clk gcc_blsp1_ahb_clk = { + .cbcr_reg = BLSP1_AHB_CBCR, + .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, + .vote_bit = BIT(10), }; /* SDHCI */ @@ -55,7 +60,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) /* 800Mhz/div, gpll0 */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); return rate; @@ -72,12 +77,16 @@ static const struct bcr_regs uart2_regs = { /* UART: 115200 */ static int clk_init_uart(struct msm_clk_priv *priv) { - /* Enable iface clk */ - clk_enable_cbc(priv->base + BLSP1_AHB_CBCR); + /* Enable AHB clock */ + clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + /* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + + /* Vote for gpll0 clock */ + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + /* Enable core clk */ clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index 008649a4c6..628c38785b 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -27,7 +27,7 @@ static const struct bcr_regs sdc_regs = { .D = SDCC2_D, }; -static const struct gpll0_ctrl gpll0_ctrl = { +static const struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -41,7 +41,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); return rate; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index f738f57043..85526186c6 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -30,7 +30,7 @@ void clk_enable_cbc(phys_addr_t cbcr) ; } -void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0) +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) { if (readl(base + gpll0->status) & gpll0->status_bit) return; /* clock already enabled */ @@ -41,6 +41,21 @@ void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0) ; } +#define BRANCH_ON_VAL (0) +#define BRANCH_NOC_FSM_ON_VAL BIT(29) +#define BRANCH_CHECK_MASK GENMASK(31, 28) + +void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) +{ + u32 val; + + setbits_le32(base + vclk->ena_vote, vclk->vote_bit); + do { + val = readl(base + vclk->cbcr_reg); + val &= BRANCH_CHECK_MASK; + } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); +} + #define APPS_CMD_RGCR_UPDATE BIT(0) /* Update clock command via CMD_RGCR */ diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 2cff4f8a06..3ae21099c2 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -11,13 +11,18 @@ #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_MASK (7 << 8) -struct gpll0_ctrl { +struct pll_vote_clk { uintptr_t status; int status_bit; uintptr_t ena_vote; int vote_bit; }; +struct vote_clk { + uintptr_t cbcr_reg; + uintptr_t ena_vote; + int vote_bit; +}; struct bcr_regs { uintptr_t cfg_rcgr; uintptr_t cmd_rcgr; @@ -30,7 +35,7 @@ struct msm_clk_priv { phys_addr_t base; }; -void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0); +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h index ae784387fa..520e2e6bd7 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -13,6 +13,7 @@ /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) #define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) #define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) From patchwork Wed May 16 09:13:40 2018 Content-Type: text/plain; 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Wed, 16 May 2018 02:14:16 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Wed, 16 May 2018 12:13:40 +0300 Message-Id: <20180516091342.7509-5-ramon.fried@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516091342.7509-1-ramon.fried@gmail.com> References: <20180516091342.7509-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 5/7] mach-snapdragon: Introduce pinctrl driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets. Currently, supporting only 8016, but implementation is generic and 8096 can be added easily. Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet). Signed-off-by: Ramon Fried Reviewed-by: Simon Glass --- v2: * restructred the code to be more generic * Reduced pin table size by snprintf on runtime as suggested by Simon. arch/arm/mach-snapdragon/Makefile | 2 + arch/arm/mach-snapdragon/pinctrl-apq8016.c | 62 +++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 128 ++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 29 ++++ configs/dragonboard410c_defconfig | 5 + .../dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 +++ 6 files changed, 248 insertions(+) create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 1c23dc52cf..1d35fea912 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -6,4 +6,6 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o obj-y += clock-snapdragon.o diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/arch/arm/mach-snapdragon/pinctrl-apq8016.c new file mode 100644 index 0000000000..602af1b1d3 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-apq8016.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8016 pinctrl + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include "pinctrl-snapdragon.h" +#include + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN]; +static const char * const msm_pinctrl_pins[] = { + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", + "QDSD_CLK", + "QDSD_CMD", + "QDSD_DATA0", + "QDSD_DATA1", + "QDSD_DATA2", + "QDSD_DATA3", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp1_uart", 2}, +}; + +static const char *apq8016_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *apq8016_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 130) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 130]; + } +} + +static unsigned int apq8016_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data apq8016_data = { + .pin_count = 140, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = apq8016_get_function_name, + .get_function_mux = apq8016_get_function_mux, + .get_pin_name = apq8016_get_pin_name, +}; + diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c new file mode 100644 index 0000000000..9b7cf59a67 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TLMM driver for Qualcomm APQ8016, APQ8096 + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include +#include +#include +#include +#include +#include "pinctrl-snapdragon.h" + +struct msm_pinctrl_priv { + phys_addr_t base; + struct msm_pinctrl_data *data; +}; + +#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_ENABLE BIT(9) + +static const struct pinconf_param msm_conf_params[] = { + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, +}; + +static int msm_get_functions_count(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->functions_count; +} + +static int msm_get_pins_count(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->pin_count; +} + +static const char *msm_get_function_name(struct udevice *dev, + unsigned int selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->get_function_name(dev, selector); +} + +static int msm_pinctrl_probe(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + priv->base = devfdt_get_addr(dev); + priv->data = (struct msm_pinctrl_data *)dev->driver_data; + + return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; +} + +static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->get_pin_name(dev, selector); +} + +static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, + unsigned int func_selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE, + priv->data->get_function_mux(func_selector) << 2); + return 0; +} + +static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_DRV_STRENGTH_MASK, argument << 6); + break; + case PIN_CONFIG_BIAS_DISABLE: + clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK); + break; + default: + return 0; + } + + return 0; +} + +static struct pinctrl_ops msm_pinctrl_ops = { + .get_pins_count = msm_get_pins_count, + .get_pin_name = msm_get_pin_name, + .set_state = pinctrl_generic_set_state, + .pinmux_set = msm_pinmux_set, + .pinconf_num_params = ARRAY_SIZE(msm_conf_params), + .pinconf_params = msm_conf_params, + .pinconf_set = msm_pinconf_set, + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data }, + { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, + { } +}; + +U_BOOT_DRIVER(pinctrl_snapdraon) = { + .name = "pinctrl_msm", + .id = UCLASS_PINCTRL, + .of_match = msm_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv), + .ops = &msm_pinctrl_ops, + .probe = msm_pinctrl_probe, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h new file mode 100644 index 0000000000..6fd9971f17 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm Pin control + * + * (C) Copyright 2018 Ramon Fried + * + */ +#ifndef _PINCTRL_SNAPDRAGON_H +#define _PINCTRL_SNAPDRAGON_H + +#include + +struct msm_pinctrl_data { + int pin_count; + int functions_count; + const char *(*get_function_name)(struct udevice *dev, + unsigned int selector); + unsigned int (*get_function_mux)(unsigned int selector); + const char *(*get_pin_name)(struct udevice *dev, + unsigned int selector); +}; + +struct pinctrl_function { + const char *name; + int val; +}; + +extern struct msm_pinctrl_data apq8016_data; + +#endif diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index e6114db2ce..4b3de64dd5 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -45,3 +45,8 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_FULL=y +CONFIG_PINCTRL_GENERIC=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h new file mode 100644 index 0000000000..615affb6f2 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for Qualcomm Snapdragon pinctrl bindings. + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H +#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H + +/* GPIO Drive Strength */ +#define DRIVE_STRENGTH_2MA 0 +#define DRIVE_STRENGTH_4MA 1 +#define DRIVE_STRENGTH_6MA 2 +#define DRIVE_STRENGTH_8MA 3 +#define DRIVE_STRENGTH_10MA 4 +#define DRIVE_STRENGTH_12MA 5 +#define DRIVE_STRENGTH_14MA 6 +#define DRIVE_STRENGTH_16MA 7 + +#endif From patchwork Wed May 16 09:13:41 2018 Content-Type: text/plain; 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Wed, 16 May 2018 02:14:17 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Wed, 16 May 2018 12:13:41 +0300 Message-Id: <20180516091342.7509-6-ramon.fried@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516091342.7509-1-ramon.fried@gmail.com> References: <20180516091342.7509-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 6/7] db410: added pinctrl node and serial bindings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Added TLMM pinctrl node for pin muxing & config. Additionally, added a serial node for uart. Signed-off-by: Ramon Fried --- arch/arm/dts/dragonboard410c.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index d9d5831f4f..182a865b0a 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "skeleton64.dtsi" +#include / { model = "Qualcomm Technologies, Inc. Dragonboard 410c"; @@ -38,6 +39,17 @@ ranges = <0x0 0x0 0x0 0xffffffff>; compatible = "simple-bus"; + pinctrl: qcom,tlmm@1000000 { + compatible = "qcom,tlmm-apq8016"; + reg = <0x1000000 0x400000>; + + blsp1_uart: uart { + function = "blsp1_uart"; + pins = "GPIO_4", "GPIO_5"; + drive-strength = ; + bias-disable; + }; + }; clkc: qcom,gcc@1800000 { compatible = "qcom,gcc-apq8016"; reg = <0x1800000 0x80000>; @@ -49,6 +61,8 @@ compatible = "qcom,msm-uartdm-v1.4"; reg = <0x78b0000 0x200>; clock = <&clkc 4>; + pinctrl-names = "uart"; + pinctrl-0 = <&blsp1_uart>; }; soc_gpios: pinctrl@1000000 { From patchwork Wed May 16 09:13:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 914287 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="prckc7XG"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40m84H6k4dz9s2L for ; Wed, 16 May 2018 19:18:23 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 94DCEC21E50; Wed, 16 May 2018 09:17:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DE5B2C21E0D; Wed, 16 May 2018 09:14:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 50741C21E35; Wed, 16 May 2018 09:14:35 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id 4206CC21E2C for ; Wed, 16 May 2018 09:14:20 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id g21-v6so67002wrb.8 for ; Wed, 16 May 2018 02:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ogd3ImVpnZjC/hIW47AwDRcrlaysPTA9SiKS6GKFQNw=; b=prckc7XGSLXl9bffoTFllmvpnTRCB6UPBHTLBfvVAfzXnc+/ykGnW/tTc1qdZ663ti g0YNr7nTdmgIUFn0f9Zm42mc+wbj6RdUFqZM2fxQ/3qSUaGufmQLdQfa1nwLqexsqmtc 7moI4Znf7TDxo1GE2Xk65099V8+lyT5Xo61az6LDqKDQA6xGIWV+koW3q3Zew1xZfa6a WxtnVnlraXHen8cGof+gbHq7UY6m8yPFj9YibIt6POusFgjeHYvxpnOnKNtGHsIlfElL miW/cXX1hQKYG4FDYPS2B3p7IALdzMcwrADYz/qNa85dLCtdHyEhQ+veMitCyyQovraL cRVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ogd3ImVpnZjC/hIW47AwDRcrlaysPTA9SiKS6GKFQNw=; b=L9OzQJmv0q35sP0bm6uKM4TaCIpyxU99fdj6plNmY87nDQRHeB2Ojq2P8qVzyybqfw f4WKWY06iHqdhsvC6BLOYy9Nz/QM6CU/BUBmqReJosn8iiu2EJ36zwf5P6zFzVweUiEq vy+676YgxPh3G87p52tYBf5oTgO1adQ9EpDUPQEDHGjDm8hL1/uUFAmWm6pReMaEhpEC 7Tr+k9AZGIXJ7CSUBycsdiARwEdqhpecSjBh0bus0eM7lsuwLiCxocSM+/gVS4l7x9fT ceC+4fh+9ImN6Fd9ostzUe57E0LzBpU55N6zuFzf+tdICiv7ehffBvbBXRYg1zGPbhlt a6tg== X-Gm-Message-State: ALKqPwdGyi828Q8rp8RyRpABwDrIdFunosI9TBX6Hq4lLX70BS5CMTLz Vqxhn7mtcY0q6KoxJF6hGhI= X-Google-Smtp-Source: AB8JxZrE70/DeeCkmZIzQe822DFHqZp78F7DxQi36xMH1c99oX5RdbOa9AjevBK+l156jGuQ0i0Jew== X-Received: by 2002:adf:8672:: with SMTP id 47-v6mr74112wrw.102.1526462059946; Wed, 16 May 2018 02:14:19 -0700 (PDT) Received: from localhost.localdomain ([141.226.166.38]) by smtp.gmail.com with ESMTPSA id h12-v6sm1920655wmc.7.2018.05.16.02.14.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 May 2018 02:14:19 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Wed, 16 May 2018 12:13:42 +0300 Message-Id: <20180516091342.7509-7-ramon.fried@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516091342.7509-1-ramon.fried@gmail.com> References: <20180516091342.7509-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 7/7] serial: serial_msm: added pinmux & config X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Serial port configuration was missing from previous implementation. It only worked because it was preconfigured by LK. This patch configures the uart for 115200 8N1. It also configures the pin mux for uart pins using DT bindings. Signed-off-by: Ramon Fried --- drivers/serial/serial_msm.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index a4279accb4..c462394dbd 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -16,6 +16,7 @@ #include #include #include +#include /* Serial registers - this driver works in uartdm mode*/ @@ -25,6 +26,9 @@ #define UARTDM_RXFS 0x50 /* RX channel status register */ #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */ #define UARTDM_RXFS_BUF_MASK 0x7 +#define UARTDM_MR1 0x00 +#define UARTDM_MR2 0x04 +#define UARTDM_CSR 0xA0 #define UARTDM_SR 0xA4 /* Status register */ #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */ @@ -45,6 +49,10 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 DECLARE_GLOBAL_DATA_PTR; @@ -179,6 +187,14 @@ static int msm_uart_clk_init(struct udevice *dev) return 0; } +static void uart_dm_init(struct msm_serial_data *priv) +{ + writel(UART_DM_CLK_RX_TX_BIT_RATE, priv->base + UARTDM_CSR); + writel(0x0, priv->base + UARTDM_MR1); + writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); + writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); + writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); +} static int msm_serial_probe(struct udevice *dev) { int ret; @@ -192,12 +208,8 @@ static int msm_serial_probe(struct udevice *dev) if (ret) return ret; - if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) - writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); - - writel(0, priv->base + UARTDM_IMR); - writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR); - msm_serial_fetch(dev); + pinctrl_select_state(dev, "uart"); + uart_dm_init(priv); return 0; }