From patchwork Fri May 11 08:20:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Yves MORDRET X-Patchwork-Id: 911846 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40j32d48hSz9s02 for ; Fri, 11 May 2018 18:21:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752811AbeEKIUx (ORCPT ); Fri, 11 May 2018 04:20:53 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:23750 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752733AbeEKIUu (ORCPT ); Fri, 11 May 2018 04:20:50 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w4B8Itk6022670; Fri, 11 May 2018 10:20:26 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hucjkf2wj-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 11 May 2018 10:20:26 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0C57D34; Fri, 11 May 2018 08:20:26 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D9B622A72; Fri, 11 May 2018 08:20:25 +0000 (GMT) Received: from localhost (10.75.127.48) by SFHDAG5NODE2.st.com (10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 11 May 2018 10:20:25 +0200 From: Pierre-Yves MORDRET To: Wolfram Sang , Maxime Coquelin , Alexandre Torgue , Colin Ian King , , , CC: Pierre-Yves MORDRET Subject: [PATCH] i2c: i2c-stm32f7: fix documentation typo Date: Fri, 11 May 2018 10:20:25 +0200 Message-ID: <1526026825-2996-1-git-send-email-pierre-yves.mordret@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG4NODE1.st.com (10.75.127.10) To SFHDAG5NODE2.st.com (10.75.127.14) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-05-11_03:, , signatures=0 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Some data structure members were either misspelled or missing. Fixes: aeb068c572 ("i2c: i2c-stm32f7: add driver") Fixes: 380b8a85e7 ("i2c: i2c-stm32f7: Add initial SMBus protocols support") Signed-off-by: Pierre-Yves MORDRET --- Version history: v1: * Initial --- --- drivers/i2c/busses/i2c-stm32f7.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c index 0f87449..62d023e 100644 --- a/drivers/i2c/busses/i2c-stm32f7.c +++ b/drivers/i2c/busses/i2c-stm32f7.c @@ -211,11 +211,12 @@ struct stm32f7_i2c_setup { /** * struct stm32f7_i2c_timings - private I2C output parameters - * @prec: Prescaler value + * @node: List entry + * @presc: Prescaler value * @scldel: Data setup time * @sdadel: Data hold time * @sclh: SCL high period (master mode) - * @sclh: SCL low period (master mode) + * @scll: SCL low period (master mode) */ struct stm32f7_i2c_timings { struct list_head node; @@ -237,7 +238,7 @@ struct stm32f7_i2c_timings { * @size: type of SMBus protocol * @read_write: direction of SMBus protocol * SMBus block read and SMBus block write - block read process call protocols - * @smbus_buff: buffer to be used for SMBus protocol transfer. It will + * @smbus_buf: buffer to be used for SMBus protocol transfer. It will * contain a maximum of 32 bytes of data + byte command + byte count + PEC * This buffer has to be 32-bit aligned to be compliant with memory address * register in DMA mode.