From patchwork Tue May 8 16:26:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 910333 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sznx9FUp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40gQ243Bvfz9s1w for ; Wed, 9 May 2018 02:30:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932773AbeEHQ3I (ORCPT ); Tue, 8 May 2018 12:29:08 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:33242 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932735AbeEHQ3F (ORCPT ); Tue, 8 May 2018 12:29:05 -0400 Received: by mail-pg0-f68.google.com with SMTP id i194-v6so21400064pgd.0; Tue, 08 May 2018 09:29:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gtT0S4rPPQ2GzsQYX0FG70PZ4AdQv58mNGIcavWwhPg=; b=sznx9FUpVMNCglGSMQp0xwXXH3cBSeEAD2BEAPl4Ypm0xd0gwcfQXjhQf841X/0Qgp HIIfrRsUUwQHJQG1ZeGPzgf/1bFfrl+nr/jC2OHFHB45UURWFGx3N2HSZA8dB/bsEXxA fb9zloTwGHjwnySKa8yB8M1/fzAwvbhInZ13WHpN8VyJl+sL33FXxMDwlgVk9s2ZYpqm 947VnUZN/vMxXzWkf6WYfYSFHIu0jur45qs/x07w2EvOU2l1/WrGYmemh5irp8c7osST tgChjePVhIG9+1M6mlrBkYzMt1StWX04Oq88JKAX0ELRrJ6dSQ27S4QMCRCLFN8sz4V0 wcrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gtT0S4rPPQ2GzsQYX0FG70PZ4AdQv58mNGIcavWwhPg=; b=cKbdNY5oL4p7qgenFDDc60X238NgMROE7FS/hLk/aCozRg0NCREntgZoId2rPfwfPb 8udPv+juSjzkORd8ZM9cFivNerPR+htFgyEXLRRvXUBHhkKFHCZU32/+C3HRavbunspv 7KZFZutA8Gc+kyYh2TDGVPHJiBGQ3tqDZBbgWoRcjfUBDC6WUoA5j6jBfehGYgEYgZbj g0lytL38/2A2sq+sN5Brp0V+hnlhYsSSvbHyD6x5u5pE11WwuhyXzExuWlWQHizTl6nn vdTJATmpJwExDdO8LrheW2Mna9mNI1y4+kZhEuesvRwrjXz4fnPHcSEuFtKhWbm+ISDG yLqw== X-Gm-Message-State: ALQs6tCbg/ktsm4fQBnrEPYsXwxDeomUc5bprsJX24l3RiwIL7dmhWxP V2KkIvvorhW+6iQZJPhLyfY= X-Google-Smtp-Source: AB8JxZqYsYg4rd+LQ4n+tCCocZGR1KQBoF1hwOBHrG3HbcFp0xy1eYpH6ycB7/NuNhELlhw6G7nMNA== X-Received: by 2002:a63:7c15:: with SMTP id x21-v6mr33117851pgc.209.1525796945234; Tue, 08 May 2018 09:29:05 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.130]) by smtp.gmail.com with ESMTPSA id o10-v6sm42083664pgc.80.2018.05.08.09.28.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 May 2018 09:29:04 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] pinctrl: tegra20: Provide CDEV1/2 clock muxes Date: Tue, 8 May 2018 19:26:04 +0300 Message-Id: <20180508162607.3500-3-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508162607.3500-1-digetx@gmail.com> References: <20180508162607.3500-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Tested-by: Marc Dietrich Acked-by: Peter De Schrijver Acked-by: Thierry Reding --- Changelog: v3: - No change. v2: - See changelog of "Restore ULPI USB on Tegra20" v2 series. drivers/pinctrl/tegra/pinctrl-tegra.c | 11 --------- drivers/pinctrl/tegra/pinctrl-tegra.h | 11 +++++++++ drivers/pinctrl/tegra/pinctrl-tegra20.c | 30 ++++++++++++++++++++++++- 3 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 72c718e66ebb..49c7c1499bc3 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -33,17 +33,6 @@ #include "../pinctrl-utils.h" #include "pinctrl-tegra.h" -struct tegra_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - - const struct tegra_pinctrl_soc_data *soc; - const char **group_pins; - - int nbanks; - void __iomem **regs; -}; - static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) { return readl(pmx->regs[bank] + reg); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 33b17cb1471e..aa33c20766c4 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -16,6 +16,17 @@ #ifndef __PINMUX_TEGRA_H__ #define __PINMUX_TEGRA_H__ +struct tegra_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + + const struct tegra_pinctrl_soc_data *soc; + const char **group_pins; + + int nbanks; + void __iomem **regs; +}; + enum tegra_pinconf_param { /* argument: tegra_pinconf_pull */ TEGRA_PINCONF_PARAM_PULL, diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index 7e38ee9bae78..b6dd939d32cc 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -19,6 +19,7 @@ * more details. */ +#include #include #include #include @@ -2231,9 +2232,36 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = { .drvtype_in_mux = false, }; +static const char *cdev1_parents[] = { + "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio", +}; + +static const char *cdev2_parents[] = { + "dev2_osc_div", "hclk", "pclk", "pll_p_out4", +}; + +static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev) +{ + struct tegra_pmx *pmx = platform_get_drvdata(pdev); + + clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0, + pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL); + + clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0, + pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL); +} + static int tegra20_pinctrl_probe(struct platform_device *pdev) { - return tegra_pinctrl_probe(pdev, &tegra20_pinctrl); + int err; + + err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl); + if (err) + return err; + + tegra20_pinctrl_register_clock_muxes(pdev); + + return 0; } static const struct of_device_id tegra20_pinctrl_of_match[] = {