From patchwork Tue May 8 16:26:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 910335 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="a2KF0OAL"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40gQ2d6jjPz9s27 for ; Wed, 9 May 2018 02:30:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755467AbeEHQ26 (ORCPT ); Tue, 8 May 2018 12:28:58 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:38827 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755462AbeEHQ25 (ORCPT ); Tue, 8 May 2018 12:28:57 -0400 Received: by mail-pf0-f193.google.com with SMTP id o76so24216901pfi.5; Tue, 08 May 2018 09:28:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Hen+wjG6wbWxgtH2nfl8nVcZ7pTN6V8XvKMD6k7Sj8U=; b=a2KF0OALddpQ2vWHYHV5Qoq8BhnWVs/UFlOsRRtLB73IqMOrRnnsyOgrH5lC38ncI2 xoK5SrutAVHOfQYZK8TIUQz3Nzq1IA0A+csvldiquS8fqrEQVfc9bReTFiuBpiv1bfWz HGicE+IJ0uzV82IY9N8C6LfLr5a94oVcbbksHgvhis8BCum2+bcSpoqo2ZdGyb+Sioh5 PlJ33wIC26xSu/98dCj++H/hSRRKT5HIjMTlJlQZiHVZqUBsSq+Bkt5Jamh4GPrbY66V kmTAezb52mfMDxxFoMuIIhNsxg+Bs0MhxB8Tr5wvSMAJq13TpZ+5jcrko6YtKnlatMnx p0cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hen+wjG6wbWxgtH2nfl8nVcZ7pTN6V8XvKMD6k7Sj8U=; b=szBQdR9QzJgEz5hNkEcR9yidTyKuFqMuU2In9Q7CaEE7R8M5Ovp2tyZhkN/jHQmivD gAEpD7ccM+yXaO/doMd7gCsn82ffJsC025SagD4nJtfVP8/wweBOlwyabIeT4ZsKxEyY e06m9bIjhW1uy9VyULLXxjCWml+2SlrUFU91dRtMWsiCcQ4yoJ8cI8GDZt4QEZkylIr8 9dSR+AvpjdvLKZGwgRAoCN3n6UJYhBFbkAJD3O/lZ6U4IR2wNAEEK+PfL01RyHhDQjTq dB2F2sB9V5NF4k6SwohDwEBFhpu8NxrQepn4S+visfj34X4mSMF39KiFO6Ok1NdDOxNi Fr/w== X-Gm-Message-State: ALQs6tCqEv0zqwZVQtWOO4cSSJnAr5k9Y6nC4AMNX5fM59+z8n+W6Jzp vJVeWs5OLbL/8BtmXNLYznQ= X-Google-Smtp-Source: AB8JxZpHHOu6DZaAugfP8pLCJ9uySzC+baM39dD2VPdN9gcZUYXqPyM3DOH/cpWMBC2NA7wCckZX+A== X-Received: by 2002:a63:7543:: with SMTP id f3-v6mr29682301pgn.256.1525796936521; Tue, 08 May 2018 09:28:56 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.130]) by smtp.gmail.com with ESMTPSA id o10-v6sm42083664pgc.80.2018.05.08.09.28.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 May 2018 09:28:55 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers Date: Tue, 8 May 2018 19:26:03 +0300 Message-Id: <20180508162607.3500-2-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508162607.3500-1-digetx@gmail.com> References: <20180508162607.3500-1-digetx@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as a parent. Add these dividers in order to be able to provide that parent option. Signed-off-by: Dmitry Osipenko Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Tested-by: Marc Dietrich Acked-by: Peter De Schrijver Acked-by: Stephen Boyd --- drivers/clk/tegra/clk-tegra20.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 0ee56dd04cec..ad5a7b5e3a39 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -26,6 +26,8 @@ #include "clk.h" #include "clk-id.h" +#define MISC_CLK_ENB 0x48 + #define OSC_CTRL 0x50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30) #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) @@ -831,6 +833,18 @@ static void __init tegra20_periph_clk_init(void) periph_clk_enb_refcnt); clks[TEGRA20_CLK_PEX] = clk; + /* dev1 OSC divider */ + clk_register_divider(NULL, "dev1_osc_div", "clk_m", + 0, clk_base + MISC_CLK_ENB, 22, 2, + CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, + NULL); + + /* dev2 OSC divider */ + clk_register_divider(NULL, "dev2_osc_div", "clk_m", + 0, clk_base + MISC_CLK_ENB, 20, 2, + CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, + NULL); + /* cdev1 */ clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000); clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, From patchwork Tue May 8 16:26:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 910331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rol6tILM"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40gQ1x6pgqz9s1w for ; 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Tue, 08 May 2018 09:29:14 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] clk: tegra20: Correct parents of CDEV1/2 clocks Date: Tue, 8 May 2018 19:26:05 +0300 Message-Id: <20180508162607.3500-4-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508162607.3500-1-digetx@gmail.com> References: <20180508162607.3500-1-digetx@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Parents of CDEV1/2 clocks are determined by muxing of the corresponding pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the corresponding muxes to fix the parents. Signed-off-by: Dmitry Osipenko Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Tested-by: Marc Dietrich Acked-by: Peter De Schrijver Acked-by: Stephen Boyd --- drivers/clk/tegra/clk-tegra20.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index ad5a7b5e3a39..636500a98561 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -846,14 +846,12 @@ static void __init tegra20_periph_clk_init(void) NULL); /* cdev1 */ - clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000); - clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, + clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, clk_base, 0, 94, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV1] = clk; /* cdev2 */ - clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000); - clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, + clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, clk_base, 0, 93, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV2] = clk; From patchwork Tue May 8 16:26:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 910328 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HMot7ua5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40gQ1t2jfxz9s1w for ; Wed, 9 May 2018 02:29:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933002AbeEHQ30 (ORCPT ); Tue, 8 May 2018 12:29:26 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:35059 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932735AbeEHQ3X (ORCPT ); Tue, 8 May 2018 12:29:23 -0400 Received: by mail-pf0-f195.google.com with SMTP id x9so5057199pfm.2; Tue, 08 May 2018 09:29:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ap0KKUnLWhoye93HkP5YQVCwi7aaYg/A0vXrB1Y5DnQ=; b=HMot7ua5fb7H6VdX5S2UQrAgTfRSbhw3jpBxn2m08yK6ZuFskn6I5/iQfO0ZBGFprf 5S7HizgpAzTd9w665zHoMWhlTgEVphLeuXvOVb6vkoekF5Mu/fO9OJFDKlU6ULoKhfkX 6wskaYJK2AtYUAiU5tjDDpBCi2smx6mqxbDH7vxyeT1D5upyMkKO8Jrm7/WZNwIwimJ6 2WeC2aGsxnhgxiHeLVt4XlpoZ70jLgwk/bQzh2vY0X1YGAZMEgesCSE80tqkFX221yno 556XHiWZCpltCxw+Q+2Mbwbiruwnu+LsoVd80uEBmwL4UK8vrY+2tZjmy+qgteqDXoTL TpHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ap0KKUnLWhoye93HkP5YQVCwi7aaYg/A0vXrB1Y5DnQ=; b=uknftAbAq4KYS7r3hxBF5rv3HyWSJSXPoicDV8y2jBqpK4QjxZ0YY6HX9YHXNkbJcb gA7bSwE/ppVrtxgYxMZ/YNHMmQ9djxXhk3gycvnPvD6jszr/Ot5S8DxqdpF8rDX0yRS+ upv7EPB6DFIyJKR/mXzsSCGajEFU8ZrvRVUV2Z1JmmSkm6X3wGHUDAB1QWILbniox3z4 Wu5xSvlTzIbs6yJwym+2hiJm/ZLsuipFqGdV7HnKx6dyjIEGpcQxElvFZ6VyAyEbZxKq JuxYVYNJFC7O/JmZV+5yhxxV1T1s0JadCM+0oY8kQN+2Hbnb4j32cYSJU4NzvKiLJT3L QLtg== X-Gm-Message-State: ALQs6tD6ASCWKv5K5/dl4Tw2Ijx6duSecUtS1gpze5/TXeqfZ5oXt6q0 9SwMGHG+27ozH4n1Hhk8dpA= X-Google-Smtp-Source: AB8JxZqqMZJON+JPv+b48RixPuGBPaWsPM4Sssx4/ZXSlBexYrgpslr5nqr839WTiJHuG0iJ+C5Syw== X-Received: by 2002:a65:51c4:: with SMTP id i4-v6mr27795093pgq.190.1525796963253; Tue, 08 May 2018 09:29:23 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.130]) by smtp.gmail.com with ESMTPSA id o10-v6sm42083664pgc.80.2018.05.08.09.29.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 May 2018 09:29:22 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 Date: Tue, 8 May 2018 19:26:06 +0300 Message-Id: <20180508162607.3500-5-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508162607.3500-1-digetx@gmail.com> References: <20180508162607.3500-1-digetx@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user may expect parent clock to be enabled by the child, so let's return -EPROBE_DEFER till parent clock appears. Signed-off-by: Dmitry Osipenko Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra114.c | 2 +- drivers/clk/tegra/clk-tegra124.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 32 +++++++++++++++++++++++++++++++- drivers/clk/tegra/clk-tegra210.c | 2 +- drivers/clk/tegra/clk-tegra30.c | 2 +- drivers/clk/tegra/clk.c | 5 +++-- drivers/clk/tegra/clk.h | 2 +- 7 files changed, 39 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 5d5a22d529f5..1824f014202b 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1367,7 +1367,7 @@ static void __init tegra114_clock_init(struct device_node *np) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks, &pll_x_params); - tegra_add_of_provider(np); + tegra_add_of_provider(np, of_clk_src_onecell_get); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); tegra_clk_apply_init_table = tegra114_clock_apply_init_table; diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 50088e976611..0c69c7970950 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1479,7 +1479,7 @@ static void __init tegra124_132_clock_init_post(struct device_node *np) &pll_x_params); tegra_init_special_resets(1, tegra124_reset_assert, tegra124_reset_deassert); - tegra_add_of_provider(np); + tegra_add_of_provider(np, of_clk_src_onecell_get); clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, &emc_lock); diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 636500a98561..cc857d4d4a86 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1089,6 +1089,36 @@ static const struct of_device_id pmc_match[] __initconst = { { }, }; +static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, + void *data) +{ + struct clk_hw *parent_hw; + struct clk_hw *hw; + struct clk *clk; + + clk = of_clk_src_onecell_get(clkspec, data); + if (IS_ERR(clk)) + return clk; + + /* + * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent + * clock is created by the pinctrl driver. It is possible for clk user + * to request these clocks before pinctrl driver got probed and hence + * user will get an orphaned clock. That might be undesirable because + * user may expect parent clock to be enabled by the child. + */ + if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || + clkspec->args[0] == TEGRA20_CLK_CDEV2) { + hw = __clk_get_hw(clk); + + parent_hw = clk_hw_get_parent(hw); + if (!parent_hw) + return ERR_PTR(-EPROBE_DEFER); + } + + return clk; +} + static void __init tegra20_clock_init(struct device_node *np) { struct device_node *node; @@ -1127,7 +1157,7 @@ static void __init tegra20_clock_init(struct device_node *np) tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); - tegra_add_of_provider(np); + tegra_add_of_provider(np, tegra20_clk_src_onecell_get); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); tegra_clk_apply_init_table = tegra20_clock_apply_init_table; diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 9fb5d51ccce4..5435d01c636a 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3567,7 +3567,7 @@ static void __init tegra210_clock_init(struct device_node *np) tegra_init_special_resets(2, tegra210_reset_assert, tegra210_reset_deassert); - tegra_add_of_provider(np); + tegra_add_of_provider(np, of_clk_src_onecell_get); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); tegra210_mbist_clk_init(); diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index b316dfb6f6c7..acfe661b2ae7 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1349,7 +1349,7 @@ static void __init tegra30_clock_init(struct device_node *np) tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX); - tegra_add_of_provider(np); + tegra_add_of_provider(np, of_clk_src_onecell_get); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); tegra_clk_apply_init_table = tegra30_clock_apply_init_table; diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index ba923f0d5953..593d76a114f9 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -298,7 +298,8 @@ static struct reset_controller_dev rst_ctlr = { .of_reset_n_cells = 1, }; -void __init tegra_add_of_provider(struct device_node *np) +void __init tegra_add_of_provider(struct device_node *np, + void *clk_src_onecell_get) { int i; @@ -314,7 +315,7 @@ void __init tegra_add_of_provider(struct device_node *np) clk_data.clks = clks; clk_data.clk_num = clk_num; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + of_clk_add_provider(np, clk_src_onecell_get, &clk_data); rst_ctlr.of_node = np; rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset; diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index ba7e20e6a82b..e1f88463b600 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -763,7 +763,7 @@ struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); -void tegra_add_of_provider(struct device_node *np); +void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get); void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); void tegra_audio_clk_init(void __iomem *clk_base, From patchwork Tue May 8 16:26:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 910326 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 08 May 2018 09:29:32 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.130]) by smtp.gmail.com with ESMTPSA id o10-v6sm42083664pgc.80.2018.05.08.09.29.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 May 2018 09:29:31 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20" Date: Tue, 8 May 2018 19:26:07 +0300 Message-Id: <20180508162607.3500-6-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508162607.3500-1-digetx@gmail.com> References: <20180508162607.3500-1-digetx@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Commit 4c9a27a6c66d ("ARM: tegra: Fix ULPI regression on Tegra20") changed "ulpi-link" clock from CDEV2 to PLL_P_OUT4. Turned out that PLL_P_OUT4 is the parent of CDEV2 clock and original clock setup of "ulpi-link" was correct. The reverted patch was fixing USB for one board and broke the other, now Tegra's clk driver correctly sets parent for the CDEV2 clock and hence patch could be reverted safely, restoring USB for all of the boards. Signed-off-by: Dmitry Osipenko Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Tested-by: Marc Dietrich --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 0a7136462a1a..983dd5c14794 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -741,7 +741,7 @@ phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT4>; + <&tegra_car TEGRA20_CLK_CDEV2>; clock-names = "reg", "pll_u", "ulpi-link"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads";