From patchwork Mon May 7 09:18:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 909621 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="jhPwcWgI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40fcWF2V3sz9s27 for ; Mon, 7 May 2018 19:19:05 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1C57AC2207A; Mon, 7 May 2018 09:19:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,RCVD_IN_SORBS_WEB,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D2D96C2207A; Mon, 7 May 2018 09:18:58 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 473E4C22061; Mon, 7 May 2018 09:18:58 +0000 (UTC) Received: from mail-pg0-f66.google.com (mail-pg0-f66.google.com [74.125.83.66]) by lists.denx.de (Postfix) with ESMTPS id A1D80C2205C for ; Mon, 7 May 2018 09:18:57 +0000 (UTC) Received: by mail-pg0-f66.google.com with SMTP id 82-v6so19779346pge.11 for ; Mon, 07 May 2018 02:18:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id; bh=4iibz0b9qsWVDmfi+NHg1G/KP0r3O9useEvdxdgPyR0=; b=jhPwcWgIsn8lKb4Frph5t5Ctt5a3Je9CP8K95dcxeIeuWwM0R52iFJ2AZdAp+uhl3a zSTxQYavU3MdUWNEl3dvQzHD7qXUFUJLzq0pjNEyaj2tSrhYW7iiSrKdcoyvbrqnoMW6 Kp85sxygajsN1bc22PLMsS6kr1jr5zdLen9Vg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=4iibz0b9qsWVDmfi+NHg1G/KP0r3O9useEvdxdgPyR0=; b=aijGMapiY4psvYs3krOp2PyrXLc0hi7qKlweE8ybtamOLqJCVbvs4pa9jR6GnfDn+2 r+V9Sq4h5wPUThWYnCBQ7Y09PZB3FX0TwVxsBhU2BifFjri475qzm+a1JFYYo4IuirUH e3hzNCVcj/8AJVx5mamxAxT289P7NBJD3F5jYbkWgJjH9j9mfzsW6PLzHZT7knx0Fz7U GzbphB6f0gBzxXJj588NFaqAAdmdOrkubv5OevRdDHmtDLv5bdznoKT5OKQq0w89djdl EHESuQ83pqVtcXJwkquLwBFIvvqn1vSHbjmZe74zhhZnks9zT8ogNivHAy1oTDS10tw3 ciGw== X-Gm-Message-State: ALQs6tC7v4BqchCgfh9vOgmVRFDDJKJc1OSwp776UQ5hTdFGwStZ00Ga Ff01R1YZ1J/2HCQh/npn1JSNGQ== X-Google-Smtp-Source: AB8JxZpogieIM7VMg0q6iLOIYdA+v+S7n2Ae8k55rGew7awIj5Ojhh9NZ1MoU11t1wDCr4FAKnNT1Q== X-Received: by 2002:a65:4e86:: with SMTP id b6-v6mr28826508pgs.392.1525684736252; Mon, 07 May 2018 02:18:56 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.172]) by smtp.gmail.com with ESMTPSA id 185sm46971597pfu.13.2018.05.07.02.18.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 May 2018 02:18:55 -0700 (PDT) From: Jagan Teki To: Mario Six Date: Mon, 7 May 2018 14:48:49 +0530 Message-Id: <20180507091849.25292-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 1/6] spi: kconfig: Move MPC8XXX_SPI to if DM_SPI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move MPC8XXX_SPI to DM_SPI defined since driver is now fully converted to dm. Signed-off-by: Jagan Teki --- drivers/spi/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ec92b84ed2..d93f7d0049 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -99,6 +99,11 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MPC8XXX_SPI + bool "MPC8XXX SPI Driver" + help + Enable support for SPI on the MPC8XXX PowerPC SoCs. + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" help @@ -288,11 +293,6 @@ config MPC8XX_SPI help Enable support for SPI on MPC8XX -config MPC8XXX_SPI - bool "MPC8XXX SPI Driver" - help - Enable support for SPI on the MPC8XXX PowerPC SoCs. - config MXC_SPI bool "MXC SPI Driver" help From patchwork Mon May 7 09:17:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 909679 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="oqcdQ8I7"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40ffdG2ZSqz9ryk for ; Mon, 7 May 2018 20:54:26 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id EAEFBC2210E; Mon, 7 May 2018 10:54:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2,RCVD_IN_SORBS_WEB,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BB22FC22048; Mon, 7 May 2018 10:54:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0F042C22061; Mon, 7 May 2018 09:17:59 +0000 (UTC) Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by lists.denx.de (Postfix) with ESMTPS id 286D0C2205C for ; Mon, 7 May 2018 09:17:59 +0000 (UTC) Received: by mail-pf0-f194.google.com with SMTP id o76so22381929pfi.5 for ; Mon, 07 May 2018 02:17:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id; bh=Zo+LFxPFDCUefjrT88CSC6X6TxtBzXpE67GlGWbcwfA=; b=oqcdQ8I7KR6SvLrTgoBUrvGz+vWIDnbNgxMmjDvqVWOx32N3Xx2Far+Tll3hvFJ/j/ yP/QpIgcXhZAcY2N3+HSLkm09Mo/whD9tsjbgTqJq7NF5aw3ldCD1UL0jisf7CZbZWtz QeKo9yteonk/vsMSSRkxzDoqlq/GAKyspg/js= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Zo+LFxPFDCUefjrT88CSC6X6TxtBzXpE67GlGWbcwfA=; b=lg3dsJOPJUgnsAKRoV5I/lKJVQXMP/GVqocns6g25xTOlA+BOoWHqGAGX/WU3cm+wP cwAdD7fpALLUb3jwQXfjdrN+wDrT5y+O4ULa1BtQwKsJxDj7lRUMVQP8Cs823codVjcR oCiK44c+o5+qyqGwTxl1G2Dpgd4eZ84FufNPzIJbVkZX5lwVjj03VZ/iNw3dNvNSjpxQ miUP3ecmx1FeqS8QywRN2kpJ0S8871uoIGEgqPm+qHkySuUmr+rtAbvcJVhFpev/c1yq cDXlfVhRMpiMCIAGPFccdold1Ty8zGz4Bt+oOLgQGxr84rjrVyN/stCuWk7Q1ujnKaDZ D6WA== X-Gm-Message-State: ALQs6tCp/BLI+7pbMvmEADyGNvMDPINEE4xhgWSRqAqAKgrlqL+ZgxYO hkFSnrsxEeckMiLvYaSxYnGVYQ== X-Google-Smtp-Source: AB8JxZoIc8x+++xefRGOzJRqu/dj9l61eO31ZkfqTPrlqUDrIatIg8qkO9/zUOJDWY+N2BXuqyZX1w== X-Received: by 2002:a63:ae49:: with SMTP id e9-v6mr28858578pgp.38.1525684677484; Mon, 07 May 2018 02:17:57 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.172]) by smtp.gmail.com with ESMTPSA id p24sm36179773pfk.58.2018.05.07.02.17.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 May 2018 02:17:56 -0700 (PDT) From: Jagan Teki To: Gilles Gameiro , Roger Meier , Adam Ford , Yegor Yefremov , Grazvydas Ignotas , Andrew F Davis , Nishanth Menon , Lars Poeschel , Enric Balletbo i Serra , Heiko Schocher , Steve Sakoman , Ash Charles , Stefan Roese , Lokesh Vutla , Dmitry Lifshitz , Tapani Utriainen , Marcin Niestroj , =?utf-8?q?Pali_Roh=C3=A1r?= , Hannes Schmelzer , Nikita Kiryanov , Igor Grinberg , Albert ARIBAU , Lothar Felten , "Derald D . Woods" , Vitaly Andrianov , Tom Rini Date: Mon, 7 May 2018 14:47:42 +0530 Message-Id: <20180507091742.25222-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 X-Mailman-Approved-At: Mon, 07 May 2018 10:54:18 +0000 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 2/6] spi: omap3_spi: Full dm conversion X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" omap3_spi now support dt along with platform data, respective boards need to switch into dm for the same. Tested-by: Adam Ford #omap3_logic Signed-off-by: Jagan Teki --- drivers/spi/Kconfig | 14 +- drivers/spi/omap3_spi.c | 337 +++++++++++------------------------ include/dm/platform_data/spi_omap3.h | 16 ++ 3 files changed, 125 insertions(+), 242 deletions(-) create mode 100644 include/dm/platform_data/spi_omap3.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d93f7d0049..72423beebf 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -111,6 +111,13 @@ config MVEBU_A3700_SPI used to access the SPI NOR flash on platforms embedding this Marvell IP core. +config OMAP3_SPI + bool "McSPI driver for OMAP" + help + SPI master controller for OMAP24XX and later Multichannel SPI + (McSPI). This driver be used to access SPI chips on platforms + embedding this OMAP3 McSPI IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32 @@ -305,11 +312,4 @@ config MXS_SPI Enable the MXS SPI controller driver. This driver can be used on the i.MX23 and i.MX28 SoCs. -config OMAP3_SPI - bool "McSPI driver for OMAP" - help - SPI master controller for OMAP24XX and later Multichannel SPI - (McSPI). This driver be used to access SPI chips on platforms - embedding this OMAP3 McSPI IP core. - endmenu # menu "SPI Support" diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 1ac691a68e..4108dcabbf 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -22,6 +22,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -109,9 +110,6 @@ struct mcspi { }; struct omap3_spi_priv { -#ifndef CONFIG_DM_SPI - struct spi_slave slave; -#endif struct mcspi *regs; unsigned int cs; unsigned int freq; @@ -312,12 +310,16 @@ static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len, return 0; } -static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { - unsigned int len; + struct udevice *bus = dev->parent; + struct omap3_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + unsigned int len; int ret = -1; + priv->cs = slave_plat->cs; if (priv->wordlen < 4 || priv->wordlen > 32) { printf("omap3_spi: invalid wordlen %d\n", priv->wordlen); return -1; @@ -353,78 +355,6 @@ static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen, return ret; } -static void _omap3_spi_set_speed(struct omap3_spi_priv *priv) -{ - uint32_t confr, div = 0; - - confr = readl(&priv->regs->channel[priv->cs].chconf); - - /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */ - if (priv->freq) { - while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div)) - > priv->freq) - div++; - } else { - div = 0xC; - } - - /* set clock divisor */ - confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK; - confr |= div << 2; - - omap3_spi_write_chconf(priv, confr); -} - -static void _omap3_spi_set_mode(struct omap3_spi_priv *priv) -{ - uint32_t confr; - - confr = readl(&priv->regs->channel[priv->cs].chconf); - - /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS - * REVISIT: this controller could support SPI_3WIRE mode. - */ - if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { - confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); - confr |= OMAP3_MCSPI_CHCONF_DPE0; - } else { - confr &= ~OMAP3_MCSPI_CHCONF_DPE0; - confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1; - } - - /* set SPI mode 0..3 */ - confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA); - if (priv->mode & SPI_CPHA) - confr |= OMAP3_MCSPI_CHCONF_PHA; - if (priv->mode & SPI_CPOL) - confr |= OMAP3_MCSPI_CHCONF_POL; - - /* set chipselect polarity; manage with FORCE */ - if (!(priv->mode & SPI_CS_HIGH)) - confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */ - else - confr &= ~OMAP3_MCSPI_CHCONF_EPOL; - - /* Transmit & receive mode */ - confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; - - omap3_spi_write_chconf(priv, confr); -} - -static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv) -{ - unsigned int confr; - - /* McSPI individual channel configuration */ - confr = readl(&priv->regs->channel[priv->wordlen].chconf); - - /* wordlength */ - confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK; - confr |= (priv->wordlen - 1) << 7; - - omap3_spi_write_chconf(priv, confr); -} - static void spi_reset(struct mcspi *regs) { unsigned int tmp; @@ -441,8 +371,10 @@ static void spi_reset(struct mcspi *regs) writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable); } -static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) +static int omap3_spi_claim_bus(struct udevice *dev) { + struct udevice *bus = dev->parent; + struct omap3_spi_priv *priv = dev_get_priv(bus); unsigned int conf; spi_reset(priv->regs); @@ -456,142 +388,6 @@ static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) conf |= OMAP3_MCSPI_MODULCTRL_SINGLE; writel(conf, &priv->regs->modulctrl); -} - -#ifndef CONFIG_DM_SPI - -static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave) -{ - return container_of(slave, struct omap3_spi_priv, slave); -} - -void spi_init(void) -{ - /* do nothing */ -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct omap3_spi_priv *priv = to_omap3_spi(slave); - - free(priv); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct omap3_spi_priv *priv = to_omap3_spi(slave); - - _omap3_spi_claim_bus(priv); - _omap3_spi_set_wordlen(priv); - _omap3_spi_set_mode(priv); - _omap3_spi_set_speed(priv); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct omap3_spi_priv *priv = to_omap3_spi(slave); - - /* Reset the SPI hardware */ - spi_reset(priv->regs); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct omap3_spi_priv *priv; - struct mcspi *regs; - - /* - * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules) - * with different number of chip selects (CS, channels): - * McSPI1 has 4 CS (bus 0, cs 0 - 3) - * McSPI2 has 2 CS (bus 1, cs 0 - 1) - * McSPI3 has 2 CS (bus 2, cs 0 - 1) - * McSPI4 has 1 CS (bus 3, cs 0) - */ - - switch (bus) { - case 0: - regs = (struct mcspi *)OMAP3_MCSPI1_BASE; - break; -#ifdef OMAP3_MCSPI2_BASE - case 1: - regs = (struct mcspi *)OMAP3_MCSPI2_BASE; - break; -#endif -#ifdef OMAP3_MCSPI3_BASE - case 2: - regs = (struct mcspi *)OMAP3_MCSPI3_BASE; - break; -#endif -#ifdef OMAP3_MCSPI4_BASE - case 3: - regs = (struct mcspi *)OMAP3_MCSPI4_BASE; - break; -#endif - default: - printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus); - return NULL; - } - - if (((bus == 0) && (cs > 3)) || - ((bus == 1) && (cs > 1)) || - ((bus == 2) && (cs > 1)) || - ((bus == 3) && (cs > 0))) { - printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus); - return NULL; - } - - if (max_hz > OMAP3_MCSPI_MAX_FREQ) { - printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n", - max_hz); - return NULL; - } - - if (mode > SPI_MODE_3) { - printf("SPI error: unsupported SPI mode %i\n", mode); - return NULL; - } - - priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs); - if (!priv) { - printf("SPI error: malloc of SPI structure failed\n"); - return NULL; - } - - priv->regs = regs; - priv->cs = cs; - priv->freq = max_hz; - priv->mode = mode; - priv->wordlen = priv->slave.wordlen; -#if 0 - /* Please migrate to DM_SPI support for this feature. */ - priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; -#endif - - return &priv->slave; -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct omap3_spi_priv *priv = to_omap3_spi(slave); - - return _spi_xfer(priv, bitlen, dout, din, flags); -} - -#else - -static int omap3_spi_claim_bus(struct udevice *dev) -{ - struct udevice *bus = dev->parent; - struct omap3_spi_priv *priv = dev_get_priv(bus); - struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); - - priv->cs = slave_plat->cs; - _omap3_spi_claim_bus(priv); return 0; } @@ -612,22 +408,31 @@ static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen) struct udevice *bus = dev->parent; struct omap3_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + unsigned int confr; + + /* McSPI individual channel configuration */ + confr = readl(&priv->regs->channel[wordlen].chconf); + + /* wordlength */ + confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK; + confr |= (wordlen - 1) << 7; priv->cs = slave_plat->cs; + omap3_spi_write_chconf(priv, confr); + priv->wordlen = wordlen; - _omap3_spi_set_wordlen(priv); return 0; } static int omap3_spi_probe(struct udevice *dev) { + struct omap3_spi_platdata *plat = dev->platdata; struct omap3_spi_priv *priv = dev_get_priv(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); - struct omap2_mcspi_platform_config* data = - (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev); + priv->regs = plat->regs; + priv->pin_dir = plat->pin_dir; + priv->wordlen = plat->wordlen; priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset); if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in")) @@ -635,16 +440,8 @@ static int omap3_spi_probe(struct udevice *dev) else priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT; priv->wordlen = SPI_DEFAULT_WORDLEN; - return 0; -} - -static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct udevice *bus = dev->parent; - struct omap3_spi_priv *priv = dev_get_priv(bus); - return _spi_xfer(priv, bitlen, dout, din, flags); + return 0; } static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed) @@ -652,10 +449,25 @@ static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed) struct udevice *bus = dev->parent; struct omap3_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + uint32_t confr, div = 0; priv->cs = slave_plat->cs; - priv->freq = slave_plat->max_hz; - _omap3_spi_set_speed(priv); + confr = readl(&priv->regs->channel[priv->cs].chconf); + + /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */ + if (speed) { + while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div)) + > speed) + div++; + } else { + div = 0xC; + } + + /* set clock divisor */ + confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK; + confr |= div << 2; + + omap3_spi_write_chconf(priv, confr); return 0; } @@ -665,10 +477,39 @@ static int omap3_spi_set_mode(struct udevice *dev, uint mode) struct udevice *bus = dev->parent; struct omap3_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + uint32_t confr; priv->cs = slave_plat->cs; - priv->mode = slave_plat->mode; - _omap3_spi_set_mode(priv); + confr = readl(&priv->regs->channel[priv->cs].chconf); + + /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS + * REVISIT: this controller could support SPI_3WIRE mode. + */ + if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { + confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); + confr |= OMAP3_MCSPI_CHCONF_DPE0; + } else { + confr &= ~OMAP3_MCSPI_CHCONF_DPE0; + confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1; + } + + /* set SPI mode 0..3 */ + confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA); + if (mode & SPI_CPHA) + confr |= OMAP3_MCSPI_CHCONF_PHA; + if (mode & SPI_CPOL) + confr |= OMAP3_MCSPI_CHCONF_POL; + + /* set chipselect polarity; manage with FORCE */ + if (!(mode & SPI_CS_HIGH)) + confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */ + else + confr &= ~OMAP3_MCSPI_CHCONF_EPOL; + + /* Transmit & receive mode */ + confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; + + omap3_spi_write_chconf(priv, confr); return 0; } @@ -677,7 +518,7 @@ static const struct dm_spi_ops omap3_spi_ops = { .claim_bus = omap3_spi_claim_bus, .release_bus = omap3_spi_release_bus, .set_wordlen = omap3_spi_set_wordlen, - .xfer = omap3_spi_xfer, + .xfer = omap3_spi_xfer, .set_speed = omap3_spi_set_speed, .set_mode = omap3_spi_set_mode, /* @@ -686,6 +527,28 @@ static const struct dm_spi_ops omap3_spi_ops = { */ }; +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int omap3_spi_ofdata_to_platdata(struct udevice *dev) +{ + struct omap3_spi_platdata *plat = dev->platdata; + struct omap2_mcspi_platform_config* data = + (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs = (struct mcspi *)addr; + plat->regs += data->regs_offset; + plat->pin_dir = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "ti,pindir-d0-out-d1-in", + MCSPI_PINDIR_D0_IN_D1_OUT); + plat->wordlen = SPI_DEFAULT_WORDLEN; + + return 0; +} + static struct omap2_mcspi_platform_config omap2_pdata = { .regs_offset = 0, }; @@ -699,13 +562,17 @@ static const struct udevice_id omap3_spi_ids[] = { { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata }, { } }; +#endif U_BOOT_DRIVER(omap3_spi) = { .name = "omap3_spi", .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) .of_match = omap3_spi_ids, + .ofdata_to_platdata = omap3_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct omap3_spi_platdata), +#endif .probe = omap3_spi_probe, .ops = &omap3_spi_ops, .priv_auto_alloc_size = sizeof(struct omap3_spi_priv), }; -#endif diff --git a/include/dm/platform_data/spi_omap3.h b/include/dm/platform_data/spi_omap3.h new file mode 100644 index 0000000000..9323266de7 --- /dev/null +++ b/include/dm/platform_data/spi_omap3.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_omap3_h +#define __spi_omap3_h + +struct omap3_spi_platdata { + struct mcspi *regs; + unsigned int wordlen; + unsigned int pin_dir:1; +}; + +#endif /* __spi_omap3_h */ From patchwork Mon May 7 09:13:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 909620 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Mon, 07 May 2018 02:13:40 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.172]) by smtp.gmail.com with ESMTPSA id k186sm53619136pfc.142.2018.05.07.02.13.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 May 2018 02:13:39 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Mon, 7 May 2018 14:43:31 +0530 Message-Id: <20180507091331.24943-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 Cc: Tom Rini , Vitaly Andrianov , Peter Howard Subject: [U-Boot] [PATCH v3 3/6] spi: davinci: Full dm conversion X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" davinci_spi now support dt along with platform data, respective boards need to switch into dm for the same. Signed-off-by: Jagan Teki --- Changes for v3: - rebased to master drivers/spi/Kconfig | 12 +- drivers/spi/davinci_spi.c | 289 +++++++++------------------------ include/dm/platform_data/spi_davinci.h | 15 ++ 3 files changed, 97 insertions(+), 219 deletions(-) create mode 100644 include/dm/platform_data/spi_davinci.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 72423beebf..46fc6bfdd7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -70,6 +70,12 @@ config CADENCE_QSPI used to access the SPI NOR flash on platforms embedding this Cadence IP core. +config DAVINCI_SPI + bool "Davinci & Keystone SPI driver" + depends on ARCH_DAVINCI || ARCH_KEYSTONE + help + Enable the Davinci SPI driver + config DESIGNWARE_SPI bool "Designware SPI driver" help @@ -259,12 +265,6 @@ config FSL_QSPI used to access the SPI NOR flash on platforms embedding this Freescale IP core. -config DAVINCI_SPI - bool "Davinci & Keystone SPI driver" - depends on ARCH_DAVINCI || ARCH_KEYSTONE - help - Enable the Davinci SPI driver - config SH_SPI bool "SuperH SPI driver" help diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index eda252d0b3..065fa00e17 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -15,6 +15,7 @@ #include #include #include +#include /* SPIGCR0 */ #define SPIGCR0_SPIENA_MASK 0x1 @@ -119,9 +120,6 @@ struct davinci_spi_regs { /* davinci spi slave */ struct davinci_spi_slave { -#ifndef CONFIG_DM_SPI - struct spi_slave slave; -#endif struct davinci_spi_regs *regs; unsigned int freq; /* current SPI bus frequency */ unsigned int mode; /* current SPI mode used */ @@ -241,11 +239,43 @@ static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned return 0; } +static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) +{ + struct davinci_spi_slave *ds = dev_get_priv(bus); -static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) + debug("%s speed %u\n", __func__, max_hz); + if (max_hz > CONFIG_SYS_SPI_CLK / 2) + return -EINVAL; + + ds->freq = max_hz; + + return 0; +} + +static int davinci_spi_set_mode(struct udevice *bus, uint mode) +{ + struct davinci_spi_slave *ds = dev_get_priv(bus); + + debug("%s mode %u\n", __func__, mode); + ds->mode = mode; + + return 0; +} + +static int davinci_spi_claim_bus(struct udevice *dev) { + struct dm_spi_slave_platdata *slave_plat = + dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct davinci_spi_slave *ds = dev_get_priv(bus); unsigned int mode = 0, scalar; + if (slave_plat->cs >= ds->num_cs) { + printf("Invalid SPI chipselect\n"); + return -EINVAL; + } + ds->half_duplex = slave_plat->mode & SPI_PREAMBLE; + /* Enable the SPI hardware */ writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); udelay(1000); @@ -255,7 +285,7 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); /* CS, CLK, SIMO and SOMI are functional pins */ - writel(((1 << cs) | SPIPC0_CLKFUN_MASK | + writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); /* setup format */ @@ -293,20 +323,32 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) return 0; } -static int __davinci_spi_release_bus(struct davinci_spi_slave *ds) +static int davinci_spi_release_bus(struct udevice *dev) { + struct davinci_spi_slave *ds = dev_get_priv(dev->parent); + /* Disable the SPI hardware */ writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); return 0; } -static int __davinci_spi_xfer(struct davinci_spi_slave *ds, - unsigned int bitlen, const void *dout, void *din, - unsigned long flags) +static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, + unsigned long flags) { + struct dm_spi_slave_platdata *slave = + dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct davinci_spi_slave *ds = dev_get_priv(bus); unsigned int len; + if (slave->cs >= ds->num_cs) { + printf("Invalid SPI chipselect\n"); + return -EINVAL; + } + ds->cur_cs = slave->cs; + if (bitlen == 0) /* Finish any previously submitted transfers */ goto out; @@ -340,240 +382,61 @@ out: u8 dummy = 0; davinci_spi_write(ds, 1, &dummy, flags); } - return 0; -} - -#ifndef CONFIG_DM_SPI - -static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) -{ - return container_of(slave, struct davinci_spi_slave, slave); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - int ret = 0; - - switch (bus) { - case SPI0_BUS: - if (cs < SPI0_NUM_CS) - ret = 1; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - if (cs < SPI1_NUM_CS) - ret = 1; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - if (cs < SPI2_NUM_CS) - ret = 1; - break; -#endif - default: - /* Invalid bus number. Do nothing */ - break; - } - return ret; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* do nothing */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* do nothing */ -} - -void spi_init(void) -{ - /* do nothing */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct davinci_spi_slave *ds; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); - if (!ds) - return NULL; - - switch (bus) { - case SPI0_BUS: - ds->regs = (struct davinci_spi_regs *)SPI0_BASE; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - ds->regs = (struct davinci_spi_regs *)SPI1_BASE; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - ds->regs = (struct davinci_spi_regs *)SPI2_BASE; - break; -#endif - default: /* Invalid bus number */ - return NULL; - } - - ds->freq = max_hz; - ds->mode = mode; - - return &ds->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - free(ds); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - ds->cur_cs = slave->cs; - - return __davinci_spi_xfer(ds, bitlen, dout, din, flags); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - -#ifdef CONFIG_SPI_HALF_DUPLEX - ds->half_duplex = true; -#else - ds->half_duplex = false; -#endif - return __davinci_spi_claim_bus(ds, ds->slave.cs); -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - __davinci_spi_release_bus(ds); -} - -#else -static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) -{ - struct davinci_spi_slave *ds = dev_get_priv(bus); - - debug("%s speed %u\n", __func__, max_hz); - if (max_hz > CONFIG_SYS_SPI_CLK / 2) - return -EINVAL; - - ds->freq = max_hz; return 0; } -static int davinci_spi_set_mode(struct udevice *bus, uint mode) -{ - struct davinci_spi_slave *ds = dev_get_priv(bus); - - debug("%s mode %u\n", __func__, mode); - ds->mode = mode; - - return 0; -} - -static int davinci_spi_claim_bus(struct udevice *dev) -{ - struct dm_spi_slave_platdata *slave_plat = - dev_get_parent_platdata(dev); - struct udevice *bus = dev->parent; - struct davinci_spi_slave *ds = dev_get_priv(bus); - - if (slave_plat->cs >= ds->num_cs) { - printf("Invalid SPI chipselect\n"); - return -EINVAL; - } - ds->half_duplex = slave_plat->mode & SPI_PREAMBLE; - - return __davinci_spi_claim_bus(ds, slave_plat->cs); -} - -static int davinci_spi_release_bus(struct udevice *dev) -{ - struct davinci_spi_slave *ds = dev_get_priv(dev->parent); - - return __davinci_spi_release_bus(ds); -} +static const struct dm_spi_ops davinci_spi_ops = { + .claim_bus = davinci_spi_claim_bus, + .release_bus = davinci_spi_release_bus, + .xfer = davinci_spi_xfer, + .set_speed = davinci_spi_set_speed, + .set_mode = davinci_spi_set_mode, +}; -static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, - unsigned long flags) +static int davinci_spi_probe(struct udevice *bus) { - struct dm_spi_slave_platdata *slave = - dev_get_parent_platdata(dev); - struct udevice *bus = dev->parent; struct davinci_spi_slave *ds = dev_get_priv(bus); + struct davinci_spi_platdata *plat = bus->platdata; + ds->regs = plat->regs; + ds->num_cs = plat->num_cs; - if (slave->cs >= ds->num_cs) { - printf("Invalid SPI chipselect\n"); - return -EINVAL; - } - ds->cur_cs = slave->cs; - - return __davinci_spi_xfer(ds, bitlen, dout, din, flags); -} - -static int davinci_spi_probe(struct udevice *bus) -{ - /* Nothing to do */ return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) static int davinci_ofdata_to_platadata(struct udevice *bus) { - struct davinci_spi_slave *ds = dev_get_priv(bus); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); + struct davinci_spi_platdata *plat = bus->platdata; + fdt_addr_t addr; - ds->regs = devfdt_map_physmem(bus, sizeof(struct davinci_spi_regs)); - if (!ds->regs) { - printf("%s: could not map device address\n", __func__); + addr = devfdt_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) return -EINVAL; - } - ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); + + plat->regs = (struct davinci_spi_regs *)addr; + plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4); return 0; } -static const struct dm_spi_ops davinci_spi_ops = { - .claim_bus = davinci_spi_claim_bus, - .release_bus = davinci_spi_release_bus, - .xfer = davinci_spi_xfer, - .set_speed = davinci_spi_set_speed, - .set_mode = davinci_spi_set_mode, -}; - static const struct udevice_id davinci_spi_ids[] = { { .compatible = "ti,keystone-spi" }, { .compatible = "ti,dm6441-spi" }, { .compatible = "ti,da830-spi" }, { } }; +#endif U_BOOT_DRIVER(davinci_spi) = { .name = "davinci_spi", .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) .of_match = davinci_spi_ids, - .ops = &davinci_spi_ops, .ofdata_to_platdata = davinci_ofdata_to_platadata, - .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), + .platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata), +#endif .probe = davinci_spi_probe, + .ops = &davinci_spi_ops, + .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), }; -#endif diff --git a/include/dm/platform_data/spi_davinci.h b/include/dm/platform_data/spi_davinci.h new file mode 100644 index 0000000000..fbc62c262a --- /dev/null +++ b/include/dm/platform_data/spi_davinci.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2018 Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_davinci_h +#define __spi_davinci_h + +struct davinci_spi_platdata { + struct davinci_spi_regs *regs; + u8 num_cs; /* total no. of CS available */ +}; + +#endif /* __spi_davinci_h */ From patchwork Mon May 7 09:12:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 909619 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Mon, 07 May 2018 02:12:29 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.172]) by smtp.gmail.com with ESMTPSA id e22-v6sm27764603pgn.0.2018.05.07.02.12.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 May 2018 02:12:29 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Mon, 7 May 2018 14:42:21 +0530 Message-Id: <20180507091221.24860-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 Cc: Tom Rini , Vitaly Andrianov , Peter Howard Subject: [U-Boot] [PATCH v3 4/6] spi: ti_qspi: Full dm conversion X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" ti_qspi now support dt along with platform data, respective boards need to switch into dm for the same. Signed-off-by: Jagan Teki --- Changes for v4: - rebased to master drivers/spi/Kconfig | 12 +- drivers/spi/ti_qspi.c | 490 ++++++++++++--------------------- include/dm/platform_data/spi_ti_qspi.h | 19 ++ 3 files changed, 202 insertions(+), 319 deletions(-) create mode 100644 include/dm/platform_data/spi_ti_qspi.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 46fc6bfdd7..73dd33f716 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -212,6 +212,12 @@ config TEGRA210_QSPI be used to access SPI chips on platforms embedding this NVIDIA Tegra210 IP core. +config TI_QSPI + bool "TI QSPI driver" + help + Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. + This driver support spi flash single, quad and memory reads. + config XILINX_SPI bool "Xilinx SPI driver" help @@ -277,12 +283,6 @@ config SH_QSPI Enable the Renesas Quad SPI controller driver. This driver can be used on Renesas SoCs. -config TI_QSPI - bool "TI QSPI driver" - help - Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. - This driver support spi flash single, quad and memory reads. - config KIRKWOOD_SPI bool "Marvell Kirkwood SPI Driver" help diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index bea3aff943..2f62016422 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -20,6 +20,8 @@ #include #include +#include + DECLARE_GLOBAL_DATA_PTR; /* ti qpsi register bit masks */ @@ -34,17 +36,17 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CLK_DIV_MAX 0xffff /* command */ #define QSPI_EN_CS(n) (n << 28) -#define QSPI_WLEN(n) ((n-1) << 19) +#define QSPI_WLEN(n) ((n - 1) << 19) #define QSPI_3_PIN BIT(18) #define QSPI_RD_SNGL BIT(16) #define QSPI_WR_SNGL (2 << 16) #define QSPI_INVAL (4 << 16) #define QSPI_RD_QUAD (7 << 16) /* device control */ -#define QSPI_DD(m, n) (m << (3 + n*8)) -#define QSPI_CKPHA(n) (1 << (2 + n*8)) -#define QSPI_CSPOL(n) (1 << (1 + n*8)) -#define QSPI_CKPOL(n) (1 << (n*8)) +#define QSPI_DD(m, n) (m << (3 + n * 8)) +#define QSPI_CKPHA(n) (1 << (2 + n * 8)) +#define QSPI_CSPOL(n) (1 << (1 + n * 8)) +#define QSPI_CKPOL(n) (1 << (n * 8)) /* status */ #define QSPI_WC BIT(1) #define QSPI_BUSY BIT(0) @@ -99,13 +101,9 @@ struct ti_qspi_regs { /* ti qspi priv */ struct ti_qspi_priv { -#ifndef CONFIG_DM_SPI - struct spi_slave slave; -#else void *memory_map; uint max_hz; u32 num_cs; -#endif struct ti_qspi_regs *base; void *ctrl_mod_mmap; ulong fclk; @@ -114,37 +112,113 @@ struct ti_qspi_priv { u32 dc; }; -static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) +/* TODO: control from sf layer to here through dm-spi */ +#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) +void spi_flash_copy_mmap(void *data, void *offset, size_t len) +{ + unsigned int addr = (unsigned int)(data); + unsigned int edma_slot_num = 1; + + /* Invalidate the area, so no writeback into the RAM races with DMA */ + invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN)); + + /* enable edma3 clocks */ + enable_edma3_clocks(); + + /* Call edma3 api to do actual DMA transfer */ + edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len); + + /* disable edma3 clocks */ + disable_edma3_clocks(); + + *((unsigned int *)offset) += len; +} +#endif + +static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) +{ + writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); + /* dummy readl to ensure bus sync */ + readl(&priv->base->cmd); +} + +static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) +{ + u32 val; + + val = readl(ctrl_mod_mmap); + if (enable) + val |= MEM_CS(cs); + else + val &= MEM_CS_UNSELECT; + writel(val, ctrl_mod_mmap); +} + +static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, + struct spi_slave *slave, + bool enable) +{ + u32 memval; + u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL); + + if (!enable) { + writel(0, &priv->base->setup0); + return; + } + + memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; + + switch (mode) { + case SPI_RX_QUAD: + memval |= QSPI_CMD_READ_QUAD; + memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + memval |= QSPI_SETUP0_READ_QUAD; + slave->mode |= SPI_RX_QUAD; + break; + case SPI_RX_DUAL: + memval |= QSPI_CMD_READ_DUAL; + memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + memval |= QSPI_SETUP0_READ_DUAL; + break; + default: + memval |= QSPI_CMD_READ; + memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS; + memval |= QSPI_SETUP0_READ_NORMAL; + break; + } + + writel(memval, &priv->base->setup0); +} + +static int ti_qspi_set_speed(struct udevice *bus, uint max_hz) { + struct ti_qspi_priv *priv = dev_get_priv(bus); uint clk_div; - if (!hz) + if (!max_hz) clk_div = 0; else - clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; + clk_div = DIV_ROUND_UP(priv->fclk, max_hz) - 1; /* truncate clk_div value to QSPI_CLK_DIV_MAX */ if (clk_div > QSPI_CLK_DIV_MAX) clk_div = QSPI_CLK_DIV_MAX; - debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); + debug("%s: max_hz: %d, clock divider %d\n", __func__, max_hz, clk_div); /* disable SCLK */ writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, &priv->base->clk_ctrl); /* enable SCLK and program the clk divider */ writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); -} -static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) -{ - writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); - /* dummy readl to ensure bus sync */ - readl(&priv->base->cmd); + return 0; } -static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) +static int ti_qspi_set_mode(struct udevice *bus, uint mode) { + struct ti_qspi_priv *priv = dev_get_priv(bus); + priv->dc = 0; if (mode & SPI_CPHA) priv->dc |= QSPI_CKPHA(0); @@ -156,57 +230,83 @@ static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) return 0; } -static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs) +static int ti_qspi_claim_bus(struct udevice *dev) { + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + if (slave_plat->cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; + } + + __ti_qspi_setup_memorymap(priv, slave, true); + writel(priv->dc, &priv->base->dc); writel(0, &priv->base->cmd); writel(0, &priv->base->data); - priv->dc <<= cs * 8; + priv->dc <<= slave_plat->cs * 8; writel(priv->dc, &priv->base->dc); return 0; } -static void __ti_qspi_release_bus(struct ti_qspi_priv *priv) +static int ti_qspi_release_bus(struct udevice *dev) { + struct spi_slave *slave = dev_get_parent_priv(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + __ti_qspi_setup_memorymap(priv, slave, false); + writel(0, &priv->base->dc); writel(0, &priv->base->cmd); writel(0, &priv->base->data); -} - -static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) -{ - u32 val; - val = readl(ctrl_mod_mmap); - if (enable) - val |= MEM_CS(cs); - else - val &= MEM_CS_UNSELECT; - writel(val, ctrl_mod_mmap); + return 0; } -static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, - const void *dout, void *din, unsigned long flags, - u32 cs) +static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { - uint words = bitlen >> 3; /* fixed 8-bit word length */ const uchar *txp = dout; + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + uint words = bitlen >> 3; /* fixed 8-bit word length */ uchar *rxp = din; + struct ti_qspi_priv *priv; + struct udevice *bus; uint status; int timeout; + bus = dev->parent; + priv = dev_get_priv(bus); + + if (slave->cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; + } + /* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { writel(MM_SWITCH, &priv->base->memswitch); if (priv->ctrl_mod_mmap) - ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true); + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, + slave->cs, true); return 0; } else if (flags & SPI_XFER_MMAP_END) { writel(~MM_SWITCH, &priv->base->memswitch); if (priv->ctrl_mod_mmap) - ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false); + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, + slave->cs, false); return 0; } @@ -221,7 +321,7 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, /* Setup command reg */ priv->cmd = 0; priv->cmd |= QSPI_WLEN(8); - priv->cmd |= QSPI_EN_CS(cs); + priv->cmd |= QSPI_EN_CS(slave->cs); if (priv->mode & SPI_3WIRE) priv->cmd |= QSPI_3_PIN; priv->cmd |= 0xfff; @@ -282,7 +382,7 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, *rxp++ = readl(&priv->base->data); xfer_len = 1; debug("rx done, status %08x, read %02x\n", - status, *(rxp-1)); + status, *(rxp - 1)); } words -= xfer_len; } @@ -294,263 +394,40 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, return 0; } -/* TODO: control from sf layer to here through dm-spi */ -#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) -void spi_flash_copy_mmap(void *data, void *offset, size_t len) -{ - unsigned int addr = (unsigned int) (data); - unsigned int edma_slot_num = 1; - - /* Invalidate the area, so no writeback into the RAM races with DMA */ - invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN)); - - /* enable edma3 clocks */ - enable_edma3_clocks(); - - /* Call edma3 api to do actual DMA transfer */ - edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len); - - /* disable edma3 clocks */ - disable_edma3_clocks(); - - *((unsigned int *)offset) += len; -} -#endif - -#ifndef CONFIG_DM_SPI - -static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) -{ - return container_of(slave, struct ti_qspi_priv, slave); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* CS handled in xfer */ - return; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - ti_qspi_cs_deactivate(priv); -} - -void spi_init(void) -{ - /* nothing to do */ -} - -static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) -{ - u32 memval = 0; - -#ifdef CONFIG_QSPI_QUAD_SUPPORT - struct spi_slave *slave = &priv->slave; - memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_8_BITS | - QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS); - slave->mode |= SPI_RX_QUAD; -#else - memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_NO_BITS | - QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS; -#endif - - writel(memval, &priv->base->setup0); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct ti_qspi_priv *priv; - -#ifdef CONFIG_AM43XX - gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); - gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); -#endif - - priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs); - if (!priv) { - printf("SPI_error: Fail to allocate ti_qspi_priv\n"); - return NULL; - } - - priv->base = (struct ti_qspi_regs *)QSPI_BASE; - priv->mode = mode; -#if defined(CONFIG_DRA7XX) - priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO; - priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA; - priv->fclk = QSPI_DRA7XX_FCLK; -#else - priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x; - priv->fclk = QSPI_FCLK; -#endif - - ti_spi_set_speed(priv, max_hz); - -#ifdef CONFIG_TI_SPI_MMAP - ti_spi_setup_spi_register(priv); -#endif - - return &priv->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - free(priv); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); - __ti_qspi_set_mode(priv, priv->mode); - return __ti_qspi_claim_bus(priv, priv->slave.cs); -} -void spi_release_bus(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); - __ti_qspi_release_bus(priv); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n", - priv->slave.bus, priv->slave.cs, bitlen, flags); - return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs); -} - -#else /* CONFIG_DM_SPI */ - -static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, - struct spi_slave *slave, - bool enable) -{ - u32 memval; - u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL); - - if (!enable) { - writel(0, &priv->base->setup0); - return; - } - - memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; - - switch (mode) { - case SPI_RX_QUAD: - memval |= QSPI_CMD_READ_QUAD; - memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; - memval |= QSPI_SETUP0_READ_QUAD; - slave->mode |= SPI_RX_QUAD; - break; - case SPI_RX_DUAL: - memval |= QSPI_CMD_READ_DUAL; - memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; - memval |= QSPI_SETUP0_READ_DUAL; - break; - default: - memval |= QSPI_CMD_READ; - memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS; - memval |= QSPI_SETUP0_READ_NORMAL; - break; - } - - writel(memval, &priv->base->setup0); -} - +static const struct dm_spi_ops ti_qspi_ops = { + .claim_bus = ti_qspi_claim_bus, + .release_bus = ti_qspi_release_bus, + .xfer = ti_qspi_xfer, + .set_speed = ti_qspi_set_speed, + .set_mode = ti_qspi_set_mode, +}; -static int ti_qspi_set_speed(struct udevice *bus, uint max_hz) +static int ti_qspi_probe(struct udevice *bus) { + struct ti_qspi_platdata *plat = bus->platdata; struct ti_qspi_priv *priv = dev_get_priv(bus); - ti_spi_set_speed(priv, max_hz); + priv->fclk = plat->fclk; + priv->ctrl_mod_mmap = plat->ctrl_mod_mmap; + priv->base = plat->base; + priv->memory_map = plat->memory_map; + priv->max_hz = plat->max_hz; + priv->num_cs = plat->num_cs; return 0; } -static int ti_qspi_set_mode(struct udevice *bus, uint mode) -{ - struct ti_qspi_priv *priv = dev_get_priv(bus); - return __ti_qspi_set_mode(priv, mode); -} - -static int ti_qspi_claim_bus(struct udevice *dev) -{ - struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); - struct spi_slave *slave = dev_get_parent_priv(dev); - struct ti_qspi_priv *priv; - struct udevice *bus; - - bus = dev->parent; - priv = dev_get_priv(bus); - - if (slave_plat->cs > priv->num_cs) { - debug("invalid qspi chip select\n"); - return -EINVAL; - } - - __ti_qspi_setup_memorymap(priv, slave, true); - - return __ti_qspi_claim_bus(priv, slave_plat->cs); -} - -static int ti_qspi_release_bus(struct udevice *dev) +static int ti_qspi_child_pre_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); - struct ti_qspi_priv *priv; - struct udevice *bus; - - bus = dev->parent; - priv = dev_get_priv(bus); - - __ti_qspi_setup_memorymap(priv, slave, false); - __ti_qspi_release_bus(priv); - - return 0; -} - -static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); - struct ti_qspi_priv *priv; - struct udevice *bus; - - bus = dev->parent; - priv = dev_get_priv(bus); - - if (slave->cs > priv->num_cs) { - debug("invalid qspi chip select\n"); - return -EINVAL; - } - - return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs); -} - -static int ti_qspi_probe(struct udevice *bus) -{ + struct udevice *bus = dev_get_parent(dev); struct ti_qspi_priv *priv = dev_get_priv(bus); - priv->fclk = dev_get_driver_data(bus); - + slave->memory_map = priv->memory_map; return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) static void *map_syscon_chipselects(struct udevice *bus) { #if CONFIG_IS_ENABLED(SYSCON) @@ -576,7 +453,7 @@ static void *map_syscon_chipselects(struct udevice *bus) cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus), "syscon-chipselects", &len); - if (len < 2*sizeof(fdt32_t)) { + if (len < 2 * sizeof(fdt32_t)) { debug("%s: offset not available\n", __func__); return NULL; } @@ -584,6 +461,7 @@ static void *map_syscon_chipselects(struct udevice *bus) return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0); #else fdt_addr_t addr; + addr = devfdt_get_addr_index(bus, 2); return (addr == FDT_ADDR_T_NONE) ? NULL : map_physmem(addr, 0, MAP_NOCACHE); @@ -592,61 +470,47 @@ static void *map_syscon_chipselects(struct udevice *bus) static int ti_qspi_ofdata_to_platdata(struct udevice *bus) { - struct ti_qspi_priv *priv = dev_get_priv(bus); + struct ti_qspi_platdata *plat = bus->platdata; const void *blob = gd->fdt_blob; int node = dev_of_offset(bus); - priv->ctrl_mod_mmap = map_syscon_chipselects(bus); - priv->base = map_physmem(devfdt_get_addr(bus), + plat->fclk = dev_get_driver_data(bus); + plat->ctrl_mod_mmap = map_syscon_chipselects(bus); + plat->base = map_physmem(devfdt_get_addr(bus), sizeof(struct ti_qspi_regs), MAP_NOCACHE); - priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0, + plat->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0, MAP_NOCACHE); - priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); - if (priv->max_hz < 0) { + plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); + if (plat->max_hz < 0) { debug("Error: Max frequency missing\n"); return -ENODEV; } - priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); + plat->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__, - (int)priv->base, priv->max_hz); + (int)plat->base, plat->max_hz); return 0; } -static int ti_qspi_child_pre_probe(struct udevice *dev) -{ - struct spi_slave *slave = dev_get_parent_priv(dev); - struct udevice *bus = dev_get_parent(dev); - struct ti_qspi_priv *priv = dev_get_priv(bus); - - slave->memory_map = priv->memory_map; - return 0; -} - -static const struct dm_spi_ops ti_qspi_ops = { - .claim_bus = ti_qspi_claim_bus, - .release_bus = ti_qspi_release_bus, - .xfer = ti_qspi_xfer, - .set_speed = ti_qspi_set_speed, - .set_mode = ti_qspi_set_mode, -}; - static const struct udevice_id ti_qspi_ids[] = { { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK}, { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK}, { } }; +#endif U_BOOT_DRIVER(ti_qspi) = { .name = "ti_qspi", .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) .of_match = ti_qspi_ids, - .ops = &ti_qspi_ops, .ofdata_to_platdata = ti_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ti_qspi_platdata), +#endif + .ops = &ti_qspi_ops, .priv_auto_alloc_size = sizeof(struct ti_qspi_priv), .probe = ti_qspi_probe, .child_pre_probe = ti_qspi_child_pre_probe, }; -#endif /* CONFIG_DM_SPI */ diff --git a/include/dm/platform_data/spi_ti_qspi.h b/include/dm/platform_data/spi_ti_qspi.h new file mode 100644 index 0000000000..3f5355284e --- /dev/null +++ b/include/dm/platform_data/spi_ti_qspi.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2018 Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_ti_qspi_h +#define __spi_ti_qspi_h + +struct ti_qspi_platdata { + struct ti_qspi_regs *base; + void *ctrl_mod_mmap; + ulong fclk; + void *memory_map; + uint max_hz; + u32 num_cs; +}; + +#endif /* __spi_ti_qspi_h */ From patchwork Mon May 7 09:11:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 909618 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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Mon, 07 May 2018 02:11:12 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.172]) by smtp.gmail.com with ESMTPSA id z15-v6sm36490552pgr.55.2018.05.07.02.11.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 May 2018 02:11:12 -0700 (PDT) From: Jagan Teki To: Walter Schweizer , Valentin Longchamp , Phil Sutter , Stefan Roese , Simon Glass , Tuomas Tynkkynen , Sam Protsenko , Dirk Eibach , Mario Six , Michael Walle , Simon Guinot , Konstantin Porotchkin , Jason Cooper , =?utf-8?q?Marek_Beh=C3=BAn?= Date: Mon, 7 May 2018 14:41:00 +0530 Message-Id: <20180507091100.24688-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 5/6] spi: kirkwood: Get drvdata in .ofdata_to_platdata X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Get the is_errata_50mhz_ac in .ofdata_to_platdata, and reuse it in .set_mode this can eventually initialized dt code at once and adding room to add platdata. Signed-off-by: Jagan Teki --- drivers/spi/kirkwood_spi.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 1ad8cdee64..4850a2b955 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -249,6 +249,7 @@ struct mvebu_spi_dev { struct mvebu_spi_platdata { struct kwspi_registers *spireg; + bool is_errata_50mhz_ac; }; struct mvebu_spi_priv { @@ -310,7 +311,6 @@ static int mvebu_spi_set_mode(struct udevice *bus, uint mode) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); struct kwspi_registers *reg = plat->spireg; - const struct mvebu_spi_dev *drvdata; u32 data = readl(®->cfg); data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF); @@ -324,8 +324,7 @@ static int mvebu_spi_set_mode(struct udevice *bus, uint mode) writel(data, ®->cfg); - drvdata = (struct mvebu_spi_dev *)dev_get_driver_data(bus); - if (drvdata->is_errata_50mhz_ac) + if (plat->is_errata_50mhz_ac) mvebu_spi_50mhz_ac_timing_erratum(bus, mode); return 0; @@ -368,8 +367,11 @@ static int mvebu_spi_probe(struct udevice *bus) static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + const struct mvebu_spi_dev *drvdata = + (struct mvebu_spi_dev *)dev_get_driver_data(bus); plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus); + plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac; return 0; } From patchwork Mon May 7 09:10:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 909617 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; 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Mon, 07 May 2018 02:10:52 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.172]) by smtp.gmail.com with ESMTPSA id h75sm35749436pfh.148.2018.05.07.02.10.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 May 2018 02:10:51 -0700 (PDT) From: Jagan Teki To: Walter Schweizer , Valentin Longchamp , Phil Sutter , Stefan Roese , Simon Glass , Tuomas Tynkkynen , Sam Protsenko , Dirk Eibach , Mario Six , Michael Walle , Simon Guinot , Konstantin Porotchkin , Jason Cooper , =?utf-8?q?Marek_Beh=C3=BAn?= Date: Mon, 7 May 2018 14:40:26 +0530 Message-Id: <20180507091026.24634-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 6/6] spi: kirkwood: Full dm conversion X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" kirkwood now support dt along with platform data, respective boards need to switch into dm for the same. Signed-off-by: Jagan Teki --- Changes for v3: - rebased master - Move kconfig option if DM_SPI drivers/spi/Kconfig | 12 +- drivers/spi/kirkwood_spi.c | 240 ++++++-------------------------- include/dm/platform_data/spi_kirkwood.h | 15 ++ 3 files changed, 62 insertions(+), 205 deletions(-) create mode 100644 include/dm/platform_data/spi_kirkwood.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 73dd33f716..64567cf6e9 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -105,6 +105,12 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config KIRKWOOD_SPI + bool "Marvell Kirkwood SPI Driver" + help + Enable support for SPI on various Marvell SoCs, such as + Kirkwood and Armada 375. + config MPC8XXX_SPI bool "MPC8XXX SPI Driver" help @@ -283,12 +289,6 @@ config SH_QSPI Enable the Renesas Quad SPI controller driver. This driver can be used on Renesas SoCs. -config KIRKWOOD_SPI - bool "Marvell Kirkwood SPI Driver" - help - Enable support for SPI on various Marvell SoCs, such as - Kirkwood and Armada 375. - config LPC32XX_SSP bool "LPC32XX SPI Driver" help diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 4850a2b955..3b65b9221b 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -14,31 +14,41 @@ #include #include #include -#ifdef CONFIG_KIRKWOOD -#include -#endif #include -static void _spi_cs_activate(struct kwspi_registers *reg) +#include + +struct mvebu_spi_dev { + bool is_errata_50mhz_ac; +}; + +struct mvebu_spi_priv { + struct kwspi_registers *spireg; +}; + +static void spi_cs_activate(struct kwspi_registers *reg) { setbits_le32(®->ctrl, KWSPI_CSN_ACT); } -static void _spi_cs_deactivate(struct kwspi_registers *reg) +static void spi_cs_deactivate(struct kwspi_registers *reg) { clrbits_le32(®->ctrl, KWSPI_CSN_ACT); } -static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { + struct udevice *bus = dev->parent; + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; unsigned int tmpdout, tmpdin; int tm, isread = 0; - debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen); + debug("%s: dout %p din %p bitlen %u\n", __func__, dout, din, bitlen); if (flags & SPI_XFER_BEGIN) - _spi_cs_activate(reg); + spi_cs_activate(reg); /* * handle data in 8-bit chunks @@ -56,8 +66,8 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ); writel(tmpdout, ®->dout); /* Write the data out */ - debug("*** spi_xfer: ... %08x written, bitlen %d\n", - tmpdout, bitlen); + debug("%s: ... %08x written, bitlen %d\n", + __func__, tmpdout, bitlen); /* * Wait for SPI transmit to get out @@ -68,8 +78,8 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) { isread = 1; tmpdin = readl(®->din); - debug("spi_xfer: din %p..%08x read\n", - din, tmpdin); + debug("%s: din %p..%08x read\n", + __func__, din, tmpdin); if (din) { *((u8 *)din) = (u8)tmpdin; @@ -83,179 +93,17 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, break; } if (tm >= KWSPI_TIMEOUT) - printf("*** spi_xfer: Time out during SPI transfer\n"); + printf("%s: Time out during SPI transfer\n", __func__); debug("loopend bitlen %d\n", bitlen); } if (flags & SPI_XFER_END) - _spi_cs_deactivate(reg); + spi_cs_deactivate(reg); return 0; } -#ifndef CONFIG_DM_SPI - -static struct kwspi_registers *spireg = - (struct kwspi_registers *)MVEBU_SPI_BASE; - -#ifdef CONFIG_KIRKWOOD -static u32 cs_spi_mpp_back[2]; -#endif - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct spi_slave *slave; - u32 data; -#ifdef CONFIG_KIRKWOOD - static const u32 kwspi_mpp_config[2][2] = { - { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ - { MPP7_SPI_SCn, 0 } /* if cs != 0 */ - }; -#endif - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - slave = spi_alloc_slave_base(bus, cs); - if (!slave) - return NULL; - - writel(KWSPI_SMEMRDY, &spireg->ctrl); - - /* calculate spi clock prescaller using max_hz */ - data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10; - data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data; - data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data; - - /* program spi clock prescaller using max_hz */ - writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg); - debug("data = 0x%08x\n", data); - - writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause); - writel(KWSPI_IRQMASK, &spireg->irq_mask); - -#ifdef CONFIG_KIRKWOOD - /* program mpp registers to select SPI_CSn */ - kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); -#endif - - return slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ -#ifdef CONFIG_KIRKWOOD - kirkwood_mpp_conf(cs_spi_mpp_back, NULL); -#endif - free(slave); -} - -#if defined(CONFIG_SYS_KW_SPI_MPP) -u32 spi_mpp_backup[4]; -#endif - -__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave) -{ - return 0; -} - -int spi_claim_bus(struct spi_slave *slave) -{ -#if defined(CONFIG_SYS_KW_SPI_MPP) - u32 config; - u32 spi_mpp_config[4]; - - config = CONFIG_SYS_KW_SPI_MPP; - - if (config & MOSI_MPP6) - spi_mpp_config[0] = MPP6_SPI_MOSI; - else - spi_mpp_config[0] = MPP1_SPI_MOSI; - - if (config & SCK_MPP10) - spi_mpp_config[1] = MPP10_SPI_SCK; - else - spi_mpp_config[1] = MPP2_SPI_SCK; - - if (config & MISO_MPP11) - spi_mpp_config[2] = MPP11_SPI_MISO; - else - spi_mpp_config[2] = MPP3_SPI_MISO; - - spi_mpp_config[3] = 0; - spi_mpp_backup[3] = 0; - - /* set new spi mpp and save current mpp config */ - kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup); -#endif - - return board_spi_claim_bus(slave); -} - -__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave) -{ -} - -void spi_release_bus(struct spi_slave *slave) -{ -#if defined(CONFIG_SYS_KW_SPI_MPP) - kirkwood_mpp_conf(spi_mpp_backup, NULL); -#endif - - board_spi_release_bus(slave); -} - -#ifndef CONFIG_SPI_CS_IS_VALID -/* - * you can define this function board specific - * define above CONFIG in board specific config file and - * provide the function in board specific src file - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && (cs == 0 || cs == 1); -} -#endif - -void spi_init(void) -{ -} - -void spi_cs_activate(struct spi_slave *slave) -{ - _spi_cs_activate(spireg); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - _spi_cs_deactivate(spireg); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - return _spi_xfer(spireg, bitlen, dout, din, flags); -} - -#else - -/* Here now the DM part */ - -struct mvebu_spi_dev { - bool is_errata_50mhz_ac; -}; - -struct mvebu_spi_platdata { - struct kwspi_registers *spireg; - bool is_errata_50mhz_ac; -}; - -struct mvebu_spi_priv { - struct kwspi_registers *spireg; -}; - static int mvebu_spi_set_speed(struct udevice *bus, uint hz) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); @@ -330,15 +178,6 @@ static int mvebu_spi_set_mode(struct udevice *bus, uint mode) return 0; } -static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct udevice *bus = dev->parent; - struct mvebu_spi_platdata *plat = dev_get_platdata(bus); - - return _spi_xfer(plat->spireg, bitlen, dout, din, flags); -} - static int mvebu_spi_claim_bus(struct udevice *dev) { struct udevice *bus = dev->parent; @@ -352,6 +191,17 @@ static int mvebu_spi_claim_bus(struct udevice *dev) return 0; } +static const struct dm_spi_ops mvebu_spi_ops = { + .claim_bus = mvebu_spi_claim_bus, + .xfer = mvebu_spi_xfer, + .set_speed = mvebu_spi_set_speed, + .set_mode = mvebu_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + static int mvebu_spi_probe(struct udevice *bus) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); @@ -364,6 +214,7 @@ static int mvebu_spi_probe(struct udevice *bus) return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); @@ -376,17 +227,6 @@ static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) return 0; } -static const struct dm_spi_ops mvebu_spi_ops = { - .claim_bus = mvebu_spi_claim_bus, - .xfer = mvebu_spi_xfer, - .set_speed = mvebu_spi_set_speed, - .set_mode = mvebu_spi_set_mode, - /* - * cs_info is not needed, since we require all chip selects to be - * in the device tree explicitly - */ -}; - static const struct mvebu_spi_dev armada_xp_spi_dev_data = { .is_errata_50mhz_ac = false, }; @@ -414,15 +254,17 @@ static const struct udevice_id mvebu_spi_ids[] = { }, { } }; +#endif U_BOOT_DRIVER(mvebu_spi) = { .name = "mvebu_spi", .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) .of_match = mvebu_spi_ids, - .ops = &mvebu_spi_ops, .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata), +#endif + .ops = &mvebu_spi_ops, .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv), .probe = mvebu_spi_probe, }; -#endif diff --git a/include/dm/platform_data/spi_kirkwood.h b/include/dm/platform_data/spi_kirkwood.h new file mode 100644 index 0000000000..ae9b2783a9 --- /dev/null +++ b/include/dm/platform_data/spi_kirkwood.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2018 Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_kirkwood_h +#define __spi_kirkwood_h + +struct mvebu_spi_platdata { + struct kwspi_registers *spireg; + bool is_errata_50mhz_ac; +}; + +#endif /* __spi_kirkwood_h */