From patchwork Sat May 5 23:35:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909214 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="aEISTxMM"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlg60LSwz9s27 for ; Sun, 6 May 2018 09:37:53 +1000 (AEST) Received: from localhost ([::1]:40262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6kR-0003ok-AY for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:37:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54210) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6jb-0003mw-2h for qemu-devel@nongnu.org; Sat, 05 May 2018 19:36:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6ja-0003Yg-5H for qemu-devel@nongnu.org; Sat, 05 May 2018 19:36:59 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:41311) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6jZ-0003YO-Vo for qemu-devel@nongnu.org; Sat, 05 May 2018 19:36:58 -0400 Received: by mail-pg0-x244.google.com with SMTP id m21-v6so17783729pgv.8 for ; Sat, 05 May 2018 16:36:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OngeG9zwMCIUVE3XOPyxbGd7ZZ/+IUjZcODr+WOrT8s=; b=aEISTxMMZheTE7OCwjbKX0O6kzmx0au055TZ5uQhwOMrbXaV8JSdGhJbfYYagEQEHh Nb3ydjicUEPWOhbxFgifsDIllaRg3EPn1veFWFvgJGDPH0R/dV3A90s7LRE9z7P+bNwy b2vzgerVWHMHMJzQX4cITPW2t00wn8LfgsHPl2MiMwG0YT1dx3Wj3xbvnoCLEojcsABW kCXxeSAmWWBJ6p+HDvj7rEGLxGu9+mUlu0R4nX1GAAzxQjqHihzORwz9LwKLbsiHAJzE s7xl4e1Ji6YygA8Mqpd99hMTr213ae1hrHsi1o1t7pMa1JghLXAKrkISPhlPbQFavltq hwIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OngeG9zwMCIUVE3XOPyxbGd7ZZ/+IUjZcODr+WOrT8s=; b=T8wTdBGZAG4sNVg8ZBHTWVu+XpIzXRtNYk2dVszck8cj6ue9KQUY4ZUHvI/a69Ueda RDMWMtiJv3hcPdcw0J3XKp7SUs5m7DruEdAuVGwwQ3PEqlrscqD8wmkTLtZX3Q4sI+O1 UARHL/IGjY+0ZiohE3UvntQC905UcQoRWOasYas1v9Ihe5OJuvAnwwCuxnSiajjQRRR9 FOSrR7QfIl1cOoPJOCnUXRMvcrah+61CXdF2Bd3ASSJ5gxZ2aWVGs+G0ehPvg4ch8xHN yQAQHKndeVz8dw83SyX/aL8vrUV+IPBXZa7JmGY8fAolMFbEVKgI3V0g0vAA8bjq7OPF qH4Q== X-Gm-Message-State: ALQs6tAI5F5RoNuL6mlQRg4i5C6ChxwxzQU+XsZOCD2Pe9M+dwaSHXk1 yra47/qY1ODMZi36ojDvE1wewuD2uRQ= X-Google-Smtp-Source: AB8JxZrRus9BWaNMfR9gCq26OuzZ5x0npWfrj8SkJqAAhqmuwCygUG0PDovy8tL1lZY6ga5rvWiF3g== X-Received: by 2002:a17:902:2804:: with SMTP id e4-v6mr32908821plb.153.1525563417005; Sat, 05 May 2018 16:36:57 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.36.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:36:56 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:07 +1200 Message-Id: <1525563325-62963-3-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2480dad11f08..df06fc720755 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -407,7 +407,7 @@ static const TypeInfo riscv_virt_board_device = { static void riscv_virt_board_machine_init(MachineClass *mc) { - mc->desc = "RISC-V VirtIO Board (Privileged spec v1.10)"; + mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)"; mc->init = riscv_virt_board_init; mc->max_cpus = 8; /* hardcoded limit in BBL */ } From patchwork Sat May 5 23:35:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909215 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="ZuE8rLdE"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlkK6rDZz9s27 for ; Sun, 6 May 2018 09:40:41 +1000 (AEST) Received: from localhost ([::1]:40272 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6n9-00069a-Gr for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:40:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54228) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6je-0003pK-Ia for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6jd-0003Zy-Ni for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:02 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:37840) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6jd-0003Zo-Ho for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:01 -0400 Received: by mail-pg0-x243.google.com with SMTP id a13-v6so17785781pgu.4 for ; Sat, 05 May 2018 16:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=USSSK7S/Vpn9QRZZXmOnn9vRr0DRKPNDSFTBR54D4AM=; b=ZuE8rLdE79hK5+gdxOr4ntaaK3CjpxOxW2NWmVZ+gPr/DhpEDoiE0istG3WvXDL7yD z2We0SfZYIxik0dFfmobNzJLL/jygBZASkpTF5ZjX85E6TNmdlXkhAF+qwwlS4S2a85K mMJEmxVw5myqw2ZrHQvb+ZwR12Qyw0LjyHQKYSRcMLVzIqoiAsNLZbac4squT3tALGSJ Ug3B999gXvhUMZ2u0/vQeBjiUZOEDmtfjjoziDFKzK5uW5y94jLEKvKq9ksqL6lSY5RQ Vluv0cV734icfxaCBgSpFp4ULVG9IaeLKZbUs9M/9Qtd5681216R/m8cQeFSo/bVHftC KaZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=USSSK7S/Vpn9QRZZXmOnn9vRr0DRKPNDSFTBR54D4AM=; b=HBpprdIZ3cvAH7GnmIXfPFCGiJ77IDGJNQVpH47oniuzK8b80Gpn69WQujX1hjLqyu hEOGDiaKN+IWZ91fymDYQdOOcQ6dMxQSj1hXTEGmhz4n854OimDuAvvB+eIfn1rG78rh wJuboMGYJjNyj77zuAX2nf30MX47kOf1vvV8BWuiy556gjgCd9PNvRNaImDUQt9XabDN jXp+qhhGLKHFzfj/oVDUFFP7/5J3dOnV6POWYdKunnYruKFOeyNHIVaSyqMMuk6F+WeW PZuWoy7O3xX9WW3tUYTIHNgbGMso0GDYROXNpdwh5YS/TNXObel7JlfryHE/4LMif5kG HIwA== X-Gm-Message-State: ALQs6tC5lLXH9h8ihRDvDyUkKkWWj8F09Vr5pakJul5tOt/oWVTV5jvz D3WZuq/OV/xLCAkCzaC0ZhnNHLRpg1Q= X-Google-Smtp-Source: AB8JxZqdOE011BnJmowukKNa3DodGMk6fdwuVS/OayZOscPk8OzjODrM/Wt1P9PQwhU8V6FW+ad3/g== X-Received: by 2002:a65:44cc:: with SMTP id g12-v6mr26140850pgs.110.1525563420512; Sat, 05 May 2018 16:37:00 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.36.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:00 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:08 +1200 Message-Id: <1525563325-62963-4-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 4 ++-- include/hw/riscv/virt.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index df06fc720755..3cc9c8090bfb 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -341,11 +341,11 @@ static void riscv_virt_board_init(MachineState *machine) }; /* copy in the reset vector */ - copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec)); + copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)); /* copy in the device tree */ qemu_fdt_dumpdtb(s->fdt, s->fdt_size); - cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec), + cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); /* create PLIC hart topology configuration string */ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 2fbe808da5f6..655e85ddbd3c 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -23,8 +23,6 @@ #define VIRT(obj) \ OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) -enum { ROM_BASE = 0x1000 }; - typedef struct { /*< private >*/ SysBusDevice parent_obj; From patchwork Sat May 5 23:35:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909217 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="fSxQ0ZeR"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlkQ42wQz9s2k for ; Sun, 6 May 2018 09:40:46 +1000 (AEST) Received: from localhost ([::1]:40273 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6nE-0006Cz-4L for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:40:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6jj-0003ru-IM for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6jg-0003ay-TK for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:07 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36607) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6jg-0003ah-Nm for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:04 -0400 Received: by mail-pg0-x242.google.com with SMTP id z129-v6so13605838pgz.3 for ; Sat, 05 May 2018 16:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DeouxeLzQKj/gPyu8YlTJo/W0FtOGv/F5LWE1yLn8uE=; b=fSxQ0ZeRxHU2sEStDBhIAKoIin/cAjJgLqQ4rqMIIPs6FQT+BMDRBvhqiTkkj2Bmul pKbxR47QJXW8mhjyZzPuwOueh93cX03t5lSRVPDdAPqYSFvdqqdxOt6qDoctdcCXJCdP Nhk/YwNwgkynRTz9Pn4hSDzIm8t1MpRyXNyMA//uX1a326LXHDQmPY0nM8u8jC/UiZWV AHd4jarg3dK6N+Zr6VQseIwE5wchPoXW0Gr5LyllzBJsPo7FF/78HoFGM6si4O933XKk 73TfP6Q/3kM0mxmSN14+x319m3NE6Y/ZpTzBlu7oC6AN6n4kWg8wkHVSDYVD6FY/Z3xs dkwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DeouxeLzQKj/gPyu8YlTJo/W0FtOGv/F5LWE1yLn8uE=; b=P3mRI1UDIZyU913HpCURnP0aQGrnTzUIGihW/7D6JQ8f2XU5b5HcB+0NBXUTTf4jT6 XkUOAOz+zQecdc3bdU6z03Dg5W+hTdRXsoUpuLBSh+4eOzO3eercfTvq92u751Yjskdo D5L8O+3VL7vG2ac/hcLARVeEQ5hYbXQenX00cDp2/GLrBa/9Zd5J8oPgrrTx8ogluegv HfeLqWiZ0R4SdZM79hF+AME3BhSFyGQu9rTIeHsQpgsBumKSxkeuJORvO6XeTtOjQ1uq ybnEtxb1Bqn9Gc+FV6HZCIuqgHucqbIWqMdTyitOHvSf8nGlv+e3dd/iU81DgCHGQbR8 ZxjA== X-Gm-Message-State: ALQs6tD2pAmiURVHbMAF5K3Y+NVlY5jdVBr/UkfnTUzuX3prmldhAnkT 1DFjzu1rYdypesV0b/OXiH5pJiojWSU= X-Google-Smtp-Source: AB8JxZrKCr70dVVzjD+X0u8mJUF0iQ4fdGkaXBjN6F+4ERmnYDKDA189OGCUJkv9dgbH1ME4dJVILw== X-Received: by 2002:a63:aa01:: with SMTP id e1-v6mr26220921pgf.331.1525563423665; Sat, 05 May 2018 16:37:03 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:03 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:09 +1200 Message-Id: <1525563325-62963-5-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When load_elf is called with NULL as an argument to the address translate callback, it does an identity translation. This commit removes the redundant identity_translate callback. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 7 +------ hw/riscv/sifive_u.c | 7 +------ hw/riscv/spike.c | 7 +------ hw/riscv/virt.c | 7 +------ 4 files changed, 4 insertions(+), 24 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 487244890ef8..3e523a073469 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -82,16 +82,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) } } -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1bd2bde9b871..adc6c2266275 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -68,16 +68,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) } } -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ae82f4eb6341..cf7f9bcc3950 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -59,16 +59,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) } } -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; - if (load_elf_ram_sym(kernel_filename, identity_translate, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3cc9c8090bfb..c2aa795981d2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -62,16 +62,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) } } -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); From patchwork Sat May 5 23:35:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909218 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; 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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:07 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:10 +1200 Message-Id: <1525563325-62963-6-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/riscv_hart.c | 6 ------ hw/riscv/sifive_e.c | 25 ------------------------- hw/riscv/sifive_u.c | 25 ------------------------- hw/riscv/spike.c | 20 -------------------- hw/riscv/virt.c | 25 ------------------------- include/hw/riscv/sifive_e.h | 5 ----- include/hw/riscv/sifive_u.h | 5 ----- include/hw/riscv/spike.h | 7 ------- include/hw/riscv/virt.h | 5 ----- 9 files changed, 123 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 14e3c186fea7..75ba7ed579bd 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -68,16 +68,10 @@ static void riscv_harts_class_init(ObjectClass *klass, void *data) dc->realize = riscv_harts_realize; } -static void riscv_harts_init(Object *obj) -{ - /* RISCVHartArrayState *s = SIFIVE_COREPLEX(obj); */ -} - static const TypeInfo riscv_harts_info = { .name = TYPE_RISCV_HART_ARRAY, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(RISCVHartArrayState), - .instance_init = riscv_harts_init, .class_init = riscv_harts_class_init, }; diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e523a073469..22dc526713c2 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine) } } -static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = riscv_sifive_e_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_e_device = { - .name = TYPE_SIFIVE_E, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SiFiveEState), - .class_init = riscv_sifive_e_class_init, -}; - static void riscv_sifive_e_machine_init(MachineClass *mc) { mc->desc = "RISC-V Board compatible with SiFive E SDK"; @@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) } DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) - -static void riscv_sifive_e_register_types(void) -{ - type_register_static(&riscv_sifive_e_device); -} - -type_init(riscv_sifive_e_register_types); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index adc6c2266275..5bb495ab9a6c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -301,31 +301,6 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } -static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_u_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = riscv_sifive_u_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_u_device = { - .name = TYPE_SIFIVE_U, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SiFiveUState), - .class_init = riscv_sifive_u_class_init, -}; - -static void riscv_sifive_u_register_types(void) -{ - type_register_static(&riscv_sifive_u_device); -} - -type_init(riscv_sifive_u_register_types); - static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc = "RISC-V Board compatible with SiFive U SDK"; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index cf7f9bcc3950..44eab94e17ef 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -334,18 +334,6 @@ static void spike_v1_09_1_board_init(MachineState *machine) smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } -static const TypeInfo spike_v_1_09_1_device = { - .name = TYPE_RISCV_SPIKE_V1_09_1_BOARD, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SpikeState), -}; - -static const TypeInfo spike_v_1_10_0_device = { - .name = TYPE_RISCV_SPIKE_V1_10_0_BOARD, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SpikeState), -}; - static void spike_v1_09_1_machine_init(MachineClass *mc) { mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)"; @@ -363,11 +351,3 @@ static void spike_v1_10_0_machine_init(MachineClass *mc) DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) - -static void riscv_spike_board_register_types(void) -{ - type_register_static(&spike_v_1_09_1_device); - type_register_static(&spike_v_1_10_0_device); -} - -type_init(riscv_spike_board_register_types); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c2aa795981d2..88b9ad509315 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -382,24 +382,6 @@ static void riscv_virt_board_init(MachineState *machine) serial_hd(0), DEVICE_LITTLE_ENDIAN); } -static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_virt_board_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = riscv_virt_board_sysbus_device_init; -} - -static const TypeInfo riscv_virt_board_device = { - .name = TYPE_RISCV_VIRT_BOARD, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(RISCVVirtState), - .class_init = riscv_virt_board_class_init, -}; - static void riscv_virt_board_machine_init(MachineClass *mc) { mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)"; @@ -408,10 +390,3 @@ static void riscv_virt_board_machine_init(MachineClass *mc) } DEFINE_MACHINE("virt", riscv_virt_board_machine_init) - -static void riscv_virt_board_register_types(void) -{ - type_register_static(&riscv_virt_board_device); -} - -type_init(riscv_virt_board_register_types); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 0aebc576c1d5..12ad6d2ebb2b 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H -#define TYPE_SIFIVE_E "riscv.sifive_e" - -#define SIFIVE_E(obj) \ - OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) - typedef struct SiFiveEState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be38aa09da20..94a390566e59 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H -#define TYPE_SIFIVE_U "riscv.sifive_u" - -#define SIFIVE_U(obj) \ - OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) - typedef struct SiFiveUState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index d85a64e33d86..8410430614b7 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -19,12 +19,6 @@ #ifndef HW_SPIKE_H #define HW_SPIKE_H -#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" -#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" - -#define SPIKE(obj) \ - OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -35,7 +29,6 @@ typedef struct { int fdt_size; } SpikeState; - enum { SPIKE_MROM, SPIKE_CLINT, diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 655e85ddbd3c..b91a4125dd61 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,6 @@ #ifndef HW_VIRT_H #define HW_VIRT_H -#define TYPE_RISCV_VIRT_BOARD "riscv.virt" -#define VIRT(obj) \ - OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -45,7 +41,6 @@ enum { VIRT_DRAM }; - enum { UART0_IRQ = 10, VIRTIO_IRQ = 1, /* 1 to 8 */ From patchwork Sat May 5 23:35:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909219 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; 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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:10 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:11 +1200 Message-Id: <1525563325-62963-7-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- disas/riscv.c | 39 ++++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 74ad16eacdd3..2cecf0d8558d 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2769,25 +2769,6 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) char tmp[64]; const char *fmt; - if (dec->op == rv_op_illegal) { - size_t len = inst_length(dec->inst); - switch (len) { - case 2: - snprintf(buf, buflen, "(0x%04" PRIx64 ")", dec->inst); - break; - case 4: - snprintf(buf, buflen, "(0x%08" PRIx64 ")", dec->inst); - break; - case 6: - snprintf(buf, buflen, "(0x%012" PRIx64 ")", dec->inst); - break; - default: - snprintf(buf, buflen, "(0x%016" PRIx64 ")", dec->inst); - break; - } - return; - } - fmt = opcode_data[dec->op].format; while (*fmt) { switch (*fmt) { @@ -3004,6 +2985,11 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst) format_inst(buf, buflen, 16, &dec); } +#define INST_FMT_2 "%04" PRIx64 " " +#define INST_FMT_4 "%08" PRIx64 " " +#define INST_FMT_6 "%012" PRIx64 " " +#define INST_FMT_8 "%016" PRIx64 " " + static int print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) { @@ -3031,6 +3017,21 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) } } + switch (len) { + case 2: + (*info->fprintf_func)(info->stream, INST_FMT_2, inst); + break; + case 4: + (*info->fprintf_func)(info->stream, INST_FMT_4, inst); + break; + case 6: + (*info->fprintf_func)(info->stream, INST_FMT_6, inst); + break; + default: + (*info->fprintf_func)(info->stream, INST_FMT_8, inst); + break; + } + disasm_inst(buf, sizeof(buf), isa, memaddr, inst); (*info->fprintf_func)(info->stream, "%s", buf); From patchwork Sat May 5 23:35:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909224 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:13 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:12 +1200 Message-Id: <1525563325-62963-8-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This fixes an issue when disassembling rv128 c.sqsp, where the code erroneously fell through to c.swsp. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Cc: Peter Maydell Signed-off-by: Michael Clark Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- disas/riscv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 2cecf0d8558d..7fd1019623ee 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) if (isa == rv128) { op = rv_op_c_sqsp; } else { - op = rv_op_c_fsdsp; break; + op = rv_op_c_fsdsp; } + break; case 6: op = rv_op_c_swsp; break; case 7: if (isa == rv32) { From patchwork Sat May 5 23:35:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909221 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="Xe0YLsZQ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlnW0lRkz9s27 for ; Sun, 6 May 2018 09:43:25 +1000 (AEST) Received: from localhost ([::1]:40291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6pm-00005k-Cp for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:43:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54314) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6jv-00043h-Jx for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6ju-0003l1-Ot for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:19 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:39484) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6ju-0003jP-K3 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:18 -0400 Received: by mail-pf0-x241.google.com with SMTP id a22so5989475pfn.6 for ; Sat, 05 May 2018 16:37:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KaX5zIkc3PWlyLzMOtemVjE9YiFvpXwvSH0oDPH16zY=; b=Xe0YLsZQcSsULt44O1pDA2hM+htCqF6Xhfid0AEptAQQMhF4Nk97ordUI6V82FwYht FdZPYWVAUS02iNRrAZBfMLsCxxsGqDUjpL4aMxgLp2RmZI9CL3bqEpi1V35AX+lx8vY3 3FxoroAWrAKTnaqftyPEZXyys5DcEi3+P5rY3WIhNrwVcjVLGiGKHqbvFhCaKCFjKQqJ sAbVSDNzR+15qEdokbnFUcPSGEa7t62MkM7hjP+3Fgltwf8UDOKjf4JpzIE4YCw1meIY JUlXebevtaRmsUwaKX4qGp8x7PTpqj++2uozGyYLjD4Uu5W/g502mvKt74/hJHt1Rs25 TuIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KaX5zIkc3PWlyLzMOtemVjE9YiFvpXwvSH0oDPH16zY=; b=Dvfu5MH8ttBfhaTSWUPaouX3uj4wv1gtDVH7T9G0hyfVyYkEqm4bu3AFuWHhBI5j9i ypKc8h6PBCorqt5muxm1nn3cONYRbxnHPq37n0YA6FNaX0PqHthOIMs8fcJ3NShdvbKR PaI7bgIF4+i77e1qgc2rYcK7qs7tacERP6T4/Ac7QvxhStpEM8oR3eCzm10Sm6ukOXU+ M9N8YcZVEzqeLChyPz59vBuJXZ1xoWXZzubjhhJ2LJxGh+6hHIloG4aHcalVjt5nYt6e /weugbY5f0pVSvpVNjEhnoNKzKtlKNPaWjxr/vAk/JcIw9QV/UzK62eQ6VcVNoBh8SK6 VEqw== X-Gm-Message-State: ALQs6tAPKYfLfKHSnWB+AY02h7dvSWZRiizwbbyDz+SAIsK3op6GKMN1 FDXH+OMrz+uCfsH9v0tXJrmbTdQ/YQs= X-Google-Smtp-Source: AB8JxZowde237CXtBOy7pw8VbdgA0gIzAH8U82sTdze+/U+Xzssrkvbnl3ScHHVT/19Wpk3nTgeM4Q== X-Received: by 2002:a17:902:780d:: with SMTP id p13-v6mr33140284pll.281.1525563437612; Sat, 05 May 2018 16:37:17 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:17 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:13 +1200 Message-Id: <1525563325-62963-9-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- include/hw/riscv/spike.h | 4 ++-- include/hw/riscv/virt.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 8410430614b7..641b70da67b6 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -16,8 +16,8 @@ * this program. If not, see . */ -#ifndef HW_SPIKE_H -#define HW_SPIKE_H +#ifndef HW_RISCV_SPIKE_H +#define HW_RISCV_SPIKE_H typedef struct { /*< private >*/ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b91a4125dd61..3a4f23e8d075 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -16,8 +16,8 @@ * this program. If not, see . */ -#ifndef HW_VIRT_H -#define HW_VIRT_H +#ifndef HW_RISCV_VIRT_H +#define HW_RISCV_VIRT_H typedef struct { /*< private >*/ From patchwork Sat May 5 23:35:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909227 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="HeplD3hW"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlwV4S9Sz9s27 for ; Sun, 6 May 2018 09:49:29 +1000 (AEST) Received: from localhost ([::1]:40322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6ve-0004rv-03 for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:49:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6jy-00046n-JP for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6jx-0003n5-U3 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:22 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:37614) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6jx-0003mp-O1 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:21 -0400 Received: by mail-pf0-x244.google.com with SMTP id e9so16092985pfi.4 for ; Sat, 05 May 2018 16:37:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8fsGHMk0fIshZzzNQctqgg504LWzDo5Afrw8at/TATY=; b=HeplD3hWsKxjlmd/aLAa05fzpf87xB2Zh9Tuykpp4QMS+ZGT01DMyrmBU5rFkgLPKR srwVQd6Ad5rG3gm7Cu+WMhK3LtJrs2yq/h9lPJdSTsuUNqg+aMmXCBFFfNItOaRYt5LB oRsExZ/wBE1favoFNiPBhllClCtCH8jPWkgMOLA/TP/aFaD3ADjWSbuDyMBdJMjwi0DN xSazyJg8Umbo7ovlI5/T4ohjZAbyfQm0pjADwVUhpSghvIvl5uY5PuMH6g+iwLjkTkOI XpFOA8VvIXe9+nbDGJY6Z/bWJ7116L+SlV7FggDO1RNamJx170OEXpIuroR5TqvAeqo+ AarQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8fsGHMk0fIshZzzNQctqgg504LWzDo5Afrw8at/TATY=; b=Z0LnnyUay7tUJup+CodtgAQ9/yGIs1SMj/rcM2UW9Z3ROuOnq8gwhyvsIDavLRFA2H D9/IovLU0CnhfFGVjrZuuIFa4o/l68fBUxMlns4XOHCw48mBDay8h6R+fb0Y70ot3GJb JHsOdy3MXbdcTSqo3Oy/G8e7eEtGFtBpqe5v9U0g9XzfhuyOb6wBo84u57XjECvELRvN ZV+nPHlha8otjZUhT2ujhgOtQCNKOS4pwsDpG0TwcrL3zg+vf9BGsk35DkxBkjN/oWK2 1SmpbTTSQfADp27AISBbo/v0cWxoJlO4+e+fzXQ8DRgz5wBQe3z+PY+ue0VXT7gTvUOC godA== X-Gm-Message-State: ALQs6tDBU+uZgrA9X0Yz5ohvfSHZ+JHPoIaxbTaTg/FlCrOlPeMTr1q8 q1BZ74T3KNBfcYcOGsA2G85Kxtbc1LQ= X-Google-Smtp-Source: AB8JxZqkCC+RQEZlOmfsWPTPjcYfA1EOP3MPOYcjolwNHepz1KJRQfIMJsnyK4AR06NluzGXOd8PyA== X-Received: by 10.98.152.203 with SMTP id d72mr31713311pfk.98.1525563440758; Sat, 05 May 2018 16:37:20 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:20 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:14 +1200 Message-Id: <1525563325-62963-10-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- include/hw/riscv/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 3a4f23e8d075..91163d6cbfe8 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -1,5 +1,5 @@ /* - * SiFive VirtIO Board + * QEMU RISC-V VirtIO machine interface * * Copyright (c) 2017 SiFive, Inc. * From patchwork Sat May 5 23:35:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909230 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="MfixepKE"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlz41CMxz9s27 for ; Sun, 6 May 2018 09:51:44 +1000 (AEST) Received: from localhost ([::1]:40337 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6xp-0006lz-QG for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:51:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54373) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6k5-0004D6-0M for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6k1-0003oe-6g for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:29 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:39477) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6k1-0003oI-1J for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:25 -0400 Received: by mail-pg0-x242.google.com with SMTP id e1-v6so6431881pga.6 for ; Sat, 05 May 2018 16:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X5Czuf6eX+C7jbQh4er/CRRjA+HddOHaco2dXcG6wog=; b=MfixepKEZ0owFCVfrg2OODZD9H0ErOfzaWWfGmwDtiHch6wNUIYEpE2nbcWrUbnIf1 Ll2pim/IZkm8+Hw7EmhLLxiVPSV4QQqejyjUnDX39DY38m5ujwJ0+TlsLRj2MgWAig4/ jzPV2OLckvWn4L8YR3eu0MCRKiK0dCLd6kKflHt5BmGsO3EXiKoqBLwzryEasbhmY7R1 zXyuXU7bxsOTk0O3BoOOU8iu6ZFtr7m3GnkJ3ZVr3wKMVjZT2np1fU2J6txkF7Taw5Hw 6APBsbnxmUW3Yrm1zD9wok/0WKPjDlXNm9ZE/PuJ0QO5InQKddytdyDvgqKem5xzii4d V6GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X5Czuf6eX+C7jbQh4er/CRRjA+HddOHaco2dXcG6wog=; b=ucZ+RBMUfZkWfDFLlhhz1u/7P5OK6h9O70Rbfu0EG0Vm8+aVhahAbZsNmky/yqSNSF 6AxH0XwcMS6p0jMZzmHJGPvkLEXf5upAy0VrhkYqPF2vvu/NgH+TqJxHzqWTR5Z1b48X R4T3c4lQgDgRdQlYQfppD9fj9lZWLTC6kh411TeallDve58ZDDaoIfCWdWj/oMt+aqeO RQ4l3FBrlIrk0y3KQb62FoUxHLJvJFiCx2FGnp4iZye3Nu2NQsmKQUtRK5H51mEHfC1n ZpXkNU2OuQR3Z9bTSIY+79ux3eZ0St5YZuhQ1ZyVwEM9fjd9YdpVcrai66a6KnldMGYr zW7w== X-Gm-Message-State: ALQs6tDZ0YRr/Kn8MrxaoCGj1mxriLso0+cKRW72iihJPLfmqm8CLlci r72LEQ/r5IV1/RWmq/IrpHpgpX10DOI= X-Google-Smtp-Source: AB8JxZrm0PWkwE0kzIwF/bKPxxtP6cfc3n3ROY6z6BeE+wbC3Xx4MxHQg1LKDqRsMeauhr2+2szbeg== X-Received: by 2002:a17:902:264:: with SMTP id 91-v6mr32748709plc.341.1525563444148; Sat, 05 May 2018 16:37:24 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:23 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:15 +1200 Message-Id: <1525563325-62963-11-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.h | 1 - 5 files changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 22dc526713c2..6fa223818502 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename) if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5bb495ab9a6c..84afed4c3b0e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename) if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 44eab94e17ef..9e18c618bfbb 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename) uint64_t kernel_entry, kernel_high; if (load_elf_ram_sym(kernel_filename, NULL, NULL, - &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 88b9ad509315..7ef9ba26debc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename) if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 41e06ac0f91d..9871e6feb1de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,7 +34,6 @@ #define TCG_GUEST_DEFAULT_MO 0 -#define ELF_MACHINE EM_RISCV #define CPUArchState struct CPURISCVState #include "qemu-common.h" From patchwork Sat May 5 23:35:16 2018 Content-Type: text/plain; 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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:27 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:16 +1200 Message-Id: <1525563325-62963-12-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- target/riscv/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 808eab7f5080..c3a029afefd9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_gen_andi_tl(source2, source2, 0x1F); tcg_gen_sar_tl(source1, source1, source2); break; - /* fall through to SRA */ #endif case OPC_RISC_SRA: tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); From patchwork Sat May 5 23:35:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909226 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="fXQ7byHE"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlsT3Lnpz9s27 for ; Sun, 6 May 2018 09:46:53 +1000 (AEST) Received: from localhost ([::1]:40314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6t9-0002uM-3W for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:46:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6k9-0004Es-Dt for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6k8-0003sG-F0 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:33 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:43428) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6k8-0003ru-8a for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:32 -0400 Received: by mail-pf0-x243.google.com with SMTP id j20so5775137pff.10 for ; Sat, 05 May 2018 16:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lXTe0rk11UlaoolQNWbqKPLh0sxqHiqOOdSvoY5p97I=; b=fXQ7byHELBOvm8vlrvlZjJx2/mCp8t3/iyKAWgwe+FKplYZ6oCefaRcpNGvtUgRQ1Q sHxcWcKDVbRDc7dhsUk118i7/W8LpHyHogtWnr1lX4zSxbduxaG6hhIaFhxohVPKJLF2 QMoKy/0ZqqtDpx/d4a7FBlWtzedVOOSz5BoxTxKdhI9iQKNvuXwAd3oQZ96OQvSNZHPq 0M+DPEnY6LpVzudRqemrGK6DGTE3mvQzzqZSlOLB2ofKTmfb7r5BIwFOZO/tG84OGtex QXiz3Qfn/MFjG30F8h4qnkFs9EQcZAoxWbHPzU13Sg7zleFLE0lvG/GUvqUYyDE5iugC ESIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lXTe0rk11UlaoolQNWbqKPLh0sxqHiqOOdSvoY5p97I=; b=cvt3LpROMS3DABCqIj/YyHNHReidtEKtZzWZ00MO+o9Nsz64Cox7J9DuDqaLpeJflu 66Tyom5FRkNe5wO0TQKrE5Df3i93bYXRV9L38S0HT7M5YYcfcEgB0qxBnhzxWnv87jFd kkuHzz8pVwH60xMHozZRD4cKy5BEwgAG+a5B7LPJ7RA+Rlk7kOAY0ObTC3okJ0JTrnjC tc6mJilOFEp/OrOsbOdqMWnSlFUqMYFJHmaufGe+KWP6+ijmtYkUn1AdJnj+Ql6D8/8z xlFDwAtIgXsdwMWGXdFXI/rrtGA0bXQCUnLyUX3WZJ6q6iNUpVK3l9wx0ScxHihT/cbR nC+Q== X-Gm-Message-State: ALQs6tBiWv2PswyBJOVHpJQGTpqItp4qiFyt7xuI/Er0tIK8YVIVAjxO 6vgHvEYZX02zp9BqYIW2kKa1poBIksw= X-Google-Smtp-Source: AB8JxZqcGMLppS/4BD1sH/iynwO8MltRA4NNbNq+04ryrJfnIee0EUuu4SmS1LWReo9X9c4i3mtYmw== X-Received: by 10.98.155.87 with SMTP id r84mr31931496pfd.109.1525563451271; Sat, 05 May 2018 16:37:31 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:30 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:17 +1200 Message-Id: <1525563325-62963-13-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a527fbba0bd..4e5a56d4e312 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -26,7 +26,7 @@ /* RISC-V CPU definitions */ -static const char riscv_exts[26] = "IMAFDQECLBJTPVNSUHKORWXYZG"; +static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; const char * const riscv_int_regnames[] = { "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9871e6feb1de..1dcbdbe6f77d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -71,6 +71,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') #define RVA RV('A') #define RVF RV('F') From patchwork Sat May 5 23:35:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909229 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="DrtRiOIK"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlws5wRwz9s27 for ; Sun, 6 May 2018 09:49:49 +1000 (AEST) Received: from localhost ([::1]:40325 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6vz-000596-E5 for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:49:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6kF-0004Ir-SM for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6kB-0003tt-UZ for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:39 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:41312) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6kB-0003tU-P6 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:35 -0400 Received: by mail-pg0-x244.google.com with SMTP id m21-v6so17784204pgv.8 for ; Sat, 05 May 2018 16:37:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wMEwam6BvPsgRK042BgP/NFq1C4V+noOwdp5p8iI2r4=; b=DrtRiOIKjzeKY/vlKFOrLaZHt1hFx8b9LuljLtbL5ZChjmxo5x2fYq92luSh0f0wGs /+bsvh7VTT0z5kuMRddFBlTzQX1bSAJrNfDfHDFp2rAy+zRNcol2Z/oX2D9Pvb/ZzNUI XcGX5YbwYYLdV+xeSdeVEJjUC5RZXJAHEuQiT7pqOKsyboz9pFmXoSeYIU4BCdonWW2y dNQTF22NmTkGcnMijpD+dHieKo2J7tjZp874asUJMkvkjKtJlmS5t2FMuU5O7ggrlcXk htd6jSwi7F7vQpXf/tqNe1wzHFH+aE6yJaPFtmrG4gMfkcUxIzbEQ5N0Qxt7fmOye+Qv 2Vig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wMEwam6BvPsgRK042BgP/NFq1C4V+noOwdp5p8iI2r4=; b=lBpn30Yam3UKPXFnOD8hBJDS5He6R4x3aS8y8L0w5Au/1UbMSnbMEPf/1SjfkgKkBz qnTBSywBYlQM7ItKHC18H320U3PKcikzYbD1iLsgK9QtNZ855V2GUv93EfoiDDkxTCpL NO/MhJ4N4CJ8J7mIiqrMbkFvWpiDR028f2D+D0XOZilzCbD1Fkf2AlxmCpH//VFz/FaB 54asbdMEbAJkijm2lOKjQfazFOWmKYtYmcqAs4zfCO1lUloknauKpsAs0MXSim6fRdrj 2wdLZKlgnckUADgounuZjev2GpZNAx8Ytk3s1F2zkeFwkAnOPQppj93HusndySVzQVrY I7jw== X-Gm-Message-State: ALQs6tA3ER156iR5jmrmxPPwmHTfWUL/UC2pBOAIaXx8N+xC8vUK6pIW tOzFzAu3H38piERtSXNrXPz+qjsU2qU= X-Google-Smtp-Source: AB8JxZoZbeT7sVEHOSK6VZ/0u6TQFNrzjDPTeF+aTAM0uS7sHM0h/KshO7mAnFX/ilNhVzpvgW/XQA== X-Received: by 2002:a63:41c1:: with SMTP id o184-v6mr26215074pga.393.1525563454858; Sat, 05 May 2018 16:37:34 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:34 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:18 +1200 Message-Id: <1525563325-62963-14-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and more complex trap handling code). Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7c6068bac958..101dac1ee8dc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -255,7 +255,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, } case CSR_SATP: /* CSR_SPTBR */ { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { - goto do_illegal; + break; } if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val_to_write ^ env->sptbr)) { @@ -465,7 +465,10 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) return env->scounteren; case CSR_SCAUSE: return env->scause; - case CSR_SPTBR: + case CSR_SATP: /* CSR_SPTBR */ + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + return 0; + } if (env->priv_ver >= PRIV_VERSION_1_10_0) { return env->satp; } else { From patchwork Sat May 5 23:35:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909216 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="m8dkSdty"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlkQ3SCKz9s27 for ; Sun, 6 May 2018 09:40:46 +1000 (AEST) Received: from localhost ([::1]:40274 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6nE-0006DJ-2i for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:40:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54481) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6kG-0004Ji-RW for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6kF-0003w3-FY for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:40 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:42444) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6kF-0003vp-9X for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:39 -0400 Received: by mail-pf0-x242.google.com with SMTP id p14so8709721pfh.9 for ; Sat, 05 May 2018 16:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6on1lJF8B1OcPUw/PwklAPiWkVR7XQhUNtC8ocAc4vg=; b=m8dkSdtypkFUW4FzXU/ZgzvqbL9IjEoM5Gf9fesHGNWfU/FB2UXohAh83GVGqQf+NQ TzTXLCs9JGrMS0OxU84MyAFggTFWYj82ct2zWksMtQ06DYHCMMluPewr+FmGd98zC+5J vBky+dyUfj20W2Y5I5Xa0VtQ0ssmP/MPq4JlwdJx8/2fQeacp5L+pP8DlG2fDtScOlIS ksOJT9KbQxz1Z+Zd/FajYIEuGr1I6EskL7NRs9L+W/hrm8YuvRkc6dFTr5RKTeYLFegh Q/LFy/f5BavEWmRc68fwC5xq2oPCVwWEqCpdwLu9SzZC/EVSELfg///0XibTVY4A1bj2 ABZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6on1lJF8B1OcPUw/PwklAPiWkVR7XQhUNtC8ocAc4vg=; b=qVG1FG57JubOfaaEbP6HIGsIhRJnTzazO2p8DVaMGrftT82JmAg5y9KSQ2bw7gM4wR G/XawMsFlKWB38W6r7qLG/WC7QlqOVV71L+/yyL9/P0hJari9CSPxf2AMD4icja5es2N gXDUfrGZYuMnykVxpumRtRKWxuRg31euBhV5XGVMuWoQWi6RQJRFwJuBt8D120yYwKe5 QiGJcPYfSUMMJanott18pGraWjUCt817vorw1fNUMbC0LHtbY3FgdRSQ91UrJMElomkN 5XnoSTzQXR8rzwtF7H+Y8vL/RQ+3i6o8HZp/HLicCWGclYc3uGRe2G83/RqzMoHpNsoK 9Uew== X-Gm-Message-State: ALQs6tB3ftx/P/u4eXQ61O+cuqXXUYDc77CnK/GBp1WwYkKXXd8rVY4E lhJgwZctF7KFsXc2L9tgh9lT2EKcsrE= X-Google-Smtp-Source: AB8JxZqzNwqAxwa7UZ4tqNz9d2IE4xXJZeh27x3cKw1kF9bRLDyEtdAO6sYHu+ekBQ+acg53eb5Wxg== X-Received: by 2002:a63:aa01:: with SMTP id e1-v6mr26221572pgf.331.1525563458374; Sat, 05 May 2018 16:37:38 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:37 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:19 +1200 Message-Id: <1525563325-62963-15-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- target/riscv/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 02cbcea2b731..95889f23b94d 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -466,6 +466,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); } env->sbadaddr = env->badaddr; + } else { + /* otherwise we must clear sbadaddr/stval + * todo: support populating stval on illegal instructions */ + env->sbadaddr = 0; } target_ulong s = env->mstatus; @@ -487,6 +491,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); } env->mbadaddr = env->badaddr; + } else { + /* otherwise we must clear mbadaddr/mtval + * todo: support populating mtval on illegal instructions */ + env->mbadaddr = 0; } target_ulong s = env->mstatus; From patchwork Sat May 5 23:35:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909223 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="OP7XsU5/"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlrz05Smz9s27 for ; Sun, 6 May 2018 09:46:27 +1000 (AEST) Received: from localhost ([::1]:40312 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6si-0002bh-IN for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:46:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6kK-0004N6-Ec for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6kJ-0003z3-Hm for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:44 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:46609) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6kJ-0003yZ-CI for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:43 -0400 Received: by mail-pf0-x243.google.com with SMTP id p12so20071052pff.13 for ; Sat, 05 May 2018 16:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hzYHz6It3AnWry9x4xd8y7/vHlQd0K6YIrGLt3sNlSw=; b=OP7XsU5/JA7Pcai5TwVbsQgVg1CAfBonq08uyRngXR9X5C44pdV/Qw3pQKq0BkH2TU HJIXixnOgLL1eXU5rs2rT3zlQF7XG0ZVfkQ54x40Iq0AYgYC22UulGt7uws0U3gysIy3 iK0WdVda6DnHhO4Ot4dinqU+n8oY0ecMg5uXR9O80v/XTBQUSlTG37Die+yVjWuE26d3 G9Zu4d4YtTYWd5+UpeE/ILTJaC2ccP5NeXsNc4TkCylDyBa2+VZ3Rgh/POsGTIFiSM1Y eakMQBm9tnlfiAR4tNJlUfakvoCCoWockaGtXpu41aaN6fcHd+0XPaPOEHnO1IC9N8iv AtgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hzYHz6It3AnWry9x4xd8y7/vHlQd0K6YIrGLt3sNlSw=; b=PFye0dQ/iHLzVOQyWM8e1vOcjr0ENm8nnLXUmf+I/mzAQTOqtAYuoecqVuB9U0Dcjq s8CCIWU7wa0XccrIrZ0suQiia6aLTqCQEMkAzAUDQoeCb+MHPYZU4oZ3QdTbMEf4xFMa kC2qqV8xB5EnF6PXQmpvQ992XmYw5QNEZ+JshZu223FQBIrwty9268KtKdxMzdD0pKYz gOmxOcN5Fqo/HxF9MB2z6TuD71HDJpXNTYdtgxbG3gFvMICBj2pwBgVdM8EO/KD5qmHq g6cDtGvtSkTqF+Q6y1Ds66eTfQzR/V+PO/cE2cqgWXHAOoDATViwPtj/GUKuDeyjNYvi 1BEg== X-Gm-Message-State: ALQs6tBn/BIx6vxXzUs+l2OrTQsB0CDOSyVNnWWArN8gjEhbLIvJnFC/ evOeqy+1odKnc2pGaG1RSkp+TFLKfW8= X-Google-Smtp-Source: AB8JxZrU/JvREh3G0AmhlNizn/UMRorvjMTDRJz/PLxalT3TrhUUP+1F7lyvcDge9VVZU0RWBB7xdA== X-Received: by 2002:a63:385a:: with SMTP id h26-v6mr26340531pgn.147.1525563462466; Sat, 05 May 2018 16:37:42 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:42 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:20 +1200 Message-Id: <1525563325-62963-16-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The mstatus.MXR alias in sstatus should only be writable by S-mode if the privileged ISA version >= v1.10. Also MXR was masked in sstatus CSR read but not sstatus CSR writes. Now we correctly mask sstatus.mxr in both read and write. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 101dac1ee8dc..f45ac7306c38 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -234,7 +234,10 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, target_ulong ms = env->mstatus; target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS - | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; + | SSTATUS_SUM | SSTATUS_SD; + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + mask |= SSTATUS_MXR; + } ms = (ms & ~mask) | (val_to_write & mask); csr_write_helper(env, ms, CSR_MSTATUS); break; @@ -441,7 +444,7 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) case CSR_SSTATUS: { target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS - | SSTATUS_SUM | SSTATUS_SD; + | SSTATUS_SUM | SSTATUS_SD; if (env->priv_ver >= PRIV_VERSION_1_10_0) { mask |= SSTATUS_MXR; } From patchwork Sat May 5 23:35:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909220 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="DqP0+UHj"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlnW0lSjz9s2k for ; Sun, 6 May 2018 09:43:25 +1000 (AEST) Received: from localhost ([::1]:40292 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6pn-00007J-Ej for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:43:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54520) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6kR-0004Rh-A1 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6kN-00042A-C8 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:51 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:38445) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6kN-00041r-36 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:47 -0400 Received: by mail-pg0-x241.google.com with SMTP id n9-v6so17787895pgq.5 for ; Sat, 05 May 2018 16:37:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t5jzHwZhrBCS47Yav0WwUHhCUGb9cJydHDYOjLekbgU=; b=DqP0+UHjeNrtetjS9K81zOap7bM1JXZcia6Hdxo4Y83ourKowjNt3OzraEBgkponnH XyMMQRU9kzSg1W4GXI4HN3+hBjEigRwBB9LQ8jlQv+NKOqUNJzTls65EvoCB6nP90WWq qfC/+9U+ARBGiJIxfyvn1MhGluN52uncWIzEP99zR+K3r+Qh3olL4quWYqwE1D7gH7nV B7GiARyPIG3YF/QVUrg0oHMAfF9WjxvsKJBiaibv7v7+hhuwsTxhWVJUR8N9d6HOUlfJ 4Y8i4IYvBQEdBP0gwttBV9+/1jigThFZvvTfLMW5tIxJFpC2DT9kVYkPF5u9oRNl5hvU MVGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t5jzHwZhrBCS47Yav0WwUHhCUGb9cJydHDYOjLekbgU=; b=P3hf2RX7Ob1d5P6C7jenDlpMk+vrNOP3trww6ZXEaAuMO2VZH/5cRsT6O/EjOHHSjn 3h7x07UoAwdCiLFbrvHBN6B0htGy1SRS/ZuJP+H6dwKNL1Koio0zvdgH2uYKa+Mrz13F teCrpASTLtURQR3wdzUJtIQ3DoiiZe8g8HvNt5eJbAVB8cOXM2YJEU7y8xebwa2B8NSl Hx5i868N0KtzFRbs0yN301XTduKYEhHQmL0ZwANCPPmyyWytYLkkwsjWAzZN/didRont gxa9gQZBcbjZDknL+RBz11808sSY3A4l45tbLW3tBDdZshpnY44yQhzxkjBq8IHtCq/X Cc3Q== X-Gm-Message-State: ALQs6tBHAHh87xWIS/fPnHMIznF5MErLVG9tkTZROy9bqd/osUJONq3M JVxYCVrje6Jheq1YdN3h/LNFMZw/qHw= X-Google-Smtp-Source: AB8JxZpRLWaw8aMAhfxj7FcM6OgEOzZcSbY7DJxon1PMp2rwhlyW7XkBR46f4SmTnq+iT6r42RjDCg== X-Received: by 10.98.228.8 with SMTP id r8mr31956197pfh.172.1525563466147; Sat, 05 May 2018 16:37:46 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:45 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:21 +1200 Message-Id: <1525563325-62963-17-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Privileged ISA v1.9.1 defines mscounteren and mucounteren: * mscounteren contains a mask of counters available to S-mode * mucounteren contains a mask of counters available to U-mode Privileged ISA v1.10 defines mcounteren and scounteren: * mcounteren contains a mask of counters available to S-mode * scounteren contains a mask of counters available to U-mode mcounteren and scounteren CSR registers were implemented however they were not honoured for counter accesses when the privilege ISA was >= v1.10. This fix solves the issue by coalescing the counter enable registers. In addition the code now generates illegal instruction exceptions for accesses to the counter enabled registers depending on the privileged ISA version. - Coalesce mscounteren and mcounteren into one variable - Coalesce mucounteren and scounteren into one variable - Makes mcounteren and scounteren CSR accesses generate illegal instructions when the privileged ISA <= v1.9.1 - Makes mscounteren and mucounteren CSR accesses generate illegal instructions when the privileged ISA >= v1.10 Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- target/riscv/cpu.h | 6 ++--- target/riscv/op_helper.c | 62 +++++++++++++++++++++++++++++++++++++----------- 2 files changed, 50 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1dcbdbe6f77d..34abc383e3d4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -151,10 +151,8 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ - uint32_t mucounteren; - uint32_t mscounteren; - target_ulong scounteren; /* since: priv-1.10.0 */ - target_ulong mcounteren; /* since: priv-1.10.0 */ + target_ulong scounteren; + target_ulong mcounteren; target_ulong sscratch; target_ulong mscratch; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f45ac7306c38..7416412b187c 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -225,11 +225,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented"); goto do_illegal; case CSR_MUCOUNTEREN: - env->mucounteren = val_to_write; - break; + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + env->scounteren = val_to_write; + break; + } else { + goto do_illegal; + } case CSR_MSCOUNTEREN: - env->mscounteren = val_to_write; - break; + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + env->mcounteren = val_to_write; + break; + } else { + goto do_illegal; + } case CSR_SSTATUS: { target_ulong ms = env->mstatus; target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE @@ -286,8 +294,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, env->stvec = val_to_write >> 2 << 2; break; case CSR_SCOUNTEREN: - env->scounteren = val_to_write; - break; + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + env->scounteren = val_to_write; + break; + } else { + goto do_illegal; + } case CSR_SSCRATCH: env->sscratch = val_to_write; break; @@ -308,8 +320,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, env->mtvec = val_to_write >> 2 << 2; break; case CSR_MCOUNTEREN: - env->mcounteren = val_to_write; - break; + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + env->mcounteren = val_to_write; + break; + } else { + goto do_illegal; + } case CSR_MSCRATCH: env->mscratch = val_to_write; break; @@ -347,6 +363,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, case CSR_PMPADDR15: pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write); break; +#endif +#if !defined(CONFIG_USER_ONLY) do_illegal: #endif default: @@ -362,8 +380,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) { #ifndef CONFIG_USER_ONLY - target_ulong ctr_en = env->priv == PRV_U ? env->mucounteren : - env->priv == PRV_S ? env->mscounteren : -1U; + target_ulong ctr_en = env->priv == PRV_U ? env->scounteren : + env->priv == PRV_S ? env->mcounteren : -1U; #else target_ulong ctr_en = -1; #endif @@ -438,9 +456,17 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) #endif break; case CSR_MUCOUNTEREN: - return env->mucounteren; + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + return env->scounteren; + } else { + break; /* illegal instruction */ + } case CSR_MSCOUNTEREN: - return env->mscounteren; + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + return env->mcounteren; + } else { + break; /* illegal instruction */ + } case CSR_SSTATUS: { target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS @@ -465,7 +491,11 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) case CSR_STVEC: return env->stvec; case CSR_SCOUNTEREN: - return env->scounteren; + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + return env->scounteren; + } else { + break; /* illegal instruction */ + } case CSR_SCAUSE: return env->scause; case CSR_SATP: /* CSR_SPTBR */ @@ -510,7 +540,11 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) case CSR_MTVEC: return env->mtvec; case CSR_MCOUNTEREN: - return env->mcounteren; + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + return env->mcounteren; + } else { + break; /* illegal instruction */ + } case CSR_MEDELEG: return env->medeleg; case CSR_MIDELEG: From patchwork Sat May 5 23:35:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909231 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="ZvCgmtdx"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dm113675z9s2k for ; Sun, 6 May 2018 09:53:25 +1000 (AEST) Received: from localhost ([::1]:40343 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6zT-0007fE-2U for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:53:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6kS-0004SY-8I for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6kQ-00045V-MI for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:52 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:41657) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6kQ-00044v-G9 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:50 -0400 Received: by mail-pf0-x242.google.com with SMTP id v63so20078338pfk.8 for ; Sat, 05 May 2018 16:37:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2f6FS39+fCEkJOvEEmeQtivubEvzxzkmeEqkjzJ6pMY=; b=ZvCgmtdxrOMHD+FUuiMJyLXA7KJ5RLEta2HmGnWfwUexNa3yxte25e3V2rpPyAdMNQ 2lrUrDilc2X3mIPdywdXuElRimN8+fGuSoFNcGSJyvzUjCCg50XLzQPpA8XyV52Tfgn1 IUz0pCazt3sewhfQYzRjqoAI0vwXMt4EyuPGSAhp9BQDpm878GVMB0x9oIjyBixbTFbB suLt/q6pO24YboGKdAC/nkSSsYwqMwmrYhWAuy1wXQurvU4oUWHbvMJKKm6u4BpXTD5+ BlxlusGglUUtLzYm6CQxPfhqOVuYa1ccd3xomAHfucUGJplqVfOkmCROllaWZwxF0qdo 3+EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2f6FS39+fCEkJOvEEmeQtivubEvzxzkmeEqkjzJ6pMY=; b=bP59c7nvCqOxui9y1fJ8eQKeEnSq5rs1DnD2b8zIlSLvrwi4YHqzgc6bXlHR28GmZ8 KoMAm7Ur6KRXoJ+mIQDkbaSl+p1hC1YDPMGwZH26D63jQFK/DROHsNALABq2/DSeZIzG hUZc/n2rvw+cM800HXjJFGf6lPXjfCVkDVZwUCvcwPI8xwimzCHNwVzXvjpU3zi4wZ7N 3rZr6iM9WUUaNQ9yhIVXGeXFqISfnpByGkuf+lM60OIimApUhTEfDm2NQv5oCRzlpPiD 5kC2vyP1LU0j+LbF7+ftDsfVOriWEObtcFC1aIWAZkJAE0/tHQvz/gieGMx3OkUJ4REt AdbQ== X-Gm-Message-State: ALQs6tBX/ROUo9BXc4obwySlSB7fb6xccWHEfX/i/TfBb31p2YePQp0H dnvFvXPyOq0ek3qPUZpYOtTaT1pIV9c= X-Google-Smtp-Source: AB8JxZpBiPbe97kRBXZXYuCMipb8OZ+AtmKE09/XqGzTOfvrImihTZm+2Fz61xYoU0KJDZLTzOpfKQ== X-Received: by 10.98.137.219 with SMTP id n88mr31567742pfk.11.1525563469572; Sat, 05 May 2018 16:37:49 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:49 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:22 +1200 Message-Id: <1525563325-62963-18-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Previously the mycycle/minstret CSRs and rdcycle/rdinstret psuedo instructions would return the time as a proxy for an increasing instruction counter in the absence of having a precise instruction count. If QEMU is invoked with -icount, the mcycle/minstret CSRs and rdcycle/rdinstret psuedo instructions will return the instruction count. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 28 ++++++++++++++++++++++++++-- target/riscv/translate.c | 2 ++ 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7416412b187c..3512462f4fd8 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -434,25 +434,49 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) case CSR_INSTRET: case CSR_CYCLE: if (ctr_ok) { +#if !defined(CONFIG_USER_ONLY) + if (use_icount) { + return cpu_get_icount(); + } else { + return cpu_get_host_ticks(); + } +#else return cpu_get_host_ticks(); +#endif } break; #if defined(TARGET_RISCV32) case CSR_INSTRETH: case CSR_CYCLEH: if (ctr_ok) { +#if !defined(CONFIG_USER_ONLY) + if (use_icount) { + return cpu_get_icount() >> 32; + } else { + return cpu_get_host_ticks() >> 32; + } +#else return cpu_get_host_ticks() >> 32; +#endif } break; #endif #ifndef CONFIG_USER_ONLY case CSR_MINSTRET: case CSR_MCYCLE: - return cpu_get_host_ticks(); + if (use_icount) { + return cpu_get_icount(); + } else { + return cpu_get_host_ticks(); + } case CSR_MINSTRETH: case CSR_MCYCLEH: #if defined(TARGET_RISCV32) - return cpu_get_host_ticks() >> 32; + if (use_icount) { + return cpu_get_icount() >> 32; + } else { + return cpu_get_host_ticks() >> 32; + } #endif break; case CSR_MUCOUNTEREN: diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c3a029afefd9..c0e6a044d383 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1390,6 +1390,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, break; default: tcg_gen_movi_tl(imm_rs1, rs1); + gen_io_start(); switch (opc) { case OPC_RISC_CSRRW: gen_helper_csrrw(dest, cpu_env, source1, csr_store); @@ -1413,6 +1414,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, gen_exception_illegal(ctx); return; } + gen_io_end(); gen_set_gpr(rd, dest); /* end tb since we may be changing priv modes, to get mmu_index right */ tcg_gen_movi_tl(cpu_pc, ctx->next_pc); From patchwork Sat May 5 23:35:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909228 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="FtJT/nsN"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dlwX3W6Bz9s27 for ; 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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:52 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:23 +1200 Message-Id: <1525563325-62963-19-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Later we can add RISCV_FEATURE_VECTORED_TRAPS however until then the correct behavior for WARL (Write Any, Read Legal) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- target/riscv/op_helper.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3512462f4fd8..af0c52a48418 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -287,11 +287,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, env->sepc = val_to_write; break; case CSR_STVEC: - if (val_to_write & 1) { + /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ + if ((val_to_write & 3) == 0) { + env->stvec = val_to_write >> 2 << 2; + } else { qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported"); - goto do_illegal; } - env->stvec = val_to_write >> 2 << 2; break; case CSR_SCOUNTEREN: if (env->priv_ver >= PRIV_VERSION_1_10_0) { @@ -313,11 +314,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, env->mepc = val_to_write; break; case CSR_MTVEC: - if (val_to_write & 1) { + /* bits [1:0] indicate mode; 0 = direct, 1 = vectored, 2 >= reserved */ + if ((val_to_write & 3) == 0) { + env->mtvec = val_to_write >> 2 << 2; + } else { qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported"); - goto do_illegal; } - env->mtvec = val_to_write >> 2 << 2; break; case CSR_MCOUNTEREN: if (env->priv_ver >= PRIV_VERSION_1_10_0) { From patchwork Sat May 5 23:35:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909232 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="THHE0GBM"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40dm2N1YCsz9s27 for ; Sun, 6 May 2018 09:54:34 +1000 (AEST) Received: from localhost ([::1]:40347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF70Z-0008LC-K2 for incoming@patchwork.ozlabs.org; Sat, 05 May 2018 19:54:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54613) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6kc-0004cb-JW for qemu-devel@nongnu.org; Sat, 05 May 2018 19:38:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6kY-0004AV-MV for qemu-devel@nongnu.org; Sat, 05 May 2018 19:38:02 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35779) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6kY-00049w-33 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:58 -0400 Received: by mail-pf0-x242.google.com with SMTP id x9so932301pfm.2 for ; Sat, 05 May 2018 16:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8aeU5ABUVuJllnFu+Xb6Txv4vMRZ+bEt/Kmtn6S0UTY=; b=THHE0GBMErS5+CAe6kT0Umux0Sv9PzmwKTnq7sobVLrDf7VoU3DPLtQ4PWv51amhDv U3UpGa+521n8fJysZ2YBHZDKszdRbIKBdpFTsX7/FqtG9pplh0pR4FhWto9UMw1w5aZt pt8s5a73Kic5HqpWV1byxezWrSD2RP47zgSA92Vl054JmXAYb8iiRAFR+BVP+diFBHDx WJMHFAJzQjLotEEquH/lZbZmEkRs6ShvGpTbQTlZdCGMaF2F2FNkz/VtQo0NuqkqxqX6 aSJ6pwboPjCyXvWD3ydBF3WDuQSx2lYzc5n6BgZiB/kIGgURpVNblqY9Adk0pZeUaHqt gawg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8aeU5ABUVuJllnFu+Xb6Txv4vMRZ+bEt/Kmtn6S0UTY=; b=X3pjYli0C4S7MvBknCSdcnMK6w+T8PcKHv3SYKHVCQ8VFKqwEM9m4WVGE20BT11iyb jxmeKb3L+V8sGAYO2BT+fXwr4nKo7jQMnGI+xNmBlOXtIcByUFAwE/TDv1EQgFFvrJ// 6GeThGkJ4OMu8F1uvjC/KQMhes3s3jtVtmYri4osFjKhYYxURmCQV4WqA+zDDDlLBkNH Z5m4VrPZrMFRWl6NPwnDdDQZ+h3co7L9KGhi/WhxmCoZmDIZabeuXa61rxzxLm27w82f YBhRItpUbaTPjzEUyrb3YLay5WSwt6szxa6zicAMScLFbzxfHxy0qOst5BeFoZIPWbS1 0inA== X-Gm-Message-State: ALQs6tATRkLOyDMPPCLNKCowFRqLqm305H1a3f7QFYwW354tM0Sbc+xu JBL+LEda6Wr5lziOsdafzWYhFJlykhI= X-Google-Smtp-Source: AB8JxZoVZ1eQPjGbQIapDdBlI3FJKN7u7vSmPUJh6TphD4uYX2o3K7sCLkqfYw2IFcnGr2wbbYwuCg== X-Received: by 2002:a17:902:2804:: with SMTP id e4-v6mr32910444plb.153.1525563477148; Sat, 05 May 2018 16:37:57 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:56 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:24 +1200 Message-Id: <1525563325-62963-20-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These fields are marked WARL (Write Any Values, Reads Legal Values) in the RISC-V Privileged Architecture Specification so instead of raising exceptions, illegal writes are silently dropped. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- target/riscv/op_helper.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index af0c52a48418..3abf52453cfc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -213,17 +213,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, break; } case CSR_MINSTRET: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented"); - goto do_illegal; + /* minstret is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLE: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented"); - goto do_illegal; + /* mcycle is WARL so unsupported writes are ignored */ + break; +#if defined(TARGET_RISCV32) case CSR_MINSTRETH: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented"); - goto do_illegal; + /* minstreth is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLEH: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented"); - goto do_illegal; + /* mcycleh is WARL so unsupported writes are ignored */ + break; +#endif case CSR_MUCOUNTEREN: if (env->priv_ver <= PRIV_VERSION_1_09_1) { env->scounteren = val_to_write; @@ -337,10 +339,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, case CSR_MBADADDR: env->mbadaddr = val_to_write; break; - case CSR_MISA: { - qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported"); - goto do_illegal; - } + case CSR_MISA: + /* misa is WARL so unsupported writes are ignored */ + break; case CSR_PMPCFG0: case CSR_PMPCFG1: case CSR_PMPCFG2: From patchwork Sat May 5 23:35:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 909225 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:38:00 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:25 +1200 Message-Id: <1525563325-62963-21-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 20/20] RISC-V: Mark ROM read-only after copying in code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The sifive_u machine already marks its ROM readonly however it has the wrong base address for its mask ROM. This patch fixes the sifive_u mask ROM base address. This commit makes all other boards consistently use mask_rom as the variable name for their ROMs. Boards that use device tree now check that that the device tree fits in the assigned ROM space using the new qemu_fdt_totalsize(void *fdt) interface, adding a bounds check and error message. This can detect truncation. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 20 +++++++--------- hw/riscv/sifive_u.c | 51 +++++++++++++++++++++------------------ hw/riscv/spike.c | 69 +++++++++++++++++++++++++++++++---------------------- hw/riscv/virt.c | 43 ++++++++++++++++++--------------- 4 files changed, 101 insertions(+), 82 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 6fa223818502..e4ecb7aa4bb6 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -74,14 +74,6 @@ static const struct MemmapEntry { [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } }; -static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) -{ - int i; - for (i = 0; i < (len >> 2); i++) { - stl_phys(&address_space_memory, pa + (i << 2), rom[i]); - } -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; @@ -112,6 +104,7 @@ static void riscv_sifive_e_init(MachineState *machine) MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *mask_rom = g_new(MemoryRegion, 1); MemoryRegion *xip_mem = g_new(MemoryRegion, 1); + int i; /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -131,7 +124,7 @@ static void riscv_sifive_e_init(MachineState *machine) memmap[SIFIVE_E_DTIM].base, main_mem); /* Mask ROM */ - memory_region_init_ram(mask_rom, NULL, "riscv.sifive.e.mrom", + memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom", memmap[SIFIVE_E_MROM].size, &error_fatal); memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_MROM].base, mask_rom); @@ -185,9 +178,12 @@ static void riscv_sifive_e_init(MachineState *machine) 0x00028067, /* 0x1004: jr t0 */ }; - /* copy in the reset vector */ - copy_le32_to_phys(memmap[SIFIVE_E_MROM].base, reset_vec, sizeof(reset_vec)); - memory_region_set_readonly(mask_rom, true); + /* copy in the reset vector in little_endian byte order */ + for (i = 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] = cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + memmap[SIFIVE_E_MROM].base, &address_space_memory); if (machine->kernel_filename) { load_kernel(machine->kernel_filename); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 84afed4c3b0e..c05dcbba955e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -47,12 +47,14 @@ #include "exec/address-spaces.h" #include "elf.h" +#include + static const struct MemmapEntry { hwaddr base; hwaddr size; } sifive_u_memmap[] = { [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, - [SIFIVE_U_MROM] = { 0x1000, 0x2000 }, + [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, @@ -60,14 +62,6 @@ static const struct MemmapEntry { [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, }; -static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) -{ - int i; - for (i = 0; i < (len >> 2); i++) { - stl_phys(&address_space_memory, pa + (i << 2), rom[i]); - } -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; @@ -221,9 +215,10 @@ static void riscv_sifive_u_init(MachineState *machine) const struct MemmapEntry *memmap = sifive_u_memmap; SiFiveUState *s = g_new0(SiFiveUState, 1); - MemoryRegion *sys_memory = get_system_memory(); + MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); - MemoryRegion *boot_rom = g_new(MemoryRegion, 1); + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + int i; /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -239,17 +234,17 @@ static void riscv_sifive_u_init(MachineState *machine) /* register RAM */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", machine->ram_size, &error_fatal); - memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base, + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, main_mem); /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom", - memmap[SIFIVE_U_MROM].base, &error_fatal); - memory_region_set_readonly(boot_rom, true); - memory_region_add_subregion(sys_memory, 0x0, boot_rom); + memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", + memmap[SIFIVE_U_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + mask_rom); if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -272,13 +267,23 @@ static void riscv_sifive_u_init(MachineState *machine) /* dtb: */ }; - /* copy in the reset vector */ - copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_vec)); + /* copy in the reset vector in little_endian byte order */ + for (i = 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] = cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + memmap[SIFIVE_U_MROM].base, &address_space_memory); /* copy in the device tree */ - qemu_fdt_dumpdtb(s->fdt, s->fdt_size); - cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + - sizeof(reset_vec), s->fdt, s->fdt_size); + if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > + memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { + error_report("not enough space to store device-tree"); + exit(1); + } + qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); + rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), + memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), + &address_space_memory); /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, @@ -292,9 +297,9 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_U_PLIC_CONTEXT_BASE, SIFIVE_U_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_U_PLIC].size); - sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base, + sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]); - /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base, + /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */ sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, smp_cpus, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 9e18c618bfbb..f94e2b670799 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -42,23 +42,17 @@ #include "exec/address-spaces.h" #include "elf.h" +#include + static const struct MemmapEntry { hwaddr base; hwaddr size; } spike_memmap[] = { - [SPIKE_MROM] = { 0x1000, 0x2000 }, + [SPIKE_MROM] = { 0x1000, 0x11000 }, [SPIKE_CLINT] = { 0x2000000, 0x10000 }, [SPIKE_DRAM] = { 0x80000000, 0x0 }, }; -static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) -{ - int i; - for (i = 0; i < (len >> 2); i++) { - stl_phys(&address_space_memory, pa + (i << 2), rom[i]); - } -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; @@ -173,7 +167,8 @@ static void spike_v1_10_0_board_init(MachineState *machine) SpikeState *s = g_new0(SpikeState, 1); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); - MemoryRegion *boot_rom = g_new(MemoryRegion, 1); + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + int i; /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -196,9 +191,10 @@ static void spike_v1_10_0_board_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", - s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -221,16 +217,26 @@ static void spike_v1_10_0_board_init(MachineState *machine) /* dtb: */ }; - /* copy in the reset vector */ - copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec)); + /* copy in the reset vector in little_endian byte order */ + for (i = 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] = cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + memmap[SPIKE_MROM].base, &address_space_memory); /* copy in the device tree */ - qemu_fdt_dumpdtb(s->fdt, s->fdt_size); - cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), - s->fdt, s->fdt_size); + if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > + memmap[SPIKE_MROM].size - sizeof(reset_vec)) { + error_report("not enough space to store device-tree"); + exit(1); + } + qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); + rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), + memmap[SPIKE_MROM].base + sizeof(reset_vec), + &address_space_memory); /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hd(0)); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, @@ -244,7 +250,8 @@ static void spike_v1_09_1_board_init(MachineState *machine) SpikeState *s = g_new0(SpikeState, 1); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); - MemoryRegion *boot_rom = g_new(MemoryRegion, 1); + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + int i; /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -264,9 +271,10 @@ static void spike_v1_09_1_board_init(MachineState *machine) main_mem); /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", - 0x40000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -319,15 +327,20 @@ static void spike_v1_09_1_board_init(MachineState *machine) g_free(isa); size_t config_string_len = strlen(config_string); - /* copy in the reset vector */ - copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec)); + /* copy in the reset vector in little_endian byte order */ + for (i = 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] = cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + memmap[SPIKE_MROM].base, &address_space_memory); /* copy in the config string */ - cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), - config_string, config_string_len); + rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len, + memmap[SPIKE_MROM].base + sizeof(reset_vec), + &address_space_memory); /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hd(0)); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 7ef9ba26debc..ad03113e0f72 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -40,13 +40,15 @@ #include "exec/address-spaces.h" #include "elf.h" +#include + static const struct MemmapEntry { hwaddr base; hwaddr size; } virt_memmap[] = { [VIRT_DEBUG] = { 0x0, 0x100 }, - [VIRT_MROM] = { 0x1000, 0x2000 }, - [VIRT_TEST] = { 0x4000, 0x1000 }, + [VIRT_MROM] = { 0x1000, 0x11000 }, + [VIRT_TEST] = { 0x100000, 0x1000 }, [VIRT_CLINT] = { 0x2000000, 0x10000 }, [VIRT_PLIC] = { 0xc000000, 0x4000000 }, [VIRT_UART0] = { 0x10000000, 0x100 }, @@ -54,14 +56,6 @@ static const struct MemmapEntry { [VIRT_DRAM] = { 0x80000000, 0x0 }, }; -static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) -{ - int i; - for (i = 0; i < (len >> 2); i++) { - stl_phys(&address_space_memory, pa + (i << 2), rom[i]); - } -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; @@ -272,7 +266,7 @@ static void riscv_virt_board_init(MachineState *machine) RISCVVirtState *s = g_new0(RISCVVirtState, 1); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); - MemoryRegion *boot_rom = g_new(MemoryRegion, 1); + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; int i; @@ -299,9 +293,10 @@ static void riscv_virt_board_init(MachineState *machine) fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", - s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", + memmap[VIRT_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, + mask_rom); if (machine->kernel_filename) { uint64_t kernel_entry = load_kernel(machine->kernel_filename); @@ -335,13 +330,23 @@ static void riscv_virt_board_init(MachineState *machine) /* dtb: */ }; - /* copy in the reset vector */ - copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)); + /* copy in the reset vector in little_endian byte order */ + for (i = 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] = cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + memmap[VIRT_MROM].base, &address_space_memory); /* copy in the device tree */ - qemu_fdt_dumpdtb(s->fdt, s->fdt_size); - cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), - s->fdt, s->fdt_size); + if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > + memmap[VIRT_MROM].size - sizeof(reset_vec)) { + error_report("not enough space to store device-tree"); + exit(1); + } + qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); + rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), + memmap[VIRT_MROM].base + sizeof(reset_vec), + &address_space_memory); /* create PLIC hart topology configuration string */ plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;