From patchwork Fri Apr 27 09:05:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 905539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-476892-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="tAC8sE3V"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40XShr5xV0z9s0v for ; Fri, 27 Apr 2018 19:06:04 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=idRLr1LEFCkGEsr0SM8Qm4uBGvHZ78NpMPOfYsXa2+PFLl 08KHw8dkVgM8m3yBxIhQizUO/lEql2VGdKAk1RBB9EZdKpgkoppTMNBuioYYlQSC zf715/OKag14cqQ2MaItZFpH1JzkMirG/IIoE8L7sczMqjhOPt0OpG0MEHS6M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=drN12ZD0Frs++Zp9GG6J4yKo3S0=; b=tAC8sE3Vh67WZjxIS4Xd 0nntoqcJeEPKav2PNbjR3xTskqgKZ5g3o69jDpMu27itWq6yppF9CTr3lIssc1Be wtTKLzlpWDsKsVXqW/doB9fdzzt0IScp0P1S3Loi83H4/q+/XfVGlTvuiTko+iGQ 5kpxxYvmA6BYeuzMFR0Q5R8= Received: (qmail 122316 invoked by alias); 27 Apr 2018 09:05:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 122228 invoked by uid 89); 27 Apr 2018 09:05:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.7 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=symbol_ref, v4sf, TARGET_64BIT, V4SI X-HELO: mail-it0-f47.google.com Received: from mail-it0-f47.google.com (HELO mail-it0-f47.google.com) (209.85.214.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Apr 2018 09:05:46 +0000 Received: by mail-it0-f47.google.com with SMTP id c3-v6so1001879itj.4 for ; Fri, 27 Apr 2018 02:05:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=yHeZinXvKLIJW+eEKO2dm9xUnRQFi+Z1N08hPSQT2js=; b=cf9+M6ngTWCP2lG+Uoni3kP32KJcyeMUSRruPKd6ai8B2J9Yhq5rwJ5p1GSu7y6B/u fgIS/nxtZdKTEMPXd2a7Vt1ACNSBUuIj2IbsFfk4JFDukXr6xKmei8aPIYu0JG9IG2w2 3Yl2KnrZIrAY0Qb2vihUIZbKmCvPpNDUnh0L1ESGum4j18+hIYT6SapEZYQxvLDUbcYy 2U5WQIWQgIkMOvITNXqhS0ykJEgRAT05j7zzmQ6RLOILglQMOXfZvajztjecg+Md4vFX K1j10nSHFYlJiaV4FPqyseCX1B3GayRcWs2U9EGgRZbQbD4KqKNiQ16dXRFk7feMmDj+ 9MNA== X-Gm-Message-State: ALQs6tBlXSPGocLKWWqlYuR8LjNK6n/q3mTo0Hbu6lB0UwhF72tsRPZ1 CePmsrVDXOkhsgFbTjIQhlLaUUYzq8Ha0Qhz88Wqga/O X-Google-Smtp-Source: AB8JxZpc2ZAxGJxbolsxk7idFNMkcJ9pRwTAqvJjnmXgeagBhQ2KBia1c2Wpcu93BFu6h3LNdQbCXNdjnKMKZ9H1Nr8= X-Received: by 2002:a24:b649:: with SMTP id d9-v6mr1068988itj.51.1524819944062; Fri, 27 Apr 2018 02:05:44 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a02:1385:0:0:0:0:0 with HTTP; Fri, 27 Apr 2018 02:05:43 -0700 (PDT) From: Uros Bizjak Date: Fri, 27 Apr 2018 11:05:43 +0200 Message-ID: Subject: [PATCH 2/2, i386]: Emit inter-unit moves using preferred_for_speed infrastructure To: "gcc-patches@gcc.gnu.org" Second part of the patch. 2018-04-27 Uros Bizjak * config/i386/i386.md (*movti_internal): Substitute Ye constraint with Yd constraint. Set "preferred_for_speed" attribute from TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC for alternatives with Yd constraint. (*movdi_internal): Ditto. (movti_interunit splitters): Remove TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC from insn condition. (movdi_interunit splitters): Ditto. * config/i386/constraints.md (Ye): Remove. (Yd): Do not depend on TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC. Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/constraints.md =================================================================== --- config/i386/constraints.md (revision 259682) +++ config/i386/constraints.md (working copy) @@ -99,10 +99,8 @@ ;; We use the Y prefix to denote any number of conditional register sets: ;; z First SSE register. -;; d any EVEX encodable SSE register for AVX512BW target or any SSE register -;; for SSE4_1 target, when inter-unit moves to SSE register are enabled -;; e any EVEX encodable SSE register for AVX512BW target or any SSE register -;; for SSE4_1 target, when inter-unit moves from SSE register are enabled +;; d any EVEX encodable SSE register for AVX512BW target or +;; any SSE register for SSE4_1 target. ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled ;; a Integer register when zero extensions with AND are disabled ;; b Any register that can be used as the GOT base when calling @@ -120,21 +118,9 @@ "First SSE register (@code{%xmm0}).") (define_register_constraint "Yd" - "TARGET_INTER_UNIT_MOVES_TO_VEC - ? (TARGET_AVX512DQ - ? ALL_SSE_REGS - : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) - : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") + "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS" + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.") -(define_register_constraint "Ye" - "TARGET_INTER_UNIT_MOVES_FROM_VEC - ? (TARGET_AVX512DQ - ? ALL_SSE_REGS - : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) - : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") - (define_register_constraint "Yp" "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 259682) +++ config/i386/i386.md (working copy) @@ -2123,7 +2123,7 @@ (define_insn "*movti_internal" [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m,?r,?Yd") - (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Ye,r"))] + (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Yd,r"))] "(TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))) || (TARGET_SSE @@ -2203,12 +2203,19 @@ (match_test "optimize_function_for_size_p (cfun)") (const_string "V4SF") ] - (const_string "TI")))]) + (const_string "TI"))) + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "6") + (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC") + (eq_attr "alternative" "7") + (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC") + ] + (symbol_ref "true")))]) (define_split [(set (match_operand:TI 0 "sse_reg_operand") (match_operand:TI 1 "general_reg_operand"))] - "TARGET_64BIT && TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_TO_VEC + "TARGET_64BIT && TARGET_SSE4_1 && reload_completed" [(set (match_dup 2) (vec_merge:V2DI @@ -2227,7 +2234,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r,?*y,*v,*v,*v,m ,m,?r ,?*Yd,?r,?*v,?*y,?*x,*k,*k ,*r,*m") (match_operand:DI 1 "general_operand" - "riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*y,r ,C ,*v,m ,*v,v,*Ye,r ,*v,r ,*x ,*y ,*r,*km,*k,*k"))] + "riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*y,r ,C ,*v,m ,*v,v,*Yd,r ,*v,r ,*x ,*y ,*r,*km,*k,*k"))] "!(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (get_attr_type (insn)) @@ -2379,9 +2386,9 @@ ] (const_string "DI"))) (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "10,19") + (cond [(eq_attr "alternative" "10,17,19") (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC") - (eq_attr "alternative" "11,20") + (eq_attr "alternative" "11,18,20") (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC") ] (symbol_ref "true"))) @@ -2402,7 +2409,7 @@ (define_split [(set (match_operand: 0 "general_reg_operand") (match_operand: 1 "sse_reg_operand"))] - "TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_FROM_VEC + "TARGET_SSE4_1 && reload_completed" [(set (match_dup 2) (vec_select:DWIH @@ -2426,7 +2433,7 @@ (define_split [(set (match_operand:DI 0 "sse_reg_operand") (match_operand:DI 1 "general_reg_operand"))] - "!TARGET_64BIT && TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_TO_VEC + "!TARGET_64BIT && TARGET_SSE4_1 && reload_completed" [(set (match_dup 2) (vec_merge:V4SI