From patchwork Fri Apr 27 08:14:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 905514 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40XRZP6WkPz9s0v for ; Fri, 27 Apr 2018 18:15:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757649AbeD0IPF (ORCPT ); Fri, 27 Apr 2018 04:15:05 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52899 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1757650AbeD0IPC (ORCPT ); Fri, 27 Apr 2018 04:15:02 -0400 X-UUID: ea93953e2edb49679cc78833dd920f65-20180427 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1763935348; Fri, 27 Apr 2018 16:14:57 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 27 Apr 2018 16:14:48 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 27 Apr 2018 16:14:48 +0800 From: To: , , , , , CC: , , , , , Sean Wang Subject: [PATCH v2 1/6] dt-bindings: gpu: mali-utgard: add mediatek, mt7623-mali compatible Date: Fri, 27 Apr 2018 16:14:42 +0800 Message-ID: <7ab060c2e9ef2b220fc62913b8936b706dfaf202.1524816502.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sean Wang The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it and define its own vendor-specific properties. Reviewed-by: Rob Herring Signed-off-by: Sean Wang --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 99d1c0a..656068f 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -19,6 +19,7 @@ Required properties: + rockchip,rk3228-mali + rockchip,rk3328-mali + stericsson,db8500-mali + + mediatek,mt7623-mali - reg: Physical base address and length of the GPU registers @@ -89,6 +90,14 @@ to specify one more vendor-specific compatible, among: * interrupt-names and interrupts: + combined: combined interrupt of all of the above lines + - mediatek,mt7623-mali + Required properties: + * resets: phandle to the reset line for the GPU + * mediatek,larb: phandle pointed to the local arbiter used to control the + access to external memory on the SoC. + see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details + Example: mali: gpu@1c40000 { From patchwork Fri Apr 27 08:14:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 905513 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40XRYr55Drz9s0v for ; Fri, 27 Apr 2018 18:14:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757667AbeD0IOy (ORCPT ); Fri, 27 Apr 2018 04:14:54 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:16422 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1757593AbeD0IOx (ORCPT ); Fri, 27 Apr 2018 04:14:53 -0400 X-UUID: ca02fbf927fc40ed8afd4f71dffb025b-20180427 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 534401716; Fri, 27 Apr 2018 16:14:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 27 Apr 2018 16:14:48 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 27 Apr 2018 16:14:48 +0800 From: To: , , , , , CC: , , , , , Sean Wang Subject: [PATCH v2 2/6] dt-bindings: clock: mediatek: add g3dsys bindings Date: Fri, 27 Apr 2018 16:14:43 +0800 Message-ID: <665c38d5803573aa9a01471253f406301b1123a1.1524816502.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sean Wang Add bindings to g3dsys providing necessary clock and reset control to Mali-450. Signed-off-by: Sean Wang Reviewed-by: Rob Herring --- .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt new file mode 100644 index 0000000..7de43bf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt @@ -0,0 +1,30 @@ +MediaTek g3dsys controller +============================ + +The MediaTek g3dsys controller provides various clocks and reset controller to +the GPU. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt2701-g3dsys", "syscon": + for MT2701 SoC + - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon": + for MT7623 SoC +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The g3dsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +g3dsys: clock-controller@13000000 { + compatible = "mediatek,mt7623-g3dsys", + "mediatek,mt2701-g3dsys", + "syscon"; + reg = <0 0x13000000 0 0x200>; + #clock-cells = <1>; + #reset-cells = <1>; +}; From patchwork Fri Apr 27 08:14:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 905516 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40XRbW2tlhz9ryr for ; Fri, 27 Apr 2018 18:16:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757720AbeD0IPY (ORCPT ); Fri, 27 Apr 2018 04:15:24 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:42143 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1757689AbeD0IPE (ORCPT ); Fri, 27 Apr 2018 04:15:04 -0400 X-UUID: 02e43fe195514bf88caeb50468fe727a-20180427 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 347077533; Fri, 27 Apr 2018 16:14:57 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 27 Apr 2018 16:14:48 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 27 Apr 2018 16:14:49 +0800 From: To: , , , , , CC: , , , , , Sean Wang Subject: [PATCH v2 3/6] dt-bindings: clock: mediatek: add entry for Mali-450 node to refer Date: Fri, 27 Apr 2018 16:14:44 +0800 Message-ID: <082c3040e2be27d30e0642943f6df35ff4de5666.1524816502.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sean Wang Just add binding for a required clock referenced by Mali-450 on MT7623 or MT2701 SoC. Cc: devicetree@vger.kernel.org Signed-off-by: Sean Wang Reviewed-by: Rob Herring --- include/dt-bindings/clock/mt2701-clk.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h index 24e93df..2ac62a6 100644 --- a/include/dt-bindings/clock/mt2701-clk.h +++ b/include/dt-bindings/clock/mt2701-clk.h @@ -431,6 +431,10 @@ #define CLK_ETHSYS_CRYPTO 8 #define CLK_ETHSYS_NR 9 +/* G3DSYS */ +#define CLK_G3DSYS_CORE 1 +#define CLK_G3DSYS_NR 2 + /* BDP */ #define CLK_BDP_BRG_BA 1 From patchwork Fri Apr 27 08:14:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 905515 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40XRb93wdhz9s1j for ; Fri, 27 Apr 2018 18:16:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757642AbeD0IP1 (ORCPT ); Fri, 27 Apr 2018 04:15:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:44791 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1757640AbeD0IOz (ORCPT ); Fri, 27 Apr 2018 04:14:55 -0400 X-UUID: d26dcfc1b7b1449ab978df5b29a6c616-20180427 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1033501459; Fri, 27 Apr 2018 16:14:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 27 Apr 2018 16:14:49 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 27 Apr 2018 16:14:49 +0800 From: To: , , , , , CC: , , , , , Sean Wang Subject: [PATCH v2 4/6] dt-bindings: reset: mediatek: add entry for Mali-450 node to refer Date: Fri, 27 Apr 2018 16:14:45 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sean Wang Just add binding for a required reset referenced by Mali-450 on MT7623 or MT2701 SoC. Cc: devicetree@vger.kernel.org Signed-off-by: Sean Wang Reviewed-by: Rob Herring --- include/dt-bindings/reset/mt2701-resets.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/reset/mt2701-resets.h b/include/dt-bindings/reset/mt2701-resets.h index 21deb54..50b7f06 100644 --- a/include/dt-bindings/reset/mt2701-resets.h +++ b/include/dt-bindings/reset/mt2701-resets.h @@ -87,4 +87,7 @@ #define MT2701_ETHSYS_GMAC_RST 23 #define MT2701_ETHSYS_PPE_RST 31 +/* G3DSYS resets */ +#define MT2701_G3DSYS_CORE_RST 0 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */