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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5b29015a3dbsm321132eaf.46.2024.05.10.17.49.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 17:49:56 -0700 (PDT) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= Cc: David Lechner , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Subject: [PATCH RFC v2 1/8] spi: dt-bindings: spi-peripheral-props: add spi-offloads property Date: Fri, 10 May 2024 19:44:24 -0500 Message-ID: <20240510-dlech-mainline-spi-engine-offload-2-v2-1-8707a870c435@baylibre.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240510-dlech-mainline-spi-engine-offload-2-v2-0-8707a870c435@baylibre.com> References: <20240510-dlech-mainline-spi-engine-offload-2-v2-0-8707a870c435@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds a new property to the spi-peripheral-props binding for use with peripherals connected to controllers that support offloading. Here, offloading means that the controller has the ability to perform complex SPI transactions without CPU intervention in some shape or form. This property will be used to assign controller offload resources to each peripheral that needs them. What these resources are will be defined by each specific controller binding. Signed-off-by: David Lechner --- v2 changes: In v1, instead of generic SPI bindings, there were only controller- specific bindings, so this is a new patch. In the previous version I also had an offloads object node that described what the offload capabilities were but it was suggested that this was not necessary/overcomplicated. So I've gone to the other extreme and made it perhaps over-simplified now by requiring all information about how each offload is used to be encoded in a single u32. We could of course consider using #spi-offload-cells instead for allowing encoding multiple parameters for each offload instance if that would be preferable. I also considered adding spi-offload-names that could be used as sort of a compatible string (more of an interface name really) in case some peripherals may want to support more than 1 specialized type of offload. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 15938f81fdce..32991a2d2264 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -113,6 +113,16 @@ properties: minItems: 2 maxItems: 4 + spi-offloads: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Array of controller offload instances that are reserved for use by the + peripheral device. The semantic meaning of the values of the array + elements is defined by the controller. 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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5b29015a3dbsm321132eaf.46.2024.05.10.17.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 17:50:00 -0700 (PDT) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= Cc: David Lechner , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Subject: [PATCH RFC v2 5/8] spi: dt-bindings: axi-spi-engine: document spi-offloads Date: Fri, 10 May 2024 19:44:28 -0500 Message-ID: <20240510-dlech-mainline-spi-engine-offload-2-v2-5-8707a870c435@baylibre.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240510-dlech-mainline-spi-engine-offload-2-v2-0-8707a870c435@baylibre.com> References: <20240510-dlech-mainline-spi-engine-offload-2-v2-0-8707a870c435@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 The AXI SPI Engine has support for hardware offloading capabilities. There can be up to 32 offload instances per SPI controller, so the bindings limit the value accordingly. Signed-off-by: David Lechner --- v2 changes: This is basically a new patch. It partially replaces "dt-bindings: iio: offload: add binding for PWM/DMA triggered buffer". The controller no longer has an offloads object node and the spi-offloads property is now a standard SPI peripheral property. --- .../devicetree/bindings/spi/adi,axi-spi-engine.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index d48faa42d025..c0668aab8b2a 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -41,6 +41,20 @@ properties: - const: s_axi_aclk - const: spi_clk +patternProperties: + "^.*@[0-9a-f]+$": + type: object + $ref: spi-peripheral-props.yaml + additionalProperties: true + properties: + spi-offloads: + description: + An array of 1 or more offload instance numbers assigned to this + peripheral. + items: + minimum: 0 + maximum: 31 + required: - compatible - reg From patchwork Sat May 11 00:44:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 1933957 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5b29015a3dbsm321132eaf.46.2024.05.10.17.50.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 17:50:02 -0700 (PDT) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= Cc: David Lechner , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Subject: [PATCH RFC v2 7/8] dt-bindings: iio: adc: adi,ad7944: add SPI offload properties Date: Fri, 10 May 2024 19:44:30 -0500 Message-ID: <20240510-dlech-mainline-spi-engine-offload-2-v2-7-8707a870c435@baylibre.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240510-dlech-mainline-spi-engine-offload-2-v2-0-8707a870c435@baylibre.com> References: <20240510-dlech-mainline-spi-engine-offload-2-v2-0-8707a870c435@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 To enable capturing data at high rates, the AD7944 is frequently used with the AXI SPI Engine IP core. This patch adds the properties needed to describe the SPI offload configuration in the device tree. The clock trigger and DMA buffer for rx data are external to the SPI controller and specific to the application so the are included in the peripheral bindings. Signed-off-by: David Lechner --- v2 changes: This is a new patch that partially replaces "dt-bindings: iio: offload: add binding for PWM/DMA triggered buffer". In the previous review, it was suggested that having a separate binding and object node for the offload was overcomplicated. So instead this opts to use the proposed standard spi-offloads property as a flag to allow the SPI periperhal node require additional properties that are resources that are physically connected to the SPI offload. On a whim, I also changed pwms to clocks in the binding. The thinking being that we only care about the frequency (it determines the sample rate) so a clock made more sense and might allow more flexibility in the future. But since the actual hardware we have is a PWM, we would have to use "pwm-clock" in the devicetree to make the PWM act as a clock. But it turns out that the pwm-clock driver does not support setting the frequency, so we would have to do more work to actually be able to use this binding in practice. --- .../devicetree/bindings/iio/adc/adi,ad7944.yaml | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7944.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7944.yaml index d17d184842d3..5ea12aac9d25 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7944.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7944.yaml @@ -129,6 +129,25 @@ properties: line goes high while the SDI and CNV lines are high (chain mode), maxItems: 1 + # optional SPI offload support for use with AXI SPI Engine + + spi-offloads: + maxItems: 1 + + dmas: + maxItems: 1 + description: RX DMA Channel for receiving a samples from the SPI offload. + + dma-names: + const: rx + + clocks: + maxItems: 1 + description: Clock to trigger the SPI offload for reading a sample. + + clock-names: + const: trigger + required: - compatible - reg @@ -190,6 +209,23 @@ allOf: properties: turbo-gpios: false + # certain properties are for SPI offload use only + - if: + required: + - spi-offloads + then: + required: + - dmas + - dma-names + - clocks + - clock-names + else: + properties: + dmas: false + dma-names: false + clocks: false + clock-names: false + unevaluatedProperties: false examples: @@ -211,3 +247,25 @@ examples: turbo-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; }; }; + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + adc@0 { + compatible = "adi,ad7944"; + reg = <0>; + spi-cpha; + spi-max-frequency = <111111111>; + adi,spi-mode = "single"; + avdd-supply = <&supply_2_5V>; + dvdd-supply = <&supply_2_5V>; + vio-supply = <&supply_1_8V>; + bvdd-supply = <&supply_5V>; + spi-offloads = <0>; + dmas = <&dma 0>; + dma-names = "rx"; + clocks = <&trigger_clk>; + clock-names = "trigger"; + }; + };