From patchwork Mon May 6 20:40:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1932158 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=vrull.eu header.i=@vrull.eu header.a=rsa-sha256 header.s=google header.b=a7+9CggI; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VYCwX71Tcz1xnT for ; Tue, 7 May 2024 06:40:42 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9820A3858D35 for ; Mon, 6 May 2024 20:40:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id CA1EB3858D1E for ; Mon, 6 May 2024 20:40:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CA1EB3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CA1EB3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::630 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715028020; cv=none; b=BbGa2El+HDZPR5qM79h8mmh6X2FvAlSANnCoe0qfAsNeyNjvYQ5YpLfdwa2dxhFjwqJQEkn4AvJKORyH4Q20cxt4JNgiDvZ+UHMozYimcJ049fU45M/T+d6gFaduuiZvBQvl+OBnzfXqvVid23y6CWGDyN9H1FocmXtijGCcdwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715028020; c=relaxed/simple; bh=je48o/yyTxwj8nIqN3zOBhdCCuLGXo2tUIkMFb3XoFw=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=QDwGp8d7RVraQxuf8xdhTAoWdcCWniKGzX3SL/lHZ15y/Dhafs1NSsm8VkDTvYwmECtAOEKXytPTZgAxto4FykCSmLIo56Esf3TMEKQn2Wh/Ljx/mrzI/gekmxRo9lW+E25nS//4HAmun8nTfUqd8VKy5s2DgtNPcGJcyL4NMaY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a52223e004dso501677566b.2 for ; Mon, 06 May 2024 13:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1715028015; x=1715632815; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=z50CvkodF/Kk4A8HRxZ1aov3gpKb4FmTJvTBPAZj7pM=; b=a7+9CggI4zqT/X29mIHDvDuFL+WBGlN95+Qe8QgR8gCa9PNIGLNvxsQLBDvmzljPet Y8JTVAaBu2XuhomZmvomAQfioAHxc9gsyQjwk7ZxRAKOU0jZYXtrNIphnA0nO/QOL94t 0R/c/oN5mtM+SLjB65+NcHqRD7R125rFOVqYQQrAhWStStYnPfzp1MHBf1Rs47zKms3u x+01aaCByZ0yUJ8YLEeFZta+M5DiLIFLZ1byZ/JRoP36/ufx+ZmPakj/708s95rWj/aJ K5FVQfe1RNB9sUQIx8LutDgRuEGUT9Tm0rPSCyXhjvDoXWB8d2gFjLsSe8xc0HUF9qUK 0Ncw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715028015; x=1715632815; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=z50CvkodF/Kk4A8HRxZ1aov3gpKb4FmTJvTBPAZj7pM=; b=ebnFbA+JR7Gj8r3dL64kaYu7Nj1msSZZQUsNqP7bZu8kSFW+FoWmx3MXL8KTfvkBT+ KdKECgrOhvvyVOtPz0Kp1qP+UNYqtqXEUCgfsnqz8p2kz6fZwvSIsZTZ/URagHPfZ/so 4fJKZdqWQdnelKByFqDlPS4+kk0xgtttX1IGarCNXP7Sio5yOI8nnRicyXlHWzRJ9N3G 9BX6sT91+5wH0uKbOu0xrTqa8s8GIoIKVa7WB8qpzoD/L8k3a0VlU2PZzj/9vZ5niV9+ tWgWyx+o1q9rpqsC8q/PRyxuco4Q36LMkFYy9dFr1QTMY1qXe1c20j9bopheAGANPiYU B6Xg== X-Gm-Message-State: AOJu0Yw2R8USP/pc5MMLlcopSnBzNZAoPRZBXrrUZvgBwBw1V8dYJQqv e4zX6g06g3sute9Urg8oF4DzmDOpv6CDUONXP4+B0T5KkzhJFncbwF4FFnf7kvN+RWlJcb/v5qt imE8= X-Google-Smtp-Source: AGHT+IHQIkJBefMh/X2lrcF/a3kJsMpi/JaDX1ySyaulj9q+kRxB8LZcUbVBmcY0nS0Hyi75zoxIbQ== X-Received: by 2002:a17:907:6e87:b0:a59:b9b1:a1d1 with SMTP id sh7-20020a1709076e8700b00a59b9b1a1d1mr7222943ejc.46.1715028015141; Mon, 06 May 2024 13:40:15 -0700 (PDT) Received: from antares.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id l21-20020a1709062a9500b00a59d578f0f8sm1211263eje.29.2024.05.06.13.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 13:40:14 -0700 (PDT) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Vineet Gupta Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH] RISC-V: Add zero_extract support for rv64gc Date: Mon, 6 May 2024 22:40:11 +0200 Message-ID: <20240506204011.3548562-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org The combiner attempts to optimize a zero-extension of a logical right shift using zero_extract. We already utilize this optimization for those cases that result in a single instructions. Let's add a insn_and_split pattern that also matches the generic case, where we can emit an optimized sequence of a slli/srli. Tested with SPEC CPU 2017 (rv64gc). PR 111501 gcc/ChangeLog: * config/riscv/riscv.md (*lshr3_zero_extend_4): New pattern for zero-extraction. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr111501.c: New test. * gcc.target/riscv/zero-extend-rshift-32.c: New test. * gcc.target/riscv/zero-extend-rshift-64.c: New test. * gcc.target/riscv/zero-extend-rshift.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 30 +++++ gcc/testsuite/gcc.target/riscv/pr111501.c | 32 +++++ .../gcc.target/riscv/zero-extend-rshift-32.c | 37 ++++++ .../gcc.target/riscv/zero-extend-rshift-64.c | 63 ++++++++++ .../gcc.target/riscv/zero-extend-rshift.c | 119 ++++++++++++++++++ 5 files changed, 281 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr111501.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d4676507b45..80cbecb78e8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2792,6 +2792,36 @@ (define_insn "*lshrsi3_zero_extend_3" [(set_attr "type" "shift") (set_attr "mode" "SI")]) +;; Canonical form for a zero-extend of a logical right shift. +;; Special cases are handled above. +;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb) +(define_insn_and_split "*lshr3_zero_extend_4" + [(set (match_operand:GPR 0 "register_operand" "=r") + (zero_extract:GPR + (match_operand:GPR 1 "register_operand" " r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand"))) + (clobber (match_scratch:GPR 4 "=&r"))] + "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1)) + && !TARGET_XTHEADBB" + "#" + "&& reload_completed" + [(set (match_dup 4) + (ashift:GPR (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (lshiftrt:GPR (match_dup 4) (match_dup 3)))] +{ + int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant (); + int sizebits = INTVAL (operands[2]); + int startbits = INTVAL (operands[3]); + int lshamt = regbits - sizebits - startbits; + int rshamt = lshamt + startbits; + operands[2] = GEN_INT (lshamt); + operands[3] = GEN_INT (rshamt); +} + [(set_attr "type" "shift") + (set_attr "mode" "")]) + ;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into ;; two logical shifts. Otherwise it requires 3 instructions: lui, ;; xor/addi/srli, and. diff --git a/gcc/testsuite/gcc.target/riscv/pr111501.c b/gcc/testsuite/gcc.target/riscv/pr111501.c new file mode 100644 index 00000000000..9355be242e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr111501.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-options "-march=rv64gc" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-allow-blank-lines-in-output 1 } */ + +/* +**do_shift: +** ... +** slli\ta[0-9],a[0-9],16 +** srli\ta[0-9],a[0-9],48 +** ... +*/ +unsigned int +do_shift(unsigned long csum) +{ + return (unsigned short)(csum >> 32); +} + +/* +**do_shift2: +** ... +** slli\ta[0-9],a[0-9],16 +** srli\ta[0-9],a[0-9],48 +** ... +*/ +unsigned int +do_shift2(unsigned long csum) +{ + return (csum << 16) >> 48; +} diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c new file mode 100644 index 00000000000..2824d6fe074 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv32 } */ +/* { dg-options "-march=rv32gc" } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define URT_ZE_UCT_RSHIFT_N_UAT(RT,CT,N,AT) \ +unsigned RT u##RT##_ze_u##CT##_rshift_##N##_u##AT(unsigned AT v) \ +{ \ + return (unsigned CT)(v >> N); \ +} + +#define ULONG_ZE_USHORT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(long,short,N,long) +#define ULONG_ZE_UINT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(long,int,N,long) + +/* +**ulong_ze_ushort_rshift_9_ulong: +** slli\ta[0-9],a[0-9],7 +** srli\ta[0-9],a[0-9],16 +** ret +*/ +ULONG_ZE_USHORT_RSHIFT_N_ULONG(9) + +/* +**ulong_ze_ushort_rshift_14_ulong: +** slli\ta[0-9],a[0-9],2 +** srli\ta[0-9],a[0-9],16 +** ret +*/ +ULONG_ZE_USHORT_RSHIFT_N_ULONG(14) + +/* +**ulong_ze_uint_rshift_23_ulong: +** srli\ta[0-9],a[0-9],23 +** ret +*/ +ULONG_ZE_UINT_RSHIFT_N_ULONG(23) diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c new file mode 100644 index 00000000000..ec5c2745561 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c @@ -0,0 +1,63 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-options "-march=rv64gc" } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define URT_ZE_UCT_RSHIFT_N_UAT(RT,CT,N,AT) \ +unsigned RT u##RT##_ze_u##CT##_rshift_##N##_u##AT(unsigned AT v) \ +{ \ + return (unsigned CT)(v >> N); \ +} + +#define ULONG_ZE_USHORT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(long,short,N,long) +#define ULONG_ZE_UINT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(long,int,N,long) +#define UINT_ZE_USHORT_RSHIFT_N_UINT(N) URT_ZE_UCT_RSHIFT_N_UAT(int,short,N,int) +#define ULONG_ZE_USHORT_RSHIFT_N_UINT(N) URT_ZE_UCT_RSHIFT_N_UAT(long,short,N,int) + +/* +**ulong_ze_ushort_rshift_9_ulong: +** slli\ta[0-9],a[0-9],39 +** srli\ta[0-9],a[0-9],48 +** ret +*/ +ULONG_ZE_USHORT_RSHIFT_N_ULONG(9) + +/* +**ulong_ze_ushort_rshift_14_ulong: +** slli\ta[0-9],a[0-9],34 +** srli\ta[0-9],a[0-9],48 +** ret +*/ +ULONG_ZE_USHORT_RSHIFT_N_ULONG(14) + +/* +**ulong_ze_ushort_rshift_51_ulong: +** srli\ta[0-9],a[0-9],51 +** ret +*/ +ULONG_ZE_USHORT_RSHIFT_N_ULONG(51) + +/* +**ulong_ze_uint_rshift_23_ulong: +** slli\ta[0-9],a[0-9],9 +** srli\ta[0-9],a[0-9],32 +** ret +*/ +ULONG_ZE_UINT_RSHIFT_N_ULONG(23) + +/* +**uint_ze_ushort_rshift_15_uint: +** slli\ta[0-9],a[0-9],33 +** srli\ta[0-9],a[0-9],48 +** ret +*/ +UINT_ZE_USHORT_RSHIFT_N_UINT(15) + +/* +**ulong_ze_ushort_rshift_15_uint: +** slli\ta[0-9],a[0-9],33 +** srli\ta[0-9],a[0-9],48 +** ret +*/ +ULONG_ZE_USHORT_RSHIFT_N_UINT(15) diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c new file mode 100644 index 00000000000..706264c8ff1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c @@ -0,0 +1,119 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Tests for merging rshifts into zero-extensions. +// u8-casts are not tested as they can be done with one instruction (andi 0xff). + +#define URT_ZE_UCT_RSHIFT_N_UAT(RT,CT,N,AT) \ +unsigned RT u##RT##_ze_u##CT##_rshift_##N##_u##AT(unsigned AT v) \ +{ \ + return (unsigned CT)(v >> N); \ +} + +#define ULONG_ZE_USHORT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(long,short,N,long) + +// Below "slli (16-N); srli 16" for rv32 +// Below "slli ((32+16)-N); srli (32+16)" for rv64 +ULONG_ZE_USHORT_RSHIFT_N_ULONG(1) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(7) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(8) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(9) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(15) +// Below "srli 16" for rv32 +// Below "srliw 16" for rv64 +ULONG_ZE_USHORT_RSHIFT_N_ULONG(16) +// Below "srli N" for rv32 +// Below "slli ((32+16)-N); srli (32+16)" for rv64 +ULONG_ZE_USHORT_RSHIFT_N_ULONG(17) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(23) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(24) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(25) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(31) +// Below compiler warning for rv32 +#if __riscv_xlen == 64 +// Below "slli ((32+16)-N); srli (32+16)" for rv64 +ULONG_ZE_USHORT_RSHIFT_N_ULONG(32) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(33) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(39) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(40) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(41) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(47) +// Below "srli N" for rv64 +ULONG_ZE_USHORT_RSHIFT_N_ULONG(48) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(49) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(55) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(56) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(57) +ULONG_ZE_USHORT_RSHIFT_N_ULONG(63) +#endif /* __riscv_xlen == 64 */ + +#define ULONG_ZE_UINT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(long,int,N,long) + +// Below "srli N" for rv32 +// Below "slli (32-N); srli 32" for rv64 +ULONG_ZE_UINT_RSHIFT_N_ULONG(1) +ULONG_ZE_UINT_RSHIFT_N_ULONG(7) +ULONG_ZE_UINT_RSHIFT_N_ULONG(8) +ULONG_ZE_UINT_RSHIFT_N_ULONG(9) +ULONG_ZE_UINT_RSHIFT_N_ULONG(15) +ULONG_ZE_UINT_RSHIFT_N_ULONG(16) +ULONG_ZE_UINT_RSHIFT_N_ULONG(17) +ULONG_ZE_UINT_RSHIFT_N_ULONG(23) +ULONG_ZE_UINT_RSHIFT_N_ULONG(24) +ULONG_ZE_UINT_RSHIFT_N_ULONG(25) +ULONG_ZE_UINT_RSHIFT_N_ULONG(31) +// Below compiler warning for rv32 +#if __riscv_xlen == 64 +// Below "srli N" for rv64 +ULONG_ZE_UINT_RSHIFT_N_ULONG(32) +ULONG_ZE_UINT_RSHIFT_N_ULONG(33) +ULONG_ZE_UINT_RSHIFT_N_ULONG(39) +ULONG_ZE_UINT_RSHIFT_N_ULONG(40) +ULONG_ZE_UINT_RSHIFT_N_ULONG(41) +ULONG_ZE_UINT_RSHIFT_N_ULONG(47) +ULONG_ZE_UINT_RSHIFT_N_ULONG(48) +ULONG_ZE_UINT_RSHIFT_N_ULONG(49) +ULONG_ZE_UINT_RSHIFT_N_ULONG(55) +ULONG_ZE_UINT_RSHIFT_N_ULONG(56) +ULONG_ZE_UINT_RSHIFT_N_ULONG(57) +ULONG_ZE_UINT_RSHIFT_N_ULONG(63) +#endif /* __riscv_xlen == 64 */ + +#define UINT_ZE_USHORT_RSHIFT_N_UINT(N) URT_ZE_UCT_RSHIFT_N_UAT(int,short,N,int) + +#if __riscv_xlen == 64 +// Below "slli ((32+16)-N); srli (32+16)" for rv64 +UINT_ZE_USHORT_RSHIFT_N_UINT(1) +UINT_ZE_USHORT_RSHIFT_N_UINT(7) +UINT_ZE_USHORT_RSHIFT_N_UINT(8) +UINT_ZE_USHORT_RSHIFT_N_UINT(9) +UINT_ZE_USHORT_RSHIFT_N_UINT(15) +// Below "srliw N" for rv64 +UINT_ZE_USHORT_RSHIFT_N_UINT(16) +UINT_ZE_USHORT_RSHIFT_N_UINT(17) +UINT_ZE_USHORT_RSHIFT_N_UINT(23) +UINT_ZE_USHORT_RSHIFT_N_UINT(24) +UINT_ZE_USHORT_RSHIFT_N_UINT(25) +UINT_ZE_USHORT_RSHIFT_N_UINT(31) +#endif /* __riscv_xlen == 64 */ + +#define UINT_ZE_USHORT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(int,short,N,long) +// Below "slli (16-N); srli 16" for rv32 +// Below "slli ((32+16)-N); srli (32+16)" for rv64 +UINT_ZE_USHORT_RSHIFT_N_ULONG(9) +UINT_ZE_USHORT_RSHIFT_N_ULONG(15) + +#define ULONG_ZE_USHORT_RSHIFT_N_UINT(N) URT_ZE_UCT_RSHIFT_N_UAT(long,short,N,int) +// Below "slli (16-N); srli 16" for rv32 +// Below "slli ((32+16)-N); srli (32+16)" for rv64 +ULONG_ZE_USHORT_RSHIFT_N_UINT(9) +ULONG_ZE_USHORT_RSHIFT_N_UINT(15) + +/* { dg-final { scan-assembler-times "slli\t" 9 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "srli\t" 26 { target { rv32 } } } } */ + +/* { dg-final { scan-assembler-times "slli\t" 36 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "srli\t" 54 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "srliw\t" 7 { target { rv64 } } } } */