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Sat, 04 May 2024 09:03:29 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 44493S50012304 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 4 May 2024 09:03:28 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 4 May 2024 02:03:27 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] aarch64: Support multiple variants including up to 3 Date: Sat, 4 May 2024 02:03:16 -0700 Message-ID: <20240504090316.2807467-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WFU6KAYJvg0Or3qjDw6rnRiJS8-VFeKv X-Proofpoint-GUID: WFU6KAYJvg0Or3qjDw6rnRiJS8-VFeKv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-04_05,2024-05-03_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2405040063 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org On some of the Qualcomm's SoC that includes oryon-1 core, the variant will be different on the cores due to big.little config. Though the difference between big and little is not significant enough to have seperate cost/scheduling models for them and the feature set is the same across all variants. Also on some SoCs, there are 3 variants of the core, big.middle.little so this increases the support there for up to 3 cores and 3 variants in the original parsing loop but it does not change the support for max of 2 different cores. After this patch and the patch that adds oryon-1, -mcpu=native works on the SoCs I am working with. Bootstrapped and tested on aarch64-linux-gnu with no regressions. gcc/ChangeLog: * config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Support 3 cores and 3 variants. If there is one core but multiple variant, then treat the variant as being all. gcc/testsuite/ChangeLog: * gcc.target/aarch64/cpunative/info_25: New file. * gcc.target/aarch64/cpunative/info_26: New file. * gcc.target/aarch64/cpunative/native_cpu_25.c: New test. * gcc.target/aarch64/cpunative/native_cpu_26.c: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/driver-aarch64.cc | 14 ++++++---- .../gcc.target/aarch64/cpunative/info_25 | 17 ++++++++++++ .../gcc.target/aarch64/cpunative/info_26 | 26 +++++++++++++++++++ .../aarch64/cpunative/native_cpu_25.c | 11 ++++++++ .../aarch64/cpunative/native_cpu_26.c | 11 ++++++++ 5 files changed, 74 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/info_25 create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/info_26 create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_25.c create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_26.c diff --git a/gcc/config/aarch64/driver-aarch64.cc b/gcc/config/aarch64/driver-aarch64.cc index b620351e572..abe6e7df7dc 100644 --- a/gcc/config/aarch64/driver-aarch64.cc +++ b/gcc/config/aarch64/driver-aarch64.cc @@ -256,9 +256,9 @@ host_detect_local_cpu (int argc, const char **argv) bool cpu = false; unsigned int i = 0; unsigned char imp = INVALID_IMP; - unsigned int cores[2] = { INVALID_CORE, INVALID_CORE }; + unsigned int cores[3] = { INVALID_CORE, INVALID_CORE, INVALID_CORE }; unsigned int n_cores = 0; - unsigned int variants[2] = { ALL_VARIANTS, ALL_VARIANTS }; + unsigned int variants[3] = { ALL_VARIANTS, ALL_VARIANTS, ALL_VARIANTS }; unsigned int n_variants = 0; bool processed_exts = false; aarch64_feature_flags extension_flags = 0; @@ -314,7 +314,7 @@ host_detect_local_cpu (int argc, const char **argv) unsigned cvariant = parse_field (buf); if (!contains_core_p (variants, cvariant)) { - if (n_variants == 2) + if (n_variants == 3) goto not_found; variants[n_variants++] = cvariant; @@ -326,7 +326,7 @@ host_detect_local_cpu (int argc, const char **argv) unsigned ccore = parse_field (buf); if (!contains_core_p (cores, ccore)) { - if (n_cores == 2) + if (n_cores == 3) goto not_found; cores[n_cores++] = ccore; @@ -383,11 +383,15 @@ host_detect_local_cpu (int argc, const char **argv) /* Weird cpuinfo format that we don't know how to handle. */ if (n_cores == 0 || n_cores > 2 - || (n_cores == 1 && n_variants != 1) || imp == INVALID_IMP || !processed_exts) goto not_found; + /* If we have one core type but multiple variants, consider + that as one variant with ALL_VARIANTS instead. */ + if (n_cores == 1 && n_variants != 1) + variants[0] = ALL_VARIANTS; + /* Simple case, one core type or just looking for the arch. */ if (n_cores == 1 || arch) { diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_25 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_25 new file mode 100644 index 00000000000..d6e83ccab09 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_25 @@ -0,0 +1,17 @@ +processor : 0 +BogoMIPS : 38.40 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres +CPU implementer : 0x51 +CPU architecture: 8 +CPU variant : 0x2 +CPU part : 0x001 +CPU revision : 1 + +processor : 1 +BogoMIPS : 38.40 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres +CPU implementer : 0x51 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0x001 +CPU revision : 1 \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_26 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_26 new file mode 100644 index 00000000000..7631baf3239 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_26 @@ -0,0 +1,26 @@ +processor : 0 +BogoMIPS : 38.40 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres +CPU implementer : 0x51 +CPU architecture: 8 +CPU variant : 0x2 +CPU part : 0x001 +CPU revision : 1 + +processor : 1 +BogoMIPS : 38.40 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres +CPU implementer : 0x51 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0x001 +CPU revision : 1 + +processor : 2 +BogoMIPS : 38.40 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres +CPU implementer : 0x51 +CPU architecture: 8 +CPU variant : 0x2 +CPU part : 0x001 +CPU revision : 1 \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_25.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_25.c new file mode 100644 index 00000000000..05c88a2edc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_25.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_25" } */ +/* { dg-additional-options "-mcpu=native --save-temps " } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8.6-a\+rng\+sm4\+crc\+aes\+sha3\+fp16} } } */ +/* Test that SoC with cores of 2 variants work. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_26.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_26.c new file mode 100644 index 00000000000..4eb943d5204 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_26.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_26" } */ +/* { dg-additional-options "-mcpu=native --save-temps " } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8.6-a\+rng\+sm4\+crc\+aes\+sha3\+fp16} } } */ +/* Test that SoC with cores of 3 variants work. */ \ No newline at end of file