From patchwork Tue Apr 30 04:43:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1929262 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=M9nQ/j6u; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=linux-tegra+bounces-2008-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VT6zl6mKKz23hd for ; Tue, 30 Apr 2024 14:44:19 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 26E6D1C217A2 for ; Tue, 30 Apr 2024 04:44:17 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 18413D531; Tue, 30 Apr 2024 04:44:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="M9nQ/j6u" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2044.outbound.protection.outlook.com [40.107.94.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64D8C10E5; Tue, 30 Apr 2024 04:44:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.44 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452254; cv=fail; b=CVuhtwZqYTKnAMV4uzj+1qbjG9NqzO9O4ZxVbh+XtVqANTDwSmkDIX1vJMhM2yIJ7sxr2rVcF2SN3fODx1fxE3Lpz2v2hDAJJPcVHtiTregeKGv5UZ1ikW5Ub7dMnoM2k3gf2F3gLui8Yom9Q+xwWTXjO/S+g3XhHao2NmZlvBs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452254; c=relaxed/simple; bh=RUEXEBxBFX8kKx41yMKJhUE7+bSHOUQ4G8xkPRlhCU8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XiZwpJkebU31mGDCvyrkUG6f7mTBnNkldNbSDp7bOKxS01yGrA0hYc2mSkvk7QGxkgoqlFbyaPCmIgvDLJIy/ycDKKqilxTdY2PWwJ3JuY0W+qEZ1STsWiUqtBl38NvdlHt2+mqoWXBtiOHs7JAz46VlOc/l69ex4Dv0gyg3Uec= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=M9nQ/j6u; arc=fail smtp.client-ip=40.107.94.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QDrYRY3Mo3ewPj8g40rIjckiHrUyV4yECG3zpIjTMeJiVkXcEDCNcK2ttnVPyEN7g4dFk6yI2flB2cATGtQo8yZCRmGx2syQW3zrcjpLr81WAHAY+X2ImWKD47UmoWCA+F+E2UzYMCZQq8s/FI91rIHmHCER8fhWgSO4/tORvQOcPc6xTY3mM4pi91Rz9515f3+fIUJVDKbbnqJphnO0vUoZfXfy6ozRjEZxYaEW8Rr4gu1i9GOWyXVJhVG6RZ5TIaVXF00RQf2Kf9bhoyTgvmDQ7N2Xx0+U6degtDtMao9/WDCGwOfCsnNDYJ0xxMKuBf0La1I2Rm48NrHyBFGjUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=r9vdxtBQLuqUDst4WxiLnMXs1NlIMnmBJqqg7uyV9Tc=; b=gxFbZOhILoEA78/KsfEknW6Dde13PtWRfq+9bSDexgTsJIAqJNi3Bd0obyqd93MP+agZEA/8DdPoktM+cTkLGqFBODcSQ9Jmx+uZ4YcM2F1BAXJnbS1z6yh7Rp3SUXf77nVOBcux/sYlGcpUZITtZHDVXAQm/ky2Sj2up0DkqUK8s7//mjPVaic5zxgZ+jUOW436tHaRIbeGc0rpeaF9atTG28AK6N33egohuEP9eIa7sgO4U7tYJid5JdTBCl+hk88F1U5VhhRBISmrg6YQ+uotdtyPnhTGYP9UYQLPXEx42p1I3Ym/wvflHkfVAPQvYxRc0TCYvTxLak/KOVJ9kw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=r9vdxtBQLuqUDst4WxiLnMXs1NlIMnmBJqqg7uyV9Tc=; b=M9nQ/j6un8rv5LPYFPn98TWKu1UcOTFfGGCr1XV2jIasy1v3NNkfTn8BdTDfAhaL4Dg4LjromSQedndwKCUf0wwqUR2wSTssJnJGK6CUAaukl51OUN63FnYVEvMtH9Z3inODHH28mI8lvV9nf1Uti5fNlcKC1wqQnKYQN9jNI5gTLwaCm2q7+oDdlSn6EbCbW4QetsKps0IZh9lQTUcqCUCGx1lgl3+vns8vA+hWo0S4k8ojOEvHbCxN0JwpIVVQvbii3KltXcfaiYwftCAjXpJmjwHWIAsHEleMhHyvXV/tPe+OH1g0pV5R8wEhe3BbCozpi+o198kauxFszr+rGg== Received: from SN1PR12CA0087.namprd12.prod.outlook.com (2603:10b6:802:21::22) by BY5PR12MB4276.namprd12.prod.outlook.com (2603:10b6:a03:20f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36; Tue, 30 Apr 2024 04:44:10 +0000 Received: from SA2PEPF0000150A.namprd04.prod.outlook.com (2603:10b6:802:21:cafe::d6) by SN1PR12CA0087.outlook.office365.com (2603:10b6:802:21::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.34 via Frontend Transport; Tue, 30 Apr 2024 04:44:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SA2PEPF0000150A.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 04:44:09 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:07 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:06 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 29 Apr 2024 21:44:06 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v6 1/6] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_issue_cmdlist() Date: Mon, 29 Apr 2024 21:43:44 -0700 Message-ID: <0acb55059f7212abdf4277a81e2f033127072bc9.1714451595.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|BY5PR12MB4276:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a0dd7fb-52a8-4faf-9a79-08dc68d02d33 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|1800799015|376005|82310400014; X-Microsoft-Antispam-Message-Info: Rx4WTYNxue3lIsV7X/f5SBQd6PAJ+lmnglWm/n4ak/FUvNk6fVQAyNAPTk7o6Mc4H1wlM/0ENikf1eG6q8/0+/gR0Xa+AQAbSE7AUWweEVr5SluXbDbeZkT0XdGG5eCndsKemYZNcUUTW5lmdh6X5FS/XhxFLJUlPB7gEwk3PUR3FSL5pjvIS2Bj+wAkMITA753HIsoL10Hi1ZAAyAsXPDO21tyz5mksyEjwxESVjwdIp204WFsIM4qitymRcrwIUx6q970GyFMB8khY0LMrF7RA41TSFL4Tz6Y1Ft2XX7brESPJczz/MYe1fQLBfYhkqD2YDDIzcstiCrvy3bZc9Ln1hGVwenaU7JAWdlq0vv5JYEaORMaWsyHDchU4OmwN3zwtPrE20CIW+DPf64e68Xihn3h30rPossZy9QxF7u8sZ4qDy1WSbBD4QZgIYAETC9TONuHtYrMOia3EnEjo+N4zea4lF6CAQhH+5UighFi6MGJH8mfJhxHc5NYYonfPSBZtnHlRouUrEGqqEXoSKDX66yq16LqL75NSYWviHkLgJMwiKLWOH3prDjYDQV8IsODIicAw4uj/zK5IRCTauZVIlaoX6Su9CtUqEgcrmUzNHlrPI+/SARfrJNd+AlkXVA7l09jpUtTELyhwtyRSFk9G/JPwv9jZzbNsj/UzpWrmEcANZQLNOvW7dniafAwL+czlgZ9j5RrYodeiQxX9kynqZsZQZ9YNDR3l4asAl4PmjanxCGAn7xCN15oxSi8In/mo6uSNIdmfgiLPCFANi4EyFJ59rtMQo/nv7UI+pmHHZNcMrOOB4HEik1U4qhXG2LVAq585NITvc0/1Yql5K8Y/9SiOOcKDXHS+qy4oYtTdsd//IsSF/VZmPDq6p9o7gu035Q+C6fEz7+lctUeMGEgjN/9mCs7Fy7u4LISteROn/g/WqSfGmJpJm0WOGb3IgrJtsDTaialzisTVS692NzfH4CAUot3Z7lv99EVbCcz5/nHp3uDsge3j9XpuFUb61fx+mZucn4tM2r5VDqi7CzqbqRgDvSlohhvLD6LO5icvkDOK7RaYeJrxZAU4ZXiRIcOmTjVy3aTI7d1J0JlWFsYln+mKV0jZWNrC5tjC6rYb9wHfkohwdNRCW2d/4AAk85jkAG6d9GercwFv3Jwij9uDkgTruwZ+ntg+adjV1wTIRDqzqwIX1caN4cNaNTIfthWNThh2a/H7V6860tpj4AYcflnSBrWOpJk9fRNMeJqCuSXI1ISyPLShmqot61LJ7OYlTTJfzrUPu1Mc3SlDurwhG8zY47vR/TS+MJHyXoRSgamYp3FtTpKhdWw1DBE3YS+TXMWlwP9ukE8nzx4a2o5xxaYN7hApu3mEFpJxTbtfyCJHwcUon8z4nI9yta5e X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(1800799015)(376005)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 04:44:09.9360 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a0dd7fb-52a8-4faf-9a79-08dc68d02d33 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4276 The driver currently calls arm_smmu_get_cmdq() helper in different places, although they are all called from the arm_smmu_cmdq_issue_cmdlist(). Allow to pass in the cmdq pointer, instead of calling arm_smmu_get_cmdq() every time. This will also help CMDQV extension in NVIDIA Tegra241 SoC, as its driver will maintain its own cmdq pointers, then need to redirect arm_smmu->cmdq to one of its vcmdqs upon seeing a supported command. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 41f93c3ab160..6a7e6b1ba5f7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -596,11 +596,11 @@ static void arm_smmu_cmdq_poll_valid_map(struct arm_smmu_cmdq *cmdq, /* Wait for the command queue to become non-full */ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { unsigned long flags; struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); int ret = 0; /* @@ -631,11 +631,11 @@ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, * Must be called with the cmdq lock held in some capacity. */ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { int ret = 0; struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); queue_poll_init(smmu, &qp); @@ -655,10 +655,10 @@ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, * Must be called with the cmdq lock held in some capacity. */ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); u32 prod = llq->prod; int ret = 0; @@ -705,12 +705,13 @@ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, } static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { if (smmu->options & ARM_SMMU_OPT_MSIPOLL) - return __arm_smmu_cmdq_poll_until_msi(smmu, llq); + return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); - return __arm_smmu_cmdq_poll_until_consumed(smmu, llq); + return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); } static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds, @@ -767,7 +768,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, while (!queue_has_space(&llq, n + sync)) { local_irq_restore(flags); - if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq)) + if (arm_smmu_cmdq_poll_until_not_full(smmu, cmdq, &llq)) dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); local_irq_save(flags); } @@ -843,7 +844,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, /* 5. If we are inserting a CMD_SYNC, we must wait for it to complete */ if (sync) { llq.prod = queue_inc_prod_n(&llq, n); - ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq); + ret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq); if (ret) { dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout at 0x%08x [hwprod 0x%08x, hwcons 0x%08x]\n", From patchwork Tue Apr 30 04:43:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1929263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=IA51PXV/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=linux-tegra+bounces-2009-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VT6zm519Tz23ny for ; Tue, 30 Apr 2024 14:44:20 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id A99CA1C218E6 for ; Tue, 30 Apr 2024 04:44:18 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B858916426; Tue, 30 Apr 2024 04:44:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="IA51PXV/" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2056.outbound.protection.outlook.com [40.107.93.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 017AB134BE; Tue, 30 Apr 2024 04:44:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.56 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452257; cv=fail; b=DajK5871+0rIZkQ9/PY8jIT5X55A4Y2Mt8aRZP0iaUskW8Q/rg2x8eGkh4CE3mluwkv2T3tNW2FvrH5gdgxYlg/GwkEKdr+p8iVb2OCGAaoSUB/1JSVij6uBCDE1oU5hjZtQ9yyfXs0VxQ0u/jS5IRLDs90zGmAeHjdEbsJN3sU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452257; c=relaxed/simple; bh=R95Zd8bG5nyFySlHcpcnTrq/y5Z2MR8BA2caSbxp15c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iSCqhIkgFzn+bwHN/t3Xc6NDxwL0XM/eHUNSGX6VJm0LS/dl3vRZWta3wEXvqgtGxzfxvl6nj5/WqnZxtcZVAGRLQ4kIkl06wMER35oAQKj24JBm67uXM2Hz8IWF/4aa+dHhd4Ky9IUnFBE5nFPCnpfcKZ4vXNKtjuXKTCX3cSs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=IA51PXV/; arc=fail smtp.client-ip=40.107.93.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bTo/HmrjJrX5i2O+MtFHvtFBgg9/G4AhioutfN5ayA5F0AuHcTiMe/4P4Rc7Wga+4GQXgXqQwDeOkLvR1ABfOjyhiHe5yAzyiiSwI7HU+EN99ihAtF05YdkdO3ACT9NxYqIrPei9C6frIVQWUl7ZwinJWB1mNKJYWd24RfcrHmAGrf7G0kuCcFoA/oK4uDTF/4E9tonSihA7cuRDWh4iK+QglTIrnXpPCK3/3W6ZGIesgEjT4domnPvHnJs+eBV/F5I0YlbTYrrx4jzKd94T+kvonv5WAS7D9Adys3yO6+qS8RExXdCCArMqtd7on0KbVcULfaYKElJn+rdIDdW6/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Gs43R8bMby/zdQZJF5aoXuNZ1WrhEw/OV5VOXDXs3S8=; b=mF2y/VPeiiCg/SuX/KGGAAhV56kK0Pcd/esNqtCeWWR1owadV2q+J7Aymwtim0CNoBWOVL6oWoUC/E0vlsiy+nvBLvD/k4xC/qpdU9P1hR0Ci10jSeXBnIdZcZ9c+XdWuToti1m2aQGJrazkpOT3emqYid98Cf1cElQ/c+9lbg/MgGRDztv6v6ZFCokgOmsa06kfCJyS6pj819waAdnn5XeosFjog2Yq9bo5KP8EpZeMpkTrqt5zwx2OgEiOqC+OF7XmtghrsARfisQ/0nMHgat+ObS6GghB0/3L/T6MEfQGWPz2PQfM4Jd9uf4HNIgIy06f0Z8AJDrXOTpj54rvkA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Gs43R8bMby/zdQZJF5aoXuNZ1WrhEw/OV5VOXDXs3S8=; b=IA51PXV/DYxQYf9A4UdBAy8rXnqn0HkBWz7IVKp/ySIZxP0MQ1+s0DSdfafeeUbPBvbF1aGXRFDDSkZ399iUBcJc06TsEyBBu7SfCymUhHxFjmCubH0gOmydv+goTgqeLSiKBZbqNUuA2JhXeDL3+P+HwAa5TB4hsYOPkUXi9Wb3URfxrkFUMPEyKv0FradNOFwTuotXJf+guK6ZsAgdeaTpftZpJG9vJM+RJtbP1kG5gGqlqOyEGwPEJY9kdWj9O7c67GyScPA2vJMZiV7Yy3MKOeSN0sfjGT/WBz6bkWYgqdzKdHRi2XBo/HMM9mAytxXDUrf/I2xywMlFrzJUAg== Received: from BL0PR02CA0017.namprd02.prod.outlook.com (2603:10b6:207:3c::30) by DM4PR12MB6566.namprd12.prod.outlook.com (2603:10b6:8:8d::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.35; Tue, 30 Apr 2024 04:44:13 +0000 Received: from BL6PEPF0001AB52.namprd02.prod.outlook.com (2603:10b6:207:3c:cafe::bf) by BL0PR02CA0017.outlook.office365.com (2603:10b6:207:3c::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.35 via Frontend Transport; Tue, 30 Apr 2024 04:44:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BL6PEPF0001AB52.mail.protection.outlook.com (10.167.241.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 04:44:13 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:08 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:07 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 29 Apr 2024 21:44:06 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v6 2/6] iommu/arm-smmu-v3: Add CS_NONE quirk Date: Mon, 29 Apr 2024 21:43:45 -0700 Message-ID: <81d79f51c69604a38ea4f72c8ac2c573c52e8609.1714451595.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|DM4PR12MB6566:EE_ X-MS-Office365-Filtering-Correlation-Id: 70bae28c-ecc0-41da-730c-08dc68d02f14 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|36860700004|82310400014; X-Microsoft-Antispam-Message-Info: AYcFc4NQhCc2V7dyelOnH3moc8d46NG2E0pi/UEW61LSl47+QMY7h1tvHXhA56NZu8yhWLydOujuHdgiH6wzEXUX5v5WfxjysXGSsHE7OJ+yTLEfv8xuVx8nU7pRXLcY8AqE5gFcw7ts2pSL1FgwFOndFWuDlUa36kTxa5phBdPE7XsZCPLJpggQp/0104ilWUV1Xznh9LQ/927kgI/BC58Z0ej+GgIPoG6KR96RR6sa7rQfYAldu8HaYxqlED5RlS2GorJD7qnHy4qEg1Im0YYPPoMWj/X1rr2m81xvy2GupCw3C50c8FwiXxCZJax0/Y/WEV5qlB1mo0Ah4RiWNQ15UPxP4nMmySnlbNoffSEuaa3pfih/XcU2Xj7KJLTSzlTD5C8q0EzxJ4hOkci/JngNrRJ13OKIu0htWb2D77CrYRBvTx1z8C+czquKfTgNELQ5rrBYQrqhWyCScmAtrVoucvrcp1m1RVhmrAEyYPhNZOC/8cZCUoXlIcOo2qJA8mCUe7+FcvFVNUy9iISmvm0lxHYSUs06C58glUo9sOAuAUCN9lYewwC7Ze41zvOF9LOkHkbZN+MN61rJkf47SPKmTREVi6udH3Vv17Nb8z3Rb3v7V4iZSOK0VZtiiQpKEsNpRbExiqV25KCUvqQDgmF/WK7oBluJbfHB4wPBpM1h9fFE9URwWZdiW/HE4IccqNSAiJrRt8rBRKFudGcViFkLB9gGqTikd845scfgpdYSW9aoS8KVN5EocQR7K0l0ixjKCqS6tDGnYXO9Xx9RfWWya/OBQ20/HGCfreDb5L6SWPlX4vqG0f/q6FdktNjH3GGc+B+EbUMWtvOut7O3KYVfmophlvVEv4+BGAaOJiyomcxW3dOWg+cWtjn/NokXXE5yMgGWGJaXco0PtPcCXtD1EFlty/cPbtdpGAmP0D+j0yXAsSBMIgo9rFsRDMYY0rIn4RCfCUlXPn3dGy0jcUV3FTZohKBoNvzulkTrSzzJuJVMBBfr2Hl9+Arj5+uWW4SCdgCh4GNPqFG7eP74GD0SH1dnuqaalQCy2ogL/gvaO9m1tlG5tG1ZyM7E2+y98fPFvlMowxGD/mhMqoWFH4GJZL2LOjeP4XBKRdm7kvhZzTtdfim6C9waXZCBfn5sQDOFgDTcxDwFyhtzXLAEHWH1UQpIkG5mtvIphwe5wGf3J6Bqp8Yq53LgsB3uMH1qOlvQx9v/L8v1ipZW/kJlpkGMTisyep+3ovZxmPvjTAB1VOD/i1ZEWB/NHH2tnDG0maagycI/KUq1Q2cFHblNzTCXbNxRk/GYhbod3WWjbrRR5EYlSuaGL4JnA2W7F31s7UDBg2CNj0VttfVJ8JrZ6s5wgbFQf1QGVsRcbhi1r1RBfzKJGfO4pcFkd/Df5k3T X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(36860700004)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 04:44:13.0092 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70bae28c-ecc0-41da-730c-08dc68d02f14 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6566 The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a quirk flag to accommodate that. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 6a7e6b1ba5f7..b3d03ca01adc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -334,7 +334,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { + if (ent->sync.cs_none) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); + } else if (ent->sync.msiaddr) { cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; } else { @@ -371,6 +373,9 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, q->ent_dwords * 8; } + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) + ent.sync.cs_none = true; + arm_smmu_cmdq_build_cmd(cmd, &ent); } @@ -708,7 +713,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)) return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 2a19bb63e5c6..bbee08e82943 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -510,6 +510,7 @@ struct arm_smmu_cmdq_ent { #define CMDQ_OP_CMD_SYNC 0x46 struct { u64 msiaddr; + bool cs_none; } sync; }; }; @@ -542,6 +543,9 @@ struct arm_smmu_queue { u32 __iomem *prod_reg; u32 __iomem *cons_reg; + +#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */ + u32 quirks; }; struct arm_smmu_queue_poll { From patchwork Tue Apr 30 04:43:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1929266 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=byI4QFNi; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org; envelope-from=linux-tegra+bounces-2011-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [IPv6:2604:1380:4601:e00::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VT6zr3pVvz23hd for ; Tue, 30 Apr 2024 14:44:24 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 8A0041F22780 for ; Tue, 30 Apr 2024 04:44:21 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 068A016426; Tue, 30 Apr 2024 04:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="byI4QFNi" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2072.outbound.protection.outlook.com [40.107.100.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4102017579; Tue, 30 Apr 2024 04:44:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.100.72 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452259; cv=fail; b=m/wp5uNO5wjEFb7lxPh1XGhBJM167pjcEdEfPzok2sHrFScDIo1iBcyII1dWEvH3PAcrNvD++3Z7Q6wU4akb5F9DMO4+tmWiNoJSSd1qoj0lS64khZPH43XifwBUOUn1DuSR9mZGlH/PRqY1+s6i3cPa9qHxax9g71JvdFtvVcI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452259; c=relaxed/simple; bh=7GRMnSoAVa9s3ommmdVF4t+GALXXFBZ2E7Ck7pimUwo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tGBnLNgFmXTdqSJ5vmTAeZAoK2V8yFFZdGSyoA4+PpxHkY1pS/9u9VBTOVUY48fmP3d100h1qaRaclF9VRbacwg0V3jdtUP55w32m0oku0+L7KRMW8Y8emRyKzBTqUGzVLyyWumN5EAziMbqhfmJyQj6THmDzXN2Z2Zczhw7nik= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=byI4QFNi; arc=fail smtp.client-ip=40.107.100.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WX41tnklJ/oU7KAmiNEe97LhatZmKokZAHxlWx7p31CceoyKB4ClvDaQD+RVQzPvYqsz/dW2yEh8FdI8Yxp3XFT5f+EH83GuaCWJfrW+PGU6n1sEXXpPzloFcRZ4RdVGRhIq0Q4N9ar/rbGL1Rt9dJySU7qHVyWMOBwMUVTkVQ5ynHXSJvJTKUFnCIfTxjDfELWE0IXFP8wN/U4Sk7Fe07leXKWMH5i1ErW4RttFetR9eL0l6EOeNo9+RdVKF4324yCsewpAmTKm/yrM/cdKEpjcH4q/EkgDk5TYh8Oo8t4hIf4mSJD+XxKr39DxBMlyX/ef6kyoRyqi3vgTTf9SQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9FRamK4114oAevkftuz6mFt73hVOGyAH5y2G717pUck=; b=Fuw6rbCx4Qb7Yujdi6W410PPXY1S9vxBZf4ng7D5T/jHDw53pasr2N6J3BBSnobRCpKYZhMKk3oLKNxkdaYrbyCxn3cd391Ty2MCLCyf5jske7E2JAvyV6Qu2qB/QV2513+Cwpqb7TwYbDVki86bEVAkK4HhE0I7Apiv6E0EfWdUoZU1/S6mnmPR8AjrN61s6IhTI7PAURFwfOs0IvLhDv6ojq6Z+Fgk/uABFdsCf+tvSrwzqP7KOFQvCjxfJY71/G61oFaK2kaR+7lA+je5mCm/SvsYUekwgw0+Wme/mzN+zCFvqHtYbwwbK05Pa7GJlTdkPsjmSveUFj7sPLSYTQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9FRamK4114oAevkftuz6mFt73hVOGyAH5y2G717pUck=; b=byI4QFNiFRthxfv74wdjKDFt/VZi9iV6OfMXQcxWOwLdr+giHZn3IyPA7rdZ8a/P52+x5HDzNkb8DKkIqmUaHo4dePN9b7lyx3xvAqFUOmurhIRKOkxxuvLQk+Mlyc8w0KZNWuB6yPOTzOqh3GUSR/Sn+ylEZjoGWFsl1w28OG/RSMKkOtzVF14hOO17hKmGWdlorrZZebuS2BX0A7FkOndm3HUKL0dVIcc56b4jrZk3qah9f7toOcr0zPf7rNzSQkwoYYiuU4sQCoitiLRunM/BdtA8wbmkTw+Hu5wv2EeHQrBkBMp7ZZ7o6mo55BVfM/+PDa4oHIEG7hQisTeVcg== Received: from SN7PR18CA0012.namprd18.prod.outlook.com (2603:10b6:806:f3::35) by PH7PR12MB7114.namprd12.prod.outlook.com (2603:10b6:510:1ed::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36; Tue, 30 Apr 2024 04:44:15 +0000 Received: from SA2PEPF00001507.namprd04.prod.outlook.com (2603:10b6:806:f3:cafe::64) by SN7PR18CA0012.outlook.office365.com (2603:10b6:806:f3::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.35 via Frontend Transport; Tue, 30 Apr 2024 04:44:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SA2PEPF00001507.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 04:44:14 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:09 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:08 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 29 Apr 2024 21:44:07 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v6 3/6] iommu/arm-smmu-v3: Make arm_smmu_cmdq_init reusable Date: Mon, 29 Apr 2024 21:43:46 -0700 Message-ID: <47a2ec844ec42694872d3c3b1a09f1b870712f78.1714451595.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001507:EE_|PH7PR12MB7114:EE_ X-MS-Office365-Filtering-Correlation-Id: 1cdf2d1d-12b4-440c-c178-08dc68d03004 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|82310400014|36860700004; X-Microsoft-Antispam-Message-Info: GJ10XDkzhv9XFd54NBCw8CCJ2/hLTcxZ640XjbpOJRM20G8T3WV+yjIUZCUmQI+odSkE5nbhVUizw2uspr/0ZxW/YUwgHeHG4si1fU5gvsCPnnWx0G/6pVJRqBjDSCC+RjZcPvY19wM9UmIrjPYFrudi3wLTwIm/ck5jS9dd8pzIfjBi/Rj0wZz7QRSuL/kBUcUlBpnwOkmrdzNdHy+8EUsQEWuPkeyfLGic/ThrtDXv2LoQsv6NYkBiVcX9SZS9dZSGaDvrzjg5SCNdert5tBM67mO+ROlRJ1Aafd5GqMK29snQqrf/7ZYsdE6PtpTjY3y2gWd5LC7GrKvLvyMOGWAFfhe/Cedxa35qH3tEpmvwTSwEs32VScMTS5MC2H87VseKXEcMOuhcROsxGEtGZ/Pt9CV0USvMqG1Ym/iKo/8xOS0ZSpxxt9b41g0LcGSS31gGWJSrmzNEc7aYDJplrQOqxPlPYGRFTy6D0Bg3lDsiqAVujjhdzWOsSg3ZH3YXXHOejEc2Qwr4+uYKoA/w+WBuM3VVyDfvJQdefLLNX78XNZ78g5nQpAl0xHFZ9ctoFE7eSG9QjYRLigVSl+NhCVDqnR5uGNNCKXRdXuqudw5JqjXJTFAIrLW/GgLhVGpPlb55FHHADzHz2Vwx9asFB92F1ZtJfT2dDS7V/YrARpkhR1AZ829ZVt4vKhCQFB+EAZ0FKWulJu9ZYu7yJj9D/y0+G6RLaddLzI8JFikicEvseMhfxi9KfLENlCd5Uz5ZqQA6OZqQW2QFw2dvnOfGd0KFTvkeGesQHUiVFopfrRACv1p3X9lupEDeHp1dVE4WHqvvZjy3YaUVCaOpr8J5RJdkOOIae01R/4kIAQpfxNeuFE22INRmiUPy/cDUJfin3HCTAl/aQ8L3lsBdpK+6+bsCsYBWXuLawKGpIx+xLsn0XXmgMeJ42mVmO3FuVldyB70x2OZAvbdklv32u+jRqed+/e99qBPVZZSPaLsiv5koC68dsV4J0Ce9W+D48oqVEXmf2/tyFXTCOfZGF0ZRCZrmvVGdXRB8kt2blcYO60XfFXy9cWIm/QQZvr0RES6cgbyEgG1wUiMdlaFGmINVazb1/XBmhP3k38RfgLgVvjyk7tyepB0RpGbqV7MSjNsSGm9RYxXodcNMIKbhS2M8qh9dRunumzIn5Imc28gdv/tB7ImKZbX3uTt4Kl/X4ld1mQbkHzrJdgKlyT75Nm7BSPsNZwqfzg+YH3ax1hbqI6H2ZB31l8gl6PH9Mak3jJJA4JnnfMCO8KQlDmrv9aLoTN/cUpQSCs9yIif8GRlIxxERvAwfDkA5ZSxqS9amV6UWVHvx375EwFrsCKtmK97NeFp7ME1H7Oz+UuJ7hoNjMjrMQZ7fZ53+y5tSDNoC+tcx X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 04:44:14.6620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1cdf2d1d-12b4-440c-c178-08dc68d03004 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001507.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7114 The CMDQV extension in NVIDIA Tegra241 SoC resues the arm_smmu_cmdq structure while the queue location isn't same as smmu->cmdq. Add a cmdq argument to arm_smmu_cmdq_init() function and shares its define in the header for CMDQV driver to use. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index b3d03ca01adc..538850059bdd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3145,9 +3145,9 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, return 0; } -static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu) +int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) { - struct arm_smmu_cmdq *cmdq = &smmu->cmdq; unsigned int nents = 1 << cmdq->q.llq.max_n_shift; atomic_set(&cmdq->owner_prod, 0); @@ -3172,7 +3172,7 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (ret) return ret; - ret = arm_smmu_cmdq_init(smmu); + ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq); if (ret) return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index bbee08e82943..ab2824e46ac5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -760,6 +760,9 @@ bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd); int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, unsigned long iova, size_t size); +int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq); + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master); From patchwork Tue Apr 30 04:43:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1929265 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=ZCQMgY9U; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=139.178.88.99; helo=sv.mirrors.kernel.org; envelope-from=linux-tegra+bounces-2012-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [139.178.88.99]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VT6zr4tlRz23ny for ; Tue, 30 Apr 2024 14:44:24 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 450792841D0 for ; Tue, 30 Apr 2024 04:44:23 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D79DA1946C; Tue, 30 Apr 2024 04:44:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ZCQMgY9U" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2060.outbound.protection.outlook.com [40.107.212.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 317BF18628; Tue, 30 Apr 2024 04:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.60 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452262; cv=fail; b=dT1fjgyRBD3bH0PfDqEpfBJiciYjX3JXujTO2xtqfCzRXyXcCsWDwKTFompd51SN5mAL7xX9ajzTq91KbWfbQHqp1qTlWkUAXv+LoV1gm8DjNA5QDx87bKRiU0f2fLraDYkxwDySSgffly1Snh6IAqleFhz5nPtGodlbYjz2YaE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452262; c=relaxed/simple; bh=+pmV/WlftSoFWSqbXrnh/dMsj4JwqxsRhryvupZmIP4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h6Im7Bddbodhfu48l7wB1UowtYmQKGvmBqCou0sHr7wOYyN+he4MEX+K9mtwfUpic99G+f+n7PM5KkwRtyLePJy0ipCpLQd8Hp8/k/OUDlHuhkU9U76WizLfQA7v4LYwFglOqew9D8gJNSMCobg+d8Te5Y4CDwVqXOS6lqUCCIE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ZCQMgY9U; arc=fail smtp.client-ip=40.107.212.60 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=H5UV8Jb/QPFjyf8urXStPaq3ByDpjThTA0ZqLAgtt2JkPuiZac/ff3AKs9hRG9jqR/E1V2A+oA5NezeUVloGqehE2IZYFutC7TrLKP8hHW5StKwXwJZxNflw4sATxV9XHg/+0d6rjTQENRp+1DEKPfemoY+TYPxJ6YgOsnsdlEicloI8Zal928sOKih+L4pvmSLk7clmackq1///nFinGNTF5t5GNoEIsbQ2sbgthdqcGLs/W5ol4bFGf+udQXvpDTRiaEm9evU6fN8Vk6TQyCRQAU6g+uFEKXFicKiqtd2ZUtFEW16c2/DC2ECIeOuxQFrDTbf8DGqv0g+iess5nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QtcUhhLLQlhwUHWp3E5qNVm8dfY4E8/bzO8zqI8jEZM=; b=EI8r29n+31tYsReNXweYWz63P5ymCn2zy5Prmn9uUkur8IXXyAhunTZLJXEq+p9vASP2hpD0I2LzaaZhCJldWHVmZQAEStfrZRolH0m4RMLlSBaOTBPLLvUYxLapNqrdJGCTq24JZdzzxQNL9XxiPFNgp+s2UmzeKKdOp+Dbf8dGaxEdXhz1ssoC8HVxbaa/W1QubOoZC9q5YXeY1Z6TUaZAn05AhEjaQxxnjRCrGtRGmIQBlxsxUIws93LsbLq0M1TWDiHw2AjBNpmzpb2rJlGXPi3BDHw/bZou3x/O+ycx2Q+Uv3kbLoTf1HUrVrV4J5/mb8ZMIHUleb+QPWzauw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QtcUhhLLQlhwUHWp3E5qNVm8dfY4E8/bzO8zqI8jEZM=; b=ZCQMgY9Ug09HN7bP1A/kpIgebqLOQ6UqkftoY6wBsXYCPn//gXq1yoU5AZXTUG+ziW8A10ibSFaUEAAzjbBxQQdt5khERA1/WzCnfZS79GBdyfILgKT+JdVvI2nMqCvZRh0bQ20lJGfylfw+UbdDCXkGtymBtnuONIkLIEClA8CBXixFvRm/Pb9ncXhcelqfa65cQ045U/6NehrxAJw+Jmqo878kllQztSDIu/61URcKwb/HmwBUS7Uue2pZB1/Ua+tnMv/NjYbxFedgCJFRE8YfLQXY0B6p/lL6ZmY/Ta90cjypScyoG8BaYQb1codHS6B4Q7VqJTReNy46FjMQVQ== Received: from SN7PR18CA0028.namprd18.prod.outlook.com (2603:10b6:806:f3::11) by IA0PR12MB8713.namprd12.prod.outlook.com (2603:10b6:208:48e::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.34; Tue, 30 Apr 2024 04:44:17 +0000 Received: from SA2PEPF00001507.namprd04.prod.outlook.com (2603:10b6:806:f3:cafe::8b) by SN7PR18CA0028.outlook.office365.com (2603:10b6:806:f3::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.34 via Frontend Transport; Tue, 30 Apr 2024 04:44:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SA2PEPF00001507.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 04:44:16 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:09 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:09 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 29 Apr 2024 21:44:09 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v6 4/6] iommu/arm-smmu-v3: Make __arm_smmu_cmdq_skip_err reusable Date: Mon, 29 Apr 2024 21:43:47 -0700 Message-ID: <25150aec77edf5590bca81f4a418ef1ee7b21952.1714451595.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001507:EE_|IA0PR12MB8713:EE_ X-MS-Office365-Filtering-Correlation-Id: 28fe10a3-34c9-4bc1-fac6-08dc68d03167 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|82310400014|1800799015|376005; X-Microsoft-Antispam-Message-Info: n/Kdb8WXVZNRMTCZX90cr9RQCNTw2j8IdvHEYrn9cbkETUtc1SdErT78EoNBIsHWIJL4PeF2Jm0QcnhkCydHEi5v1t/FdDhvGcaRVTHY0Du5uv+SYK9GISFT1LEiqkXceAUzEQsBsY3aGiHoeVcca/SbyZO65KuIJS98hFEAn9sQ0RQmBHadDOA4Ddynyq+2aafA7xRsc27umuStPasfIVxY8xyULG2GoSg7KH+X4b6R3l9oVvCttFsPWkKLQxgKCIEgIRhLACceujDYeOVHx5iL/so3u8CntOBm14D6noWSDbJOkHsx0wlcj/veqfIRj0nErLsKng73jG6d7S8KMQW9oxJilYN3GipG7+w5XmP7kn4W99ftgn4QTeK4sRlBsvxnIbZDyL97Mb9jUiLdDkORt6ARHcv9qc/eECX2c3fDLRLmRIsyivMR1yAxk63eXwis95937HvtihZabx4FpvY01x4n5+2kIqdnUJJVeuH7QlRTyRNkPMsBf7Ai7J6lnK/CW7uOoi6MPGcFQGM+dKuWUiZjVc/kQJNoYKdAys1Vb5H1QBTRRRiK1Owfd2cydfopv5J4CJOmSXyePmXxdAE5VltilvAhrSZz+jR7CZ1/3aD/19IvLvm/DuuRAXDsDVYa6+/T8al/uQWt2532G9LMN0S/KKFGrCr3cvsgVMwNlhJbVDZ7EZGeOidaCfOYvyZoXykHw0wfnd3OAcrHvM9rjsvGxD53a98Tz7fkgWWh/xyuZxuyU60awyeJ35qC4qGVlcypR3yod01aQm1ue/hBEtnIxbfnFbdD8ag8ncWIlvQTj27/h2IddccJDMl9YnJMx5dwDPzGdNjiMogNZp9Jr5NUxc0q15Ez5MwClocTf0p16yEmmAWgISqhARRoIibbDqU6wjLltwAPsmLvcPjOo2ANPxG02iQYESU73Fp1kUvCmz68ymCi+PFldSTxarXDf6XPLiIgKGMpSTu1iab0SAFgXMQ9CQzJTHO6Go2tRAieuR7vGuilEoLJQvijn9OVBU+N193WDgINs+QE9DBSEY/pDnxO7tZLMdFdOnrqAyQfB7qtTZzYY8xfeQN2Rxk0QAc4DDCcXBRDza2RMI0hR3KdrSXBjLu6KA5HlNwrWloHGtGLsA27hXwIXmbqrGwF6SI+QyadQ4r3Cbv65LhLsKm6EZ2cKmBabIgxFMWU53bijR2t3zbVkWZfG5L+rjxjmNuHK0JCjK/Oo31Ubj7JJGj5qVE7h0K/NLpsWCMIP4TLCjKP8KQP0aEeSbfVR4HT7x3LGwM9LRtuUlmo2yB3oyBuaIgMBGohSQH4xumUftPHIU7ToeZYIWXl0cJf5QhoHvTkEHhTcIv3sTuAfIfm+cGEd2Jo5XSO6qWc7rTW2xsjDWGjUgEuw3fE+dI/ X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(82310400014)(1800799015)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 04:44:16.9902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28fe10a3-34c9-4bc1-fac6-08dc68d03167 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001507.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8713 Allow __arm_smmu_cmdq_skip_err function to be reused by NVIDIA Tegra241 CMDQV unit since it will use the same data structure for q. And include the CMDQ_QUIRK_SYNC_CS_NONE_ONLY quirk when inserting a CMD_SYNC. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 538850059bdd..5111859347d5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -379,8 +379,8 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, arm_smmu_cmdq_build_cmd(cmd, &ent); } -static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q) +void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -428,6 +428,9 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, for (i = 0; i < ARRAY_SIZE(cmd); ++i) dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) + cmd_sync.sync.cs_none = true; + /* Convert the erroneous command into a CMD_SYNC */ arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ab2824e46ac5..32e7fc5e1794 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -762,6 +762,8 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); +void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q); #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); From patchwork Tue Apr 30 04:43:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1929268 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=KCYGo4zm; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org; envelope-from=linux-tegra+bounces-2013-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [IPv6:2604:1380:4601:e00::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VT6zy61kqz23ny for ; Tue, 30 Apr 2024 14:44:30 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 4F20B1F2297D for ; Tue, 30 Apr 2024 04:44:27 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C1C2817579; Tue, 30 Apr 2024 04:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="KCYGo4zm" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2047.outbound.protection.outlook.com [40.107.243.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB115199B9; Tue, 30 Apr 2024 04:44:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452265; cv=fail; b=sxrLnbWxUy3nv6h0va8wwhBhsSKTIOaTtUNkfGZUXZsXumsTjDGs0L1tEL+xqC9szlcI1q/0e9MF/9aOKMJP7mOEjPXg10UyeT5TQZn59tZT+jSapmLyClMpLBqPrs8PRzIkNY+Svd0YX9iIVzE/EixQ6EKoDEEWnTjjw6gr3UU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452265; c=relaxed/simple; bh=qRIqctcipDp16BDY2JyySLjuJcf5i1ahgSle6dJHHBc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H1NtvkT9FDo1DcVanUWg7pIM/8TQqczRRlQKuYIBoXL+W52p7pSa00LsdFffaPEYnf4F2JtTFN85hqg35CuJ0UbscpeQnEmKNHb0rsAmpD/1/RkCMH4tzA++iNu02jrtKRTl50PnnmslOwiDLfYJAknaPVDPvBNmvt2OVIeb4GY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=KCYGo4zm; arc=fail smtp.client-ip=40.107.243.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Gbli+fOZBI4ekS85HBtTJpuwrGNs4aCarZ/QT7VYtdJTbZo/57hmYPrEOIFlIvYclAaU/vhrTcmJ/KYrOydx41ILYw2tjyCLTbzXnQ48AD0lat/hP7wz7Q4cAVUKUbHvncH91K4CCUq7/NRFUz7j12tm5lUD45JforRZ1+v1kE4DlPEBLm69b0MHQHr24qOKtNizNKQFGRpP0etj+U75Pn/M/Wl1haRr7q6NyEhuFyfbD9xdNfjX/hVJQJbGUzZT7MYE3k71BT2fkpsmX61ZljIveFNqKKp7XxapzK3yZans2JCd5aLVH0ORSC0VQoG2nLy+REgL56+KWCgymsayxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Gm1nddAd8qPxUx7RuWZO+6pSj1/u/fHRDeGHIT6kVMQ=; b=jByg9g6rxF+faWbXjJxqdQM6dISNXK0Aw9b7KNKH8PAPE23fDFBDWfJ9OkQXvnHu8Utc6M6i1p7Oh7tWc+5p3CQkX69y8+HyQ4hnEdtzkdkBqwi7VFxtj67YI3BVTCENnb0VvZ83JFBxlWESswJVf/B9yYUs9nIk18aYubRUu1iEu5yGxq86sPbYHu2JstXn6UvKab3YjMDzERpjHbUqi3DvHLtKf1e96/2PEpQTfxrvJfb7Rgjg/hKquiKy5ANr4RJvmmFXSjMie4muUHGlKfd1pOkDwT99m+RRxMy174hKQT8aGKE76RVYdpYw35NPf0Mf+xpbo2+uUebU1LwiQA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Gm1nddAd8qPxUx7RuWZO+6pSj1/u/fHRDeGHIT6kVMQ=; b=KCYGo4zmAjYuowXlN/f29pK5VYOI2y74OcXPqAkdvc4+nv1NC1WyjJiy6LuntRVwfrvSq13qiFQ3iwHEqJB3cXGILfOOViU3Yw3SfzaQRASXOOzV1tZyIwq5CxVcm0bA2wg/Fqd75fd1+7yQ6biHgYhFqIVgO2WSE0vyL8R/pamYRaRH3aCyU59kuxdbNRW3RkccDt4HiZ3nX9YadZ6jB1kCgYlp3heaENAGvlDq6aL3vpiT8imv5M4n1XYHnTVZf05YIo78rdZo6aQi4hutfBAgf5LzOqHUS/OMPn6cmHzv/xOkasfQfTTbDO8jBkWRj5bl3Qw84azACpmq7SkS+Q== Received: from BL1PR13CA0205.namprd13.prod.outlook.com (2603:10b6:208:2be::30) by PH7PR12MB6666.namprd12.prod.outlook.com (2603:10b6:510:1a8::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.32; Tue, 30 Apr 2024 04:44:18 +0000 Received: from BL6PEPF0001AB53.namprd02.prod.outlook.com (2603:10b6:208:2be:cafe::7d) by BL1PR13CA0205.outlook.office365.com (2603:10b6:208:2be::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.21 via Frontend Transport; Tue, 30 Apr 2024 04:44:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BL6PEPF0001AB53.mail.protection.outlook.com (10.167.241.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 04:44:17 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:10 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:10 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 29 Apr 2024 21:44:09 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v6 5/6] iommu/arm-smmu-v3: Add in-kernel support for NVIDIA Tegra241 (Grace) CMDQV Date: Mon, 29 Apr 2024 21:43:48 -0700 Message-ID: <63414546b1eafdf8032ac1b95ea514da6d206d63.1714451595.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB53:EE_|PH7PR12MB6666:EE_ X-MS-Office365-Filtering-Correlation-Id: 52dd932c-dd42-4aa0-ce09-08dc68d031e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|1800799015|376005|82310400014; X-Microsoft-Antispam-Message-Info: Y0PkqDTVYvK2oh3uBTELpCHxoUMaqkeGN5LwUTkFwJmuuDFrpLvj7HdT+0qNt2Wlc5dv6u4mrJ+8COOI5aSNYf5K7ni1IulgXfhzdg36wIkPXHjcM2EQs1lqtApcp10w+RqifcIVuHzdABY3bwfonPi72nEWSt/EsZuH8o3V0iRapGRHkaLpZ7EIJYY1Vq29PJy9kgY2lWIuSR5wVD/ofZdjWc19lkZlTjsqe36P/8u/B9cMZEbnc/7zp7zjnOTehWdGrvio6/jTzc50qxUY6D8PshNvUMJdLptsxS2H+U144gBrUOlgQJbG+9oVNNSCAxOwx0dnVlAoLkaBwxSc9kOqb3Ch8kweaplzv8nBi+X4QsfvO57tkUfkYbW7q38buy45dkJUAm5Dve2wTkTM/C/3Fn79REhU6LOYCs6gLYBESiikLhrcKXhWBqNy1WfZDAhfTawAebaXECRtDkiA0I9dRtB+PbUDgfKGAzgcjkMqztIj6uHJ3iGakUJKvPNPFF8MRpx8H4xO6m2GU/Vi6EHTrI/01JztgmUtz8cQyVy1xYenUTg2TC/GO4AhbZ3MQoUZZ+jaBZFsJT5wLPHhKqjaCI41sPcrGVKrOBSOxDEUd6d5B+0S0Of1ZFGuDhY/ZCJia1rZlNv5THqSjo5A8WER2O5CClNPfV76CkRdzqocI0QoBcPrEUZeDNorS3oQ6bPaCHxyARQXWLzbxKvZa7e9uiEwLypgPpR37BIdPiCgdLjkh4RoRYunr3Hfk23X5zdlykJDo+luNalfJk6HuaAyIFctuXjI7SVVcgC/JWsfs2ZUt7Lz9hGHDOUBN6An3oMl4WTEHdz/pRvBSaIGrJmDkQAS4vOv1GSMiu9v45msipFspVO5tssb3Du51FjsZNZ1yKJbDpfDUZ2158zX0i3AdVVblsUHsbUSG54S/8m7o3m7mGY7YLl4nf2qvtNRf45UhQ02Uzhimreg/6J+QnJ4i2qYbA1Qpkpi0MfWosTul/qqRLAnCxJvnshxfoG0zoxkYheniJEWLaEYqd+AladDMXiumNyMvxzVmUDKu0VhyIQd3JpESDASx+ZwW37WsYOJWk2JUKTqniZt17ztDcjNCmaBwyHUk4CxxnDU/VA4eLnjfpn21s9yKzFx3ScPdY33Slu4uXJ87ESYFmTsa6MHIM3ug8VNddjXjo0PKUZNbw0KMMdo8ctBeR558o10FuUXREYF4gqSBPJVOfxS5WXiK/X2pWvcSFsF/XHN/YaNdzCkcMrZZwfPNQ3Qa5JCMg3UD0dOVeMhcaiVa03ghK6E4g2LQPxt2QhjjJ5Zh5FWe3yTyz/diaN6vscsvSdftpgzmY6mJBBfoAj6pZoCI3fD5v2WYaMa5NN4JQ/2TU1WsesKBur8mx12L3tAJCDO X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(1800799015)(376005)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 04:44:17.7235 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52dd932c-dd42-4aa0-ce09-08dc68d031e3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6666 From: Nate Watterson NVIDIA's Tegra241 Soc has a CMDQ-Virtualization (CMDQV) hardware, extending the standard ARM SMMU v3 IP to support multiple VCMDQs with virtualization capabilities. In terms of command queue, they are very like a standard SMMU CMDQ (or ECMDQs), but only support CS_NONE in the CS field of CMD_SYNC. Add a new tegra241-cmdqv driver, and insert its structure pointer into the existing arm_smmu_device, and then add related function calls in the SMMUv3 driver to interact with the CMDQV driver. In the CMDQV driver, add a minimal part for the in-kernel support: reserve VINTF0 for in-kernel use, and assign some of the VCMDQs to the VINTF0, and select one VCMDQ based on the current CPU ID to execute supported commands. This multi-queue design for in-kernel use gives some limited improvements: up to 20% reduction of invalidation time was measured by a multi-threaded DMA unmap benchmark, compared to a single queue. The other part of the CMDQV driver will be user-space support that gives a hypervisor running on the host OS to talk to the driver for virtualization use cases, allowing VMs to use VCMDQs without trappings, i.e. no VM Exits. This is currently WIP based on IOMMUFD, and will be sent for review after SMMU nesting patches are getting merged. This part will provide a guest OS a bigger improvement: 70% to 90% reductions of TLB invalidation time were measured by DMA unmap tests running in a guest OS, compared to nested SMMU CMDQ (with trappings). However, it is very important for this in-kernel support to get merged and installed to VMs running on Grace-powered servers as soon as possible. So, later those servers would only need to upgrade their host kernels for the user-space support. As the initial version, the CMDQV driver only supports ACPI configurations. Signed-off-by: Nate Watterson Co-developed-by: Nicolin Chen Signed-off-by: Nicolin Chen --- MAINTAINERS | 1 + drivers/iommu/Kconfig | 12 + drivers/iommu/arm/arm-smmu-v3/Makefile | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 37 + .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 815 ++++++++++++++++++ 6 files changed, 882 insertions(+), 6 deletions(-) create mode 100644 drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c diff --git a/MAINTAINERS b/MAINTAINERS index f6dc90559341..8a799dbc300b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21742,6 +21742,7 @@ M: Thierry Reding R: Krishna Reddy L: linux-tegra@vger.kernel.org S: Supported +F: drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c F: drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c F: drivers/iommu/tegra* diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 0af39bbbe3a3..82e557de31e3 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -410,6 +410,18 @@ config ARM_SMMU_V3_SVA Say Y here if your system supports SVA extensions such as PCIe PASID and PRI. +config TEGRA241_CMDQV + bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3" + depends on ARM_SMMU_V3 + depends on ACPI + help + Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The + CMDQ-V extension is similar to v3.3 ECMDQ for multi command queues + support, except with virtualization capabilities. + + Say Y here if your system is NVIDIA Tegra241 (Grace) or it has the same + CMDQ-V extension. + config S390_IOMMU def_bool y if S390 && PCI depends on S390 && PCI diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile index 54feb1ecccad..8dff2bc4c7f3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/Makefile +++ b/drivers/iommu/arm/arm-smmu-v3/Makefile @@ -2,4 +2,5 @@ obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o arm_smmu_v3-objs-y += arm-smmu-v3.o arm_smmu_v3-objs-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o +arm_smmu_v3-objs-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o arm_smmu_v3-objs := $(arm_smmu_v3-objs-y) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 5111859347d5..665a5e585f72 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -354,6 +354,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) { + if (smmu->tegra241_cmdqv) + return tegra241_cmdqv_get_cmdq(smmu); + return &smmu->cmdq; } @@ -3105,12 +3108,10 @@ static struct iommu_ops arm_smmu_ops = { }; /* Probing and initialisation functions */ -static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q, - void __iomem *page, - unsigned long prod_off, - unsigned long cons_off, - size_t dwords, const char *name) +int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q, void __iomem *page, + unsigned long prod_off, unsigned long cons_off, + size_t dwords, const char *name) { size_t qsz; @@ -3567,6 +3568,12 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) return ret; } + if (smmu->tegra241_cmdqv) { + ret = tegra241_cmdqv_device_reset(smmu); + if (ret) + return ret; + } + /* Invalidate any cached configuration */ cmd.opcode = CMDQ_OP_CFGI_ALL; arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); @@ -3941,6 +3948,9 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev, if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE) smmu->features |= ARM_SMMU_FEAT_COHERENCY; + smmu->tegra241_cmdqv = + tegra241_cmdqv_acpi_probe(smmu, node->identifier); + return 0; } #else diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 32e7fc5e1794..87e4c227a937 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -626,6 +626,8 @@ struct arm_smmu_strtab_cfg { u32 strtab_base_cfg; }; +struct tegra241_cmdqv; + /* An SMMUv3 instance */ struct arm_smmu_device { struct device *dev; @@ -689,6 +691,12 @@ struct arm_smmu_device { struct rb_root streams; struct mutex streams_mutex; + + /* + * Pointer to NVIDIA Tegra241 CMDQ-Virtualization Extension support, + * similar to v3.3 ECMDQ except with virtualization capabilities. + */ + struct tegra241_cmdqv *tegra241_cmdqv; }; struct arm_smmu_stream { @@ -764,6 +772,10 @@ int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, struct arm_smmu_queue *q); +int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q, void __iomem *page, + unsigned long prod_off, unsigned long cons_off, + size_t dwords, const char *name); #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); @@ -820,4 +832,29 @@ static inline void arm_smmu_sva_remove_dev_pasid(struct iommu_domain *domain, { } #endif /* CONFIG_ARM_SMMU_V3_SVA */ + +#ifdef CONFIG_TEGRA241_CMDQV +struct tegra241_cmdqv * +tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id); +int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu); +struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu); +#else /* CONFIG_TEGRA241_CMDQV */ +static inline struct tegra241_cmdqv * +tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id) +{ + return NULL; +} + +static inline int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu) +{ + return -ENODEV; +} + +static inline struct arm_smmu_cmdq * +tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu) +{ + return NULL; +} +#endif /* CONFIG_TEGRA241_CMDQV */ + #endif /* _ARM_SMMU_V3_H */ diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c new file mode 100644 index 000000000000..4b2af3aaa6b4 --- /dev/null +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -0,0 +1,815 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2021-2024 NVIDIA CORPORATION & AFFILIATES. */ + +#define dev_fmt(fmt) "tegra241_cmdqv: " fmt + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm-smmu-v3.h" + +#define TEGRA241_CMDQV_HID "NVDA200C" + +/* CMDQV register page base and size defines */ +#define TEGRA241_CMDQV_CONFIG_BASE (0) +#define TEGRA241_CMDQV_CONFIG_SIZE (SZ_64K) +#define TEGRA241_VCMDQ_PAGE0_BASE (TEGRA241_CMDQV_CONFIG_BASE + SZ_64K) +#define TEGRA241_VCMDQ_PAGE1_BASE (TEGRA241_VCMDQ_PAGE0_BASE + SZ_64K) +#define TEGRA241_VINTF_PAGE_BASE (TEGRA241_VCMDQ_PAGE1_BASE + SZ_64K) + +/* CMDQV global config regs */ +#define TEGRA241_CMDQV_CONFIG 0x0000 +#define CMDQV_EN BIT(0) + +#define TEGRA241_CMDQV_PARAM 0x0004 +#define CMDQV_NUM_VINTF_LOG2 GENMASK(11, 8) +#define CMDQV_NUM_VCMDQ_LOG2 GENMASK(7, 4) + +#define TEGRA241_CMDQV_STATUS 0x0008 +#define CMDQV_ENABLED BIT(0) + +#define TEGRA241_CMDQV_VINTF_ERR_MAP 0x0014 +#define TEGRA241_CMDQV_VINTF_INT_MASK 0x001C +#define TEGRA241_CMDQV_VCMDQ_ERR_MAP0 0x0024 +#define TEGRA241_CMDQV_VCMDQ_ERR_MAP(i) (0x0024 + 0x4*(i)) + +#define TEGRA241_CMDQV_CMDQ_ALLOC(q) (0x0200 + 0x4*(q)) +#define CMDQV_CMDQ_ALLOC_VINTF GENMASK(20, 15) +#define CMDQV_CMDQ_ALLOC_LVCMDQ GENMASK(7, 1) +#define CMDQV_CMDQ_ALLOCATED BIT(0) + +/* VINTF config regs */ +#define TEGRA241_VINTF(v) (0x1000 + 0x100*(v)) + +#define TEGRA241_VINTF_CONFIG 0x0000 +#define VINTF_HYP_OWN BIT(17) +#define VINTF_VMID GENMASK(16, 1) +#define VINTF_EN BIT(0) + +#define TEGRA241_VINTF_STATUS 0x0004 +#define VINTF_STATUS GENMASK(3, 1) +#define VINTF_ENABLED BIT(0) + +#define TEGRA241_VINTF_CMDQ_ERR_MAP(m) (0x00C0 + 0x4*(m)) + +/* VCMDQ config regs */ +/* -- PAGE0 -- */ +#define TEGRA241_VCMDQ_PAGE0(q) (TEGRA241_VCMDQ_PAGE0_BASE + 0x80*(q)) + +#define TEGRA241_VCMDQ_CONS 0x00000 +#define VCMDQ_CONS_ERR GENMASK(30, 24) + +#define TEGRA241_VCMDQ_PROD 0x00004 + +#define TEGRA241_VCMDQ_CONFIG 0x00008 +#define VCMDQ_EN BIT(0) + +#define TEGRA241_VCMDQ_STATUS 0x0000C +#define VCMDQ_ENABLED BIT(0) + +#define TEGRA241_VCMDQ_GERROR 0x00010 +#define TEGRA241_VCMDQ_GERRORN 0x00014 + +/* -- PAGE1 -- */ +#define TEGRA241_VCMDQ_PAGE1(q) (TEGRA241_VCMDQ_PAGE1_BASE + 0x80*(q)) +#define VCMDQ_ADDR GENMASK(47, 5) +#define VCMDQ_LOG2SIZE GENMASK(4, 0) + +#define TEGRA241_VCMDQ_BASE 0x00000 +#define TEGRA241_VCMDQ_CONS_INDX_BASE 0x00008 + +/* VINTF logical-VCMDQ pages */ +#define TEGRA241_VINTFi_PAGE0(i) (TEGRA241_VINTF_PAGE_BASE + SZ_128K*(i)) +#define TEGRA241_VINTFi_PAGE1(i) (TEGRA241_VINTFi_PAGE0(i) + SZ_64K) +#define TEGRA241_VINTFi_LVCMDQ_PAGE0(i, q) \ + (TEGRA241_VINTFi_PAGE0(i) + 0x80*(q)) +#define TEGRA241_VINTFi_LVCMDQ_PAGE1(i, q) \ + (TEGRA241_VINTFi_PAGE1(i) + 0x80*(q)) + +/* MMIO helpers */ +#define cmdqv_readl(reg) \ + readl(cmdqv->base + TEGRA241_CMDQV_##reg) +#define cmdqv_readl_relaxed(reg) \ + readl_relaxed(cmdqv->base + TEGRA241_CMDQV_##reg) +#define cmdqv_writel(val, reg) \ + writel((val), cmdqv->base + TEGRA241_CMDQV_##reg) +#define cmdqv_writel_relaxed(val, reg) \ + writel_relaxed((val), cmdqv->base + TEGRA241_CMDQV_##reg) + +#define vintf_readl(reg) \ + readl(vintf->base + TEGRA241_VINTF_##reg) +#define vintf_readl_relaxed(reg) \ + readl_relaxed(vintf->base + TEGRA241_VINTF_##reg) +#define vintf_writel(val, reg) \ + writel((val), vintf->base + TEGRA241_VINTF_##reg) +#define vintf_writel_relaxed(val, reg) \ + writel_relaxed((val), vintf->base + TEGRA241_VINTF_##reg) + +#define vcmdq_page0_readl(reg) \ + readl(vcmdq->page0 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page0_readl_relaxed(reg) \ + readl_relaxed(vcmdq->page0 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page0_writel(val, reg) \ + writel((val), vcmdq->page0 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page0_writel_relaxed(val, reg) \ + writel_relaxed((val), vcmdq->page0 + TEGRA241_VCMDQ_##reg) + +#define vcmdq_page1_readl(reg) \ + readl(vcmdq->page1 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page1_readl_relaxed(reg) \ + readl_relaxed(vcmdq->page1 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page1_readq_relaxed(reg) \ + readq_relaxed(vcmdq->page1 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page1_writel(val, reg) \ + writel((val), vcmdq->page1 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page1_writel_relaxed(val, reg) \ + writel_relaxed((val), vcmdq->page1 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page1_writeq(val, reg) \ + writeq((val), vcmdq->page1 + TEGRA241_VCMDQ_##reg) +#define vcmdq_page1_writeq_relaxed(val, reg) \ + writeq_relaxed((val), vcmdq->page1 + TEGRA241_VCMDQ_##reg) + +/* Logging helpers */ +#define cmdqv_warn(fmt, ...) \ + dev_warn(cmdqv->dev, "CMDQV: " fmt, ##__VA_ARGS__) +#define cmdqv_err(fmt, ...) \ + dev_err(cmdqv->dev, "CMDQV: " fmt, ##__VA_ARGS__) +#define cmdqv_info(fmt, ...) \ + dev_info(cmdqv->dev, "CMDQV: " fmt, ##__VA_ARGS__) +#define cmdqv_dbg(fmt, ...) \ + dev_dbg(cmdqv->dev, "CMDQV: " fmt, ##__VA_ARGS__) + +#define vintf_warn(fmt, ...) \ + dev_warn(vintf->cmdqv->dev, "VINTF%u: " fmt, vintf->idx, ##__VA_ARGS__) +#define vintf_err(fmt, ...) \ + dev_err(vintf->cmdqv->dev, "VINTF%u: " fmt, vintf->idx, ##__VA_ARGS__) +#define vintf_info(fmt, ...) \ + dev_info(vintf->cmdqv->dev, "VINTF%u: " fmt, vintf->idx, ##__VA_ARGS__) +#define vintf_dbg(fmt, ...) \ + dev_dbg(vintf->cmdqv->dev, "VINTF%u: " fmt, vintf->idx, ##__VA_ARGS__) + +#define vcmdq_warn(fmt, ...) \ + ({ \ + struct tegra241_vintf *vintf = vcmdq->vintf; \ + if (vintf) \ + vintf_warn("VCMDQ%u/LVCMDQ%u: " fmt, \ + vcmdq->idx, vcmdq->lidx, \ + ##__VA_ARGS__); \ + else \ + dev_warn(vcmdq->cmdqv->dev, "VCMDQ%u: " fmt, \ + vcmdq->idx, ##__VA_ARGS__); \ + }) +#define vcmdq_err(fmt, ...) \ + ({ \ + struct tegra241_vintf *vintf = vcmdq->vintf; \ + if (vintf) \ + vintf_err("VCMDQ%u/LVCMDQ%u: " fmt, \ + vcmdq->idx, vcmdq->lidx, \ + ##__VA_ARGS__); \ + else \ + dev_err(vcmdq->cmdqv->dev, "VCMDQ%u: " fmt, \ + vcmdq->idx, ##__VA_ARGS__); \ + }) +#define vcmdq_info(fmt, ...) \ + ({ \ + struct tegra241_vintf *vintf = vcmdq->vintf; \ + if (vintf) \ + vintf_info("VCMDQ%u/LVCMDQ%u: " fmt, \ + vcmdq->idx, vcmdq->lidx, \ + ##__VA_ARGS__); \ + else \ + dev_info(vcmdq->cmdqv->dev, "VCMDQ%u: " fmt, \ + vcmdq->idx, ##__VA_ARGS__); \ + }) +#define vcmdq_dbg(fmt, ...) \ + ({ \ + struct tegra241_vintf *vintf = vcmdq->vintf; \ + if (vintf) \ + vintf_dbg("VCMDQ%u/LVCMDQ%u: " fmt, \ + vcmdq->idx, vcmdq->lidx, \ + ##__VA_ARGS__); \ + else \ + dev_dbg(vcmdq->cmdqv->dev, "VCMDQ%u: " fmt, \ + vcmdq->idx, ##__VA_ARGS__); \ + }) + +/* Configuring and polling helpers */ +#define tegra241_cmdqv_write_config(_owner, _OWNER, _regval) \ + ({ \ + bool _en = (_regval) & _OWNER##_EN; \ + u32 _status; \ + int _ret; \ + writel((_regval), _owner->base + TEGRA241_##_OWNER##_CONFIG); \ + _ret = readl_poll_timeout( \ + _owner->base + TEGRA241_##_OWNER##_STATUS, _status, \ + _en ? (_regval) & _OWNER##_ENABLED : \ + !((_regval) & _OWNER##_ENABLED), \ + 1, ARM_SMMU_POLL_TIMEOUT_US); \ + if (_ret) \ + _owner##_err("failed to %sable, STATUS = 0x%08X\n", \ + _en ? "en" : "dis", _status); \ + atomic_set(&_owner->status, _status); \ + _ret; \ + }) + +#define cmdqv_write_config(_regval) \ + tegra241_cmdqv_write_config(cmdqv, CMDQV, _regval) +#define vintf_write_config(_regval) \ + tegra241_cmdqv_write_config(vintf, VINTF, _regval) +#define vcmdq_write_config(_regval) \ + tegra241_cmdqv_write_config(vcmdq, VCMDQ, _regval) + +static bool disable_cmdqv; +module_param(disable_cmdqv, bool, 0444); +MODULE_PARM_DESC(disable_cmdqv, + "This allows to disable CMDQV HW and use default SMMU internal CMDQ."); + +static bool bypass_vcmdq; +module_param(bypass_vcmdq, bool, 0444); +MODULE_PARM_DESC(bypass_vcmdq, + "This allows to bypass VCMDQ for debugging use or perf comparison."); + +/** + * struct tegra241_vcmdq - Virtual Command Queue + * @idx: Global index in the CMDQV HW + * @lidx: Local index in the VINTF + * @status: cached status register + * @cmdqv: CMDQV HW pointer + * @vintf: VINTF HW pointer + * @cmdq: Command Queue struct + * @base: MMIO base address + * @page0: MMIO Page0 base address + * @page1: MMIO Page1 base address + */ +struct tegra241_vcmdq { + u16 idx; + u16 lidx; + + atomic_t status; + + struct tegra241_cmdqv *cmdqv; + struct tegra241_vintf *vintf; + struct arm_smmu_cmdq cmdq; + + void __iomem *base; + void __iomem *page0; + void __iomem *page1; +}; + +/** + * struct tegra241_vintf - Virtual Interface + * @idx: Global index in the CMDQV HW + * @status: cached status register + * @cmdqv: CMDQV HW pointer + * @vcmdqs: List of VCMDQ pointers + * @base: MMIO base address + */ +struct tegra241_vintf { + u16 idx; + + atomic_t status; + + struct tegra241_cmdqv *cmdqv; + struct tegra241_vcmdq **vcmdqs; + + void __iomem *base; +}; + +/** + * struct tegra241_cmdqv - CMDQ-V for SMMUv3 + * @smmu: SMMUv3 pointer + * @dev: Device pointer + * @base: MMIO base address + * @irq: IRQ number + * @num_vintfs: Total number of VINTFs + * @num_vcmdqs: Total number of VCMDQs + * @num_vcmdqs_per_vintf: Number of VCMDQs per VINTF + * @status: cached status register + * @vintf_ids: VINTF id allocator + * @vcmdq_ids: VCMDQ id allocator + * @vtinfs: List of VINTFs + */ +struct tegra241_cmdqv { + struct arm_smmu_device *smmu; + + struct device *dev; + void __iomem *base; + int irq; + + /* CMDQV Hardware Params */ + u16 num_vintfs; + u16 num_vcmdqs; + u16 num_vcmdqs_per_vintf; + + atomic_t status; + + struct ida vintf_ids; + struct ida vcmdq_ids; + + struct tegra241_vintf **vintfs; +}; + +static void tegra241_cmdqv_handle_vintf0_error(struct tegra241_cmdqv *cmdqv) +{ + struct tegra241_vintf *vintf = cmdqv->vintfs[0]; + int i; + + /* Cache status to bypass VCMDQs until error is recovered */ + atomic_set(&vintf->status, vintf_readl(STATUS)); + + for (i = 0; i < 4; i++) { + u32 lvcmdq_err_map = vintf_readl_relaxed(CMDQ_ERR_MAP(i)); + + while (lvcmdq_err_map) { + int lidx = ffs(lvcmdq_err_map) - 1; + struct tegra241_vcmdq *vcmdq = vintf->vcmdqs[lidx]; + u32 gerrorn, gerror; + + lvcmdq_err_map &= ~BIT(lidx); + + __arm_smmu_cmdq_skip_err(cmdqv->smmu, &vcmdq->cmdq.q); + + gerrorn = vcmdq_page0_readl_relaxed(GERRORN); + gerror = vcmdq_page0_readl_relaxed(GERROR); + + vcmdq_page0_writel(gerror, GERRORN); + } + } + + /* Now error status should be clean, cache it again */ + atomic_set(&vintf->status, vintf_readl(STATUS)); +} + +static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) +{ + struct tegra241_cmdqv *cmdqv = (struct tegra241_cmdqv *)devid; + u32 vintf_errs[2]; + u32 vcmdq_errs[4]; + + vintf_errs[0] = cmdqv_readl_relaxed(VINTF_ERR_MAP); + vintf_errs[1] = cmdqv_readl_relaxed(VINTF_ERR_MAP + 0x4); + + vcmdq_errs[0] = cmdqv_readl_relaxed(VCMDQ_ERR_MAP(0)); + vcmdq_errs[1] = cmdqv_readl_relaxed(VCMDQ_ERR_MAP(1)); + vcmdq_errs[2] = cmdqv_readl_relaxed(VCMDQ_ERR_MAP(2)); + vcmdq_errs[3] = cmdqv_readl_relaxed(VCMDQ_ERR_MAP(3)); + + cmdqv_warn("unexpected cmdqv error reported\n"); + cmdqv_warn(" vintf_map: 0x%08X%08X\n", vintf_errs[1], vintf_errs[0]); + cmdqv_warn(" vcmdq_map: 0x%08X%08X%08X%08X\n", + vcmdq_errs[3], vcmdq_errs[2], vcmdq_errs[1], vcmdq_errs[0]); + + /* Handle VINTF0 and its VCMDQs */ + if (vintf_errs[0] & 0x1) + tegra241_cmdqv_handle_vintf0_error(cmdqv); + + return IRQ_HANDLED; +} + +struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu) +{ + struct tegra241_cmdqv *cmdqv = smmu->tegra241_cmdqv; + struct tegra241_vintf *vintf = cmdqv->vintfs[0]; + struct tegra241_vcmdq *vcmdq; + u16 lidx; + + if (bypass_vcmdq) + return &smmu->cmdq; + + /* Use SMMU CMDQ if vintfs[0] is uninitialized */ + if (!FIELD_GET(VINTF_ENABLED, atomic_read(&vintf->status))) + return &smmu->cmdq; + + /* Use SMMU CMDQ if vintfs[0] has error status */ + if (FIELD_GET(VINTF_STATUS, atomic_read(&vintf->status))) + return &smmu->cmdq; + + /* + * Select a vcmdq to use. Here we use a temporal solution to + * balance out traffic on cmdq issuing: each cmdq has its own + * lock, if all cpus issue cmdlist using the same cmdq, only + * one CPU at a time can enter the process, while the others + * will be spinning at the same lock. + */ + lidx = smp_processor_id() % cmdqv->num_vcmdqs_per_vintf; + vcmdq = vintf->vcmdqs[lidx]; + if (!FIELD_GET(VCMDQ_ENABLED, atomic_read(&vcmdq->status))) + return &smmu->cmdq; + return &vcmdq->cmdq; +} + +static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) +{ + u32 gerrorn, gerror; + + if (vcmdq_write_config(0)) { + vcmdq_err("GERRORN=0x%X\n", vcmdq_page0_readl_relaxed(GERRORN)); + vcmdq_err("GERROR=0x%X\n", vcmdq_page0_readl_relaxed(GERROR)); + vcmdq_err("CONS=0x%X\n", vcmdq_page0_readl_relaxed(CONS)); + } + vcmdq_page0_writel_relaxed(0, PROD); + vcmdq_page0_writel_relaxed(0, CONS); + vcmdq_page1_writeq_relaxed(0, BASE); + vcmdq_page1_writeq_relaxed(0, CONS_INDX_BASE); + + gerrorn = vcmdq_page0_readl_relaxed(GERRORN); + gerror = vcmdq_page0_readl_relaxed(GERROR); + if (gerror != gerrorn) { + vcmdq_info("Uncleared error detected, resetting\n"); + vcmdq_page0_writel(gerror, GERRORN); + } + + vcmdq_dbg("deinited\n"); +} + +static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) +{ + int ret; + + /* Configure and enable the vcmdq */ + tegra241_vcmdq_hw_deinit(vcmdq); + + vcmdq_page1_writeq_relaxed(vcmdq->cmdq.q.q_base, BASE); + + ret = vcmdq_write_config(VCMDQ_EN); + if (ret) { + vcmdq_err("GERRORN=0x%X\n", vcmdq_page0_readl_relaxed(GERRORN)); + vcmdq_err("GERROR=0x%X\n", vcmdq_page0_readl_relaxed(GERROR)); + vcmdq_err("CONS=0x%X\n", vcmdq_page0_readl_relaxed(CONS)); + return ret; + } + + vcmdq_dbg("inited\n"); + return 0; +} + +/* Adapt struct arm_smmu_cmdq init sequences from arm-smmu-v3.c for VCMDQs */ +static int tegra241_vcmdq_alloc_smmu_cmdq(struct tegra241_vcmdq *vcmdq) +{ + struct arm_smmu_device *smmu = vcmdq->cmdqv->smmu; + struct arm_smmu_cmdq *cmdq = &vcmdq->cmdq; + struct arm_smmu_queue *q = &cmdq->q; + char name[16]; + int ret; + + sprintf(name, "vcmdq%u", vcmdq->idx); + + q->llq.max_n_shift = ilog2(SZ_64K >> CMDQ_ENT_SZ_SHIFT); + + /* Use the common helper to init the VCMDQ, and then... */ + ret = arm_smmu_init_one_queue(smmu, q, vcmdq->page0, + TEGRA241_VCMDQ_PROD, TEGRA241_VCMDQ_CONS, + CMDQ_ENT_DWORDS, name); + if (ret) + return ret; + + /* ...override q_base to write VCMDQ_BASE registers */ + q->q_base = q->base_dma & VCMDQ_ADDR; + q->q_base |= FIELD_PREP(VCMDQ_LOG2SIZE, q->llq.max_n_shift); + + /* All VCMDQs support CS_NONE only for CMD_SYNC */ + q->quirks = CMDQ_QUIRK_SYNC_CS_NONE_ONLY; + + return arm_smmu_cmdq_init(smmu, cmdq); +} + +static void tegra241_vcmdq_free_smmu_cmdq(struct tegra241_vcmdq *vcmdq) +{ + struct tegra241_cmdqv *cmdqv = vcmdq->cmdqv; + struct arm_smmu_queue *q = &vcmdq->cmdq.q; + size_t nents = 1 << q->llq.max_n_shift; + + dmam_free_coherent(cmdqv->smmu->dev, (nents * CMDQ_ENT_DWORDS) << 3, + q->base, q->base_dma); +} + +static int tegra241_vintf_lvcmdq_init(struct tegra241_vintf *vintf, u16 lidx, + struct tegra241_vcmdq *vcmdq) +{ + struct tegra241_cmdqv *cmdqv = vintf->cmdqv; + u16 idx = vintf->idx; + u16 qidx; + + qidx = ida_alloc_max(&cmdqv->vcmdq_ids, + cmdqv->num_vcmdqs - 1, GFP_KERNEL); + if (qidx < 0) + return qidx; + + vcmdq->idx = qidx; + vcmdq->lidx = lidx; + vcmdq->cmdqv = cmdqv; + vcmdq->vintf = vintf; + vcmdq->page0 = cmdqv->base + TEGRA241_VINTFi_LVCMDQ_PAGE0(idx, lidx); + vcmdq->page1 = cmdqv->base + TEGRA241_VINTFi_LVCMDQ_PAGE1(idx, lidx); + vcmdq->base = vcmdq->page0; /* CONFIG register is in page0 */ + return 0; +} + +static void tegra241_vintf_lvcmdq_deinit(struct tegra241_vcmdq *vcmdq) +{ + ida_free(&vcmdq->cmdqv->vcmdq_ids, vcmdq->idx); +} + +static struct tegra241_vcmdq * +tegra241_vintf_lvcmdq_alloc(struct tegra241_vintf *vintf, u16 lidx) +{ + struct tegra241_cmdqv *cmdqv = vintf->cmdqv; + struct tegra241_vcmdq *vcmdq; + int ret; + + vcmdq = devm_kzalloc(cmdqv->dev, sizeof(*vcmdq), GFP_KERNEL); + if (!vcmdq) + return ERR_PTR(-ENOMEM); + + ret = tegra241_vintf_lvcmdq_init(vintf, lidx, vcmdq); + if (ret) + goto free_vcmdq; + + /* Setup struct arm_smmu_cmdq data members */ + ret = tegra241_vcmdq_alloc_smmu_cmdq(vcmdq); + if (ret) + goto deinit_lvcmdq; + + ret = tegra241_vcmdq_hw_init(vcmdq); + if (ret) + goto free_queue; + + vcmdq_dbg("allocated\n"); + return vcmdq; +free_queue: + tegra241_vcmdq_free_smmu_cmdq(vcmdq); +deinit_lvcmdq: + tegra241_vintf_lvcmdq_deinit(vcmdq); +free_vcmdq: + devm_kfree(cmdqv->dev, vcmdq); + return ERR_PTR(ret); +} + +static void tegra241_vintf_lvcmdq_free(struct tegra241_vcmdq *vcmdq) +{ + tegra241_vcmdq_hw_deinit(vcmdq); + tegra241_vcmdq_free_smmu_cmdq(vcmdq); + tegra241_vintf_lvcmdq_deinit(vcmdq); + devm_kfree(vcmdq->cmdqv->dev, vcmdq); +} + +int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu) +{ + struct tegra241_cmdqv *cmdqv = smmu->tegra241_cmdqv; + struct tegra241_vintf *vintf = cmdqv->vintfs[0]; + int qidx, lidx, idx, ret; + u32 regval; + + /* Reset CMDQV */ + regval = cmdqv_readl_relaxed(CONFIG); + ret = cmdqv_write_config(regval & ~CMDQV_EN); + if (ret) + return ret; + ret = cmdqv_write_config(regval | CMDQV_EN); + if (ret) + return ret; + + /* Reset and configure vintf0 */ + ret = vintf_write_config(0); + if (ret) + return ret; + + /* Pre-allocate num_vcmdqs_per_vintf of VCMDQs to each VINTF */ + for (idx = 0, qidx = 0; idx < cmdqv->num_vintfs; idx++) { + for (lidx = 0; lidx < cmdqv->num_vcmdqs_per_vintf; lidx++) { + regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, idx); + regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, lidx); + regval |= CMDQV_CMDQ_ALLOCATED; + cmdqv_writel_relaxed(regval, CMDQ_ALLOC(qidx++)); + } + } + + regval = FIELD_PREP(VINTF_HYP_OWN, 1); + vintf_writel(regval, CONFIG); + + ret = vintf_write_config(regval | VINTF_EN); + if (ret) + return ret; + + /* Build an arm_smmu_cmdq for each vcmdq allocated to vintf */ + vintf->vcmdqs = devm_kcalloc(cmdqv->dev, cmdqv->num_vcmdqs_per_vintf, + sizeof(*vintf->vcmdqs), GFP_KERNEL); + if (!vintf->vcmdqs) + return -ENOMEM; + + /* Allocate logical vcmdqs to vintf */ + for (lidx = 0; lidx < cmdqv->num_vcmdqs_per_vintf; lidx++) { + struct tegra241_vcmdq *vcmdq; + + vcmdq = tegra241_vintf_lvcmdq_alloc(vintf, lidx); + if (IS_ERR(vcmdq)) + goto free_lvcmdq; + vintf->vcmdqs[lidx] = vcmdq; + } + + return 0; +free_lvcmdq: + for (lidx--; lidx >= 0; lidx--) + tegra241_vintf_lvcmdq_free(vintf->vcmdqs[lidx]); + devm_kfree(cmdqv->dev, vintf->vcmdqs); + return ret; +} + +static int tegra241_cmdqv_acpi_is_memory(struct acpi_resource *res, void *data) +{ + struct resource_win win; + + return !acpi_dev_resource_address_space(res, &win); +} + +static int tegra241_cmdqv_acpi_get_irqs(struct acpi_resource *ares, void *data) +{ + struct resource r; + int *irq = data; + + if (*irq <= 0 && acpi_dev_resource_interrupt(ares, 0, &r)) + *irq = r.start; + return 1; /* No need to add resource to the list */ +} + +static struct tegra241_cmdqv * +tegra241_cmdqv_find_resource(struct arm_smmu_device *smmu, int id) +{ + struct tegra241_cmdqv *cmdqv = NULL; + struct device *dev = smmu->dev; + struct list_head resource_list; + struct resource_entry *rentry; + struct acpi_device *adev; + const char *match_uid; + int ret; + + if (acpi_disabled) + return NULL; + + /* Look for a device in the DSDT whose _UID matches the SMMU node ID */ + match_uid = kasprintf(GFP_KERNEL, "%u", id); + adev = acpi_dev_get_first_match_dev(TEGRA241_CMDQV_HID, match_uid, -1); + kfree(match_uid); + + if (!adev) + return NULL; + + dev_info(dev, "found companion CMDQV device, %s\n", + dev_name(&adev->dev)); + + INIT_LIST_HEAD(&resource_list); + ret = acpi_dev_get_resources(adev, &resource_list, + tegra241_cmdqv_acpi_is_memory, NULL); + if (ret < 0) { + dev_err(dev, "failed to get memory resource: %d\n", ret); + goto put_dev; + } + + cmdqv = devm_kzalloc(dev, sizeof(*cmdqv), GFP_KERNEL); + if (!cmdqv) + goto free_list; + + cmdqv->dev = dev; + cmdqv->smmu = smmu; + + rentry = list_first_entry_or_null(&resource_list, + struct resource_entry, node); + if (!rentry) { + cmdqv_err("failed to get memory resource entry\n"); + goto free_cmdqv; + } + + cmdqv->base = devm_ioremap_resource(smmu->dev, rentry->res); + if (IS_ERR(cmdqv->base)) { + cmdqv_err("failed to ioremap: %ld\n", PTR_ERR(cmdqv->base)); + goto free_cmdqv; + } + + acpi_dev_free_resource_list(&resource_list); + + INIT_LIST_HEAD(&resource_list); + + ret = acpi_dev_get_resources(adev, &resource_list, + tegra241_cmdqv_acpi_get_irqs, &cmdqv->irq); + if (ret < 0 || cmdqv->irq <= 0) { + cmdqv_warn("no cmdqv interrupt. errors will not be reported\n"); + } else { + ret = devm_request_irq(smmu->dev, cmdqv->irq, + tegra241_cmdqv_isr, 0, + "tegra241-cmdqv", cmdqv); + if (ret) { + cmdqv_err("failed to request irq (%d): %d\n", + cmdqv->irq, ret); + goto iounmap; + } + } + + goto free_list; + +iounmap: + devm_iounmap(cmdqv->dev, cmdqv->base); +free_cmdqv: + devm_kfree(cmdqv->dev, cmdqv); + cmdqv = NULL; +free_list: + acpi_dev_free_resource_list(&resource_list); +put_dev: + put_device(&adev->dev); + + return cmdqv; +} + +struct dentry *cmdqv_debugfs_dir; + +static int tegra241_cmdqv_probe(struct tegra241_cmdqv *cmdqv) +{ + struct tegra241_vintf *vintf; + u32 regval; + int ret; + + regval = cmdqv_readl(CONFIG); + if (disable_cmdqv) { + cmdqv_info("disable_cmdqv=true. Falling back to SMMU CMDQ\n"); + cmdqv_write_config(regval & ~CMDQV_EN); + return -ENODEV; + } + + ret = cmdqv_write_config(regval | CMDQV_EN); + if (ret) + return ret; + + regval = cmdqv_readl_relaxed(PARAM); + cmdqv->num_vintfs = 1 << FIELD_GET(CMDQV_NUM_VINTF_LOG2, regval); + cmdqv->num_vcmdqs = 1 << FIELD_GET(CMDQV_NUM_VCMDQ_LOG2, regval); + cmdqv->num_vcmdqs_per_vintf = cmdqv->num_vcmdqs / cmdqv->num_vintfs; + + cmdqv->vintfs = devm_kcalloc(cmdqv->dev, cmdqv->num_vintfs, + sizeof(*cmdqv->vintfs), GFP_KERNEL); + if (!cmdqv->vintfs) + return -ENOMEM; + + vintf = devm_kzalloc(cmdqv->dev, sizeof(*vintf), GFP_KERNEL); + if (!vintf) { + ret = -ENOMEM; + goto free_vintfs; + } + + ida_init(&cmdqv->vintf_ids); + ida_init(&cmdqv->vcmdq_ids); + + /* Reserve vintfs[0] for in-kernel use */ + ret = ida_alloc_max(&cmdqv->vintf_ids, 0, GFP_KERNEL); + if (ret != 0) { + cmdqv_err("failed to reserve vintf0: ret %d\n", ret); + if (ret > 0) + ret = -EBUSY; + goto destroy_ids; + } + vintf->idx = 0; + cmdqv->vintfs[0] = vintf; + + vintf->cmdqv = cmdqv; + vintf->base = cmdqv->base + TEGRA241_VINTF(0); + +#ifdef CONFIG_IOMMU_DEBUGFS + if (!cmdqv_debugfs_dir) { + cmdqv_debugfs_dir = debugfs_create_dir("tegra241_cmdqv", iommu_debugfs_dir); + debugfs_create_bool("bypass_vcmdq", 0644, cmdqv_debugfs_dir, &bypass_vcmdq); + } +#endif + + return 0; +destroy_ids: + ida_destroy(&cmdqv->vcmdq_ids); + ida_destroy(&cmdqv->vintf_ids); + devm_kfree(cmdqv->dev, vintf); +free_vintfs: + devm_kfree(cmdqv->dev, cmdqv->vintfs); + return ret; +} + +struct tegra241_cmdqv * +tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id) +{ + struct tegra241_cmdqv *cmdqv; + + cmdqv = tegra241_cmdqv_find_resource(smmu, id); + if (!cmdqv) + return NULL; + + if (tegra241_cmdqv_probe(cmdqv)) { + if (cmdqv->irq > 0) + devm_free_irq(smmu->dev, cmdqv->irq, cmdqv); + devm_iounmap(smmu->dev, cmdqv->base); + devm_kfree(smmu->dev, cmdqv); + return NULL; + } + + return cmdqv; +} From patchwork Tue Apr 30 04:43:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1929267 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=YWTJOq0P; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=linux-tegra+bounces-2014-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VT6zy36Tdz23hd for ; Tue, 30 Apr 2024 14:44:30 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 2EC012843D2 for ; Tue, 30 Apr 2024 04:44:29 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BE78914F70; Tue, 30 Apr 2024 04:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="YWTJOq0P" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2051.outbound.protection.outlook.com [40.107.92.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE144224FD; Tue, 30 Apr 2024 04:44:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452268; cv=fail; b=rcLa0tibV8tdFO5Jf1N/igPFWs52XCEvDFrbDSvhLYNtT4XjHMb4D+MHez+TNzGHeTCG3WAGrL81cQ/xGuHZoXSJtCeBrAL8KF5H1hQWjYeo5lPdBnn9tQOZn4vBAoxbgb3f2yv/yO88KMQJ2waEq1XC3VtTbvXA2b1piosrdEE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714452268; c=relaxed/simple; bh=LWXYAYfBOx52YUQVKAMAspGxxDebB4Xs42TB0zeBL/0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Dg8RvwYxPplvEF7Ly1rwPvkwETkWd/8wtbp5yGtUeAy6+G5AQuil6qijLvdnyYxUF63Wm0K4MznFclziCNOWh6TjhCGZonU1TFQ6G0QhIVDwBsPUEvEmfFZITpIcU14zW1SgOenwnciLnn27SxYWha528zHxvPR4+QH1kafPw+U= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=YWTJOq0P; arc=fail smtp.client-ip=40.107.92.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=W9SFCdV0Q+ySK21Yr2tTPTUw8acVbLt2agKbYps+vWyFzcxLFyEAKUBs3UAf4S4sZpisYa5idk5Qpu6LhzFXtMggKuTjmmkT9UJRIp+TLy8LejH+kqMNfSjlzOV8q67tjuIUNl7Sz9JBHgoCsPSqaXPhS4mOFPkVpFwHvt/n83bwnjzCRWzphUeyhNlLw+73LNpjcTvCPgDM5oxfnnTAjMhY0ClLOG8HszgZWKd94QiCfH61GYVpbXF0n2ShGP09biYiiQ27mK3jYfude4Rmn5eul3hetmTYKhzahecdG2zCwltfNv+qxGvwL8BhLiv0calgjhBoOvFP5WZw1NbpKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hUHqpfFc7P9L/7S5eFMmeZU/JeujbJnunF42Jf7h/fk=; b=ItSyj6R9bYmKBfzjqQ0Kz4T8B8pbu+jfXapxGPgJTFDKxVYBxsuOLCP76K5RFNlx1oScJpAtX+BUtnKLLV4zbfpGqrQ5YHweY9BwiDdzc1KZEhfMg5quI3YooftF0JQXfxvJL8co4DLYqUH7OFp5/hVerJkWePkzCWzoV9qEcpLUe1Xr2akW3oAncLjT1QGxsD9REiwmEWVsdAHJP/FJEN7aWz6mV4FxhCevQzKF/Y38rq+0wfQGLpKkKnsNLuwiOb3qupfGrnWef4RptD/Zo8BGP7UUXPdQtZPGplyyoYv42GbzVpE5iUqQTIwFj0SYeni8NQlG9BKKYQlwtDr7iA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hUHqpfFc7P9L/7S5eFMmeZU/JeujbJnunF42Jf7h/fk=; b=YWTJOq0PZ5Qr3KP9VEhgUEc6gOsuPsLpYSA4DHpyOW4a7cSKwWc/epmq0GuDdLzXvyFbhI+sqH69uw7bTbEgOHMrmZ+N51G5tzPaSGEdaQmVI3fM/nJN3tCOUr1WlpnfrV954Rxac7XSjygGkggdi+NTE+x5tP/alTbitk0ps79PJs5OwQgidIBJUWjeMXA9roiYJ37Wm+TRyvHt4aHg/alCPFe8FMBzbAVfh5xtgbUE7JvrEfd3luicQBCM6RYYSLUuuuxQ8C5xGHytUKp0KCRpRjGUrG4XKjiDWes4cGaowCyxIHGYn6VPKV8w1Difw5M+9j//9qW+hxwcwE75FA== Received: from SN7PR18CA0011.namprd18.prod.outlook.com (2603:10b6:806:f3::19) by DS0PR12MB7584.namprd12.prod.outlook.com (2603:10b6:8:13b::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.35; Tue, 30 Apr 2024 04:44:20 +0000 Received: from SA2PEPF00001507.namprd04.prod.outlook.com (2603:10b6:806:f3:cafe::ae) by SN7PR18CA0011.outlook.office365.com (2603:10b6:806:f3::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.35 via Frontend Transport; Tue, 30 Apr 2024 04:44:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SA2PEPF00001507.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 04:44:20 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:11 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Apr 2024 21:44:10 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 29 Apr 2024 21:44:10 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v6 6/6] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF Date: Mon, 29 Apr 2024 21:43:49 -0700 Message-ID: <4ee1f867e838b90a21de16b12cf2e39ba699eab4.1714451595.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001507:EE_|DS0PR12MB7584:EE_ X-MS-Office365-Filtering-Correlation-Id: c4081c2a-1f10-4e6d-f4b9-08dc68d03389 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|82310400014|1800799015|36860700004; X-Microsoft-Antispam-Message-Info: 3Hg7Q9ikK+b8dsqQhbSi0qEMPCHXZ/jGq91MbSOKjR+M1DVT94oz/YkCb+mCuop42nJRhEcY90MGN6/C0OZpuifUOlWeaiSoui67jpilzGF2bUVeMVpO0weNGZedJJ2blaDQRE143B+mRapq9/pNOf9WVBAR9BrmT+QBRUDXU1RiQfDIvaK4u2ZpUqZslStt+O/r9Tm88Rk+uUd6I3enQ2NRfKO8n1R1H4szzQRyRYjoX0vYNBlK2JLxNtvtmslWGYsEWEpn0FKRWs6IuO+uf8HOKpd5Mlxtwwz4llhhElRq2EoWJLXTXEnhPuyCoXmMhECMm+wD1UBvDUJjapraU7FfSlMLCaRfuPt4xQ1MtLYkPEh29zXSvVxTGuXsCs2WhUM5XC0dGGN9x5Hp5dWPmwX08eUywwrP6vNfMNl42M3+bv3bNxuZ3hotAHm4TKRcmCSo1lLckBHwrJhsqAP7Wtv/lsk2uqEfZZ8+5q5MbpTVe8vYoEufrkp+eDYAeNUC77jD0FvRVRHcZsKzAFVcE1vjbS05d7QVziDBDT0gYBs79FHYoVYHwdfYPaxaixu/xTuWSf8oZU0hw7hwK26l4fMPaET5Olame4R+2G8aJf6tPaRdBOMgOjqlo+DsVOeQlztkkeCJRgCZ7dFNV5CRS0BZpDu0uR3Zs4mhgjAivVeimSTWdOJuTYcbVEgaixuJf8wtsxWNuH1dRQ34u/OqLSYxz30MjI60AwmueJFHbFxLoFx/Si9vP4+Np17HWeyNIP2TjkSmucX891T5E3ayVuVKNpp5U8Qjx4iV05AbJDz1snibbY+yCLByZkElgN/ws0Lqpknv9fXP/At/wjhihBgXZ/2qZ38UV6lWOw94J40xHpq691EYG2uFXxnV45jOlQ5TfRfgAG8GgVt4DwuSkiFPQzBV5a5q0gC1KLockajNsVLQC/sajRLg1e+EDHbYfReDMNg1oDN6y+sC3J3qehOTmj/BA85vAH0OFEvnySQtFC8PNOjGUHKuBZdFcXl6bMdEhYGx4NPba1eJTTnHyuzgudtaXIvyLuABiMfZ9AXH4ZuTaKpv+Nkq/nnjGstP0ZhupAaun9nqn48tYYdauURA40CZ26Pv0fgfpFNKq8l0WH2TlITsQ9sK2HSBuhFR8Tsuk9KQZu0JDw4zsADfR6Pccczwf4UN+/NKcKv5M/fNOcDhSASc2e5KOq0EGbLptji6gwfKKyTPUXUDKIY2HIb799QVe1/n1hhtXiPT7teIXojyON1TBFx/BqM4M/9CaExnJCI8lF2cL4DLvdXXqb/sTV3LDfrVK4pl41txw4oMbRv1T+ZsaeE9BAt3xldy3FRVh5Ori+7CBCK4nkI98hRKnq0Mkhas59P3/ShP0Ipkig7ctsrTsdyEv4mhksN3 X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(82310400014)(1800799015)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 04:44:20.5683 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4081c2a-1f10-4e6d-f4b9-08dc68d03389 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001507.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7584 When VCMDQs are assigned to a VINTF owned by a guest (HYP_OWN bit unset), only TLB and ATC invalidation commands are supported by the VCMDQ HW. So, add a new helper to scan the input cmds to make sure every single command is supported when selecting a queue. Note that the guest VM shouldn't have HYP_OWN bit being set regardless of guest kernel driver writing it or not, i.e. the hypervisor running in the host OS should wire this bit to zero when trapping a write access to this VINTF_CONFIG register from a guest kernel. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 ++- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 44 ++++++++++++++++++- 3 files changed, 50 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 665a5e585f72..0802c3c96a2a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -352,10 +352,11 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) return 0; } -static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) +static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu, + u64 *cmds, int n) { if (smmu->tegra241_cmdqv) - return tegra241_cmdqv_get_cmdq(smmu); + return tegra241_cmdqv_get_cmdq(smmu, cmds, n); return &smmu->cmdq; } @@ -766,7 +767,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, u32 prod; unsigned long flags; bool owner; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); + struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu, cmds, n); struct arm_smmu_ll_queue llq, head; int ret = 0; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 87e4c227a937..e21e29f4770b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -837,7 +837,8 @@ static inline void arm_smmu_sva_remove_dev_pasid(struct iommu_domain *domain, struct tegra241_cmdqv * tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id); int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu); -struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu); +struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, + u64 *cmds, int n); #else /* CONFIG_TEGRA241_CMDQV */ static inline struct tegra241_cmdqv * tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id) @@ -851,7 +852,7 @@ static inline int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu) } static inline struct arm_smmu_cmdq * -tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu) +tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, u64 *cmds, int n) { return NULL; } diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 4b2af3aaa6b4..59ff2b740bec 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -266,6 +266,7 @@ struct tegra241_vcmdq { * struct tegra241_vintf - Virtual Interface * @idx: Global index in the CMDQV HW * @status: cached status register + * @hyp_own: Owned by hypervisor (in-kernel) * @cmdqv: CMDQV HW pointer * @vcmdqs: List of VCMDQ pointers * @base: MMIO base address @@ -274,6 +275,7 @@ struct tegra241_vintf { u16 idx; atomic_t status; + bool hyp_own; struct tegra241_cmdqv *cmdqv; struct tegra241_vcmdq **vcmdqs; @@ -372,7 +374,32 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) return IRQ_HANDLED; } -struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu) +static bool tegra241_vintf_support_cmds(struct tegra241_vintf *vintf, + u64 *cmds, int n) +{ + int i; + + /* VINTF owned by hypervisor can execute any command */ + if (vintf->hyp_own) + return true; + + /* Guest-owned VINTF must Check against the list of supported CMDs */ + for (i = 0; i < n; i++) { + switch (FIELD_GET(CMDQ_0_OP, cmds[i * CMDQ_ENT_DWORDS])) { + case CMDQ_OP_TLBI_NH_ASID: + case CMDQ_OP_TLBI_NH_VA: + case CMDQ_OP_ATC_INV: + continue; + default: + return false; + } + } + + return true; +} + +struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, + u64 *cmds, int n) { struct tegra241_cmdqv *cmdqv = smmu->tegra241_cmdqv; struct tegra241_vintf *vintf = cmdqv->vintfs[0]; @@ -390,6 +417,10 @@ struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu) if (FIELD_GET(VINTF_STATUS, atomic_read(&vintf->status))) return &smmu->cmdq; + /* Unsupported CMDs go for smmu->cmdq pathway */ + if (!tegra241_vintf_support_cmds(vintf, cmds, n)) + return &smmu->cmdq; + /* * Select a vcmdq to use. Here we use a temporal solution to * balance out traffic on cmdq issuing: each cmdq has its own @@ -590,6 +621,11 @@ int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu) } } + /* + * Note that HYP_OWN bit is wired to zero when running in guest kernel + * regardless of enabling it here, as !HYP_OWN cmdqs have a restricted + * set of supported commands, by following the HW design. + */ regval = FIELD_PREP(VINTF_HYP_OWN, 1); vintf_writel(regval, CONFIG); @@ -597,6 +633,12 @@ int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu) if (ret) return ret; + /* + * As being mentioned above, HYP_OWN bit is wired to zero for a guest + * kernel, so read it back from HW to ensure that reflects in hyp_own + */ + vintf->hyp_own = !!(VINTF_HYP_OWN & vintf_readl(CONFIG)); + /* Build an arm_smmu_cmdq for each vcmdq allocated to vintf */ vintf->vcmdqs = devm_kcalloc(cmdqv->dev, cmdqv->num_vcmdqs_per_vintf, sizeof(*vintf->vcmdqs), GFP_KERNEL);