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[106.168.128.197]) by smtp.gmail.com with ESMTPSA id g13-20020a170902d5cd00b001dd88a5dc47sm6902682plh.290.2024.04.14.21.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Apr 2024 21:33:23 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, tudor.ambarus@linaro.org, pratyush@kernel.org, d-gole@ti.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 1/4] mtd: ubi: Do not zero out EC and VID on ECC-ed NOR flashes Date: Mon, 15 Apr 2024 13:33:08 +0900 Message-Id: <87a8c4db9598aa2deb52c41895191b17070ca156.1713154967.git.Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano For NOR flashes EC and VID are zeroed out before an erase is issued to make sure UBI does not mistakenly treat the PEB as used and associate it with an LEB. But on some flashes, like the Infineon Semper NOR flash family, multi-pass page programming is not allowed on the default ECC scheme. This means zeroing out these magic numbers will result in the flash throwing a page programming error. Do not zero out EC and VID for such flashes. A writesize > 1 is an indication of an ECC-ed flash. Signed-off-by: Takahiro Kuwano Acked-by: Tudor Ambarus --- drivers/mtd/ubi/build.c | 4 +--- drivers/mtd/ubi/io.c | 9 ++++++++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index a1941b8eb8..81c1b7bdbc 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -679,10 +679,8 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024) ubi->bad_peb_limit = get_bad_peb_limit(ubi, max_beb_per1024); } - if (ubi->mtd->type == MTD_NORFLASH) { - ubi_assert(ubi->mtd->writesize == 1); + if (ubi->mtd->type == MTD_NORFLASH) ubi->nor_flash = 1; - } ubi->min_io_size = ubi->mtd->writesize; ubi->hdrs_min_io_size = ubi->mtd->writesize >> ubi->mtd->subpage_sft; diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 14be95b74b..45699b4a47 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -563,7 +563,14 @@ int ubi_io_sync_erase(struct ubi_device *ubi, int pnum, int torture) return -EROFS; } - if (ubi->nor_flash) { + /* + * If the flash is ECC-ed then we have to erase the ECC block before we + * can write to it. But the write is in preparation to an erase in the + * first place. This means we cannot zero out EC and VID before the + * erase and we just have to hope the flash starts erasing from the + * start of the page. + */ + if (ubi->nor_flash && ubi->mtd->writesize == 1) { err = nor_erase_prepare(ubi, pnum); if (err) return err; From patchwork Mon Apr 15 04:33:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Kuwano X-Patchwork-Id: 1923555 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=RFse5koq; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VHvSb30XFz1yZ2 for ; Mon, 15 Apr 2024 14:33:51 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5FF568813F; Mon, 15 Apr 2024 06:33:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RFse5koq"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DAC6488152; Mon, 15 Apr 2024 06:33:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A9E4287F4A for ; Mon, 15 Apr 2024 06:33:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tkuw584924@gmail.com Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-5ce9555d42eso1637416a12.2 for ; Sun, 14 Apr 2024 21:33:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1713155608; x=1713760408; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yVABp0aj/N65+2OS5Q6ckzzUCIj/U2v0s8DfimTFZzc=; b=RFse5koqI1FCC3q/Oit3S0ZViogKuWfpLa2plIBwNYd/+UWFktgrc/Tjk4koFSTN/c J7lRrOXAooaqtJ5U7AbMBaH3NuRaiUETm8HzO8CVikwPW/5fqC0OdCSiejWM/YmFjmv0 jMsCsL1x9c8Slq1XC5+YKOj+gxjYTM2cVKmINVkQi2viDVCOOYyYFRLySMjqWBHXZjnz AxvnJS976qj3xocUkldwTXWWa58JBcaiLxj0K9O1c2/PkgIzxFLl9yUu2QZ7CopyV97V 5+VX7PJ4bJQc2xnEs099wkx1WsPWP3lFwGCUpkCMp5TgNE8AwhLvj8HQGWIQhn+Smn1z Ty4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713155608; x=1713760408; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yVABp0aj/N65+2OS5Q6ckzzUCIj/U2v0s8DfimTFZzc=; b=a3lze9YLFe8/ERJOVGh1QEb6DW3WfX06f9R/dNMQMCDd4646CpwejQgXmZjg8w95id kR/JWOeCa56Fgs0CahSyanJov3B/NHrYTfBQV8fPUt/4RZpCmJPZ79iUeY5h9fd5J+Sd 1CCohXkxt53YgGJ9fhTUU9jkaxAnQe2DDNmPuSauWSD2nmm1KvutC2C6KYUSCfAVwRWo s6sIL2LHzApiv2cKlpdoiVcOSKwNLC9laNzNQXN3iEwrZvSoqKCneScwkcOm2NSyb6zH P7yYB8iLeb4Yma3uJH58B72tLCrZg7NWBddxfRQPHQ38hc17MsmJilMekSGUZO33ohTn X/xg== X-Gm-Message-State: AOJu0YwiRyNkJna1gbSLvxQbX5F2N7AZhXPz+7UeEtJ4+H9m+tLIwbFu iWsn0aOAi5TKV0FX++acBvHvSICtktz7pJT7IR+c5qRF+GCwiu7M1PuLiw== X-Google-Smtp-Source: AGHT+IFVcRXeIfRjD2LPFWmk6Nem4pepg4V6DO6m/RrNKx25tj2EUmG2gAKzFcaGBrIQRqgqyOaWWQ== X-Received: by 2002:a17:902:d4c7:b0:1e2:1805:52c5 with SMTP id o7-20020a170902d4c700b001e2180552c5mr11097499plg.16.1713155608087; Sun, 14 Apr 2024 21:33:28 -0700 (PDT) Received: from ISCN5CG2520RPD.infineon.com (KD106168128197.ppp-bb.dion.ne.jp. [106.168.128.197]) by smtp.gmail.com with ESMTPSA id g13-20020a170902d5cd00b001dd88a5dc47sm6902682plh.290.2024.04.14.21.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Apr 2024 21:33:27 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, tudor.ambarus@linaro.org, pratyush@kernel.org, d-gole@ti.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 2/4] mtd: spi-nor: Allow flashes to specify MTD writesize Date: Mon, 15 Apr 2024 13:33:09 +0900 Message-Id: <16e3ddf31a406f6aa4dd8e8267ef5d2a329678ea.1713154967.git.Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano Some flashes like the Infineon SEMPER NOR flash family use ECC. Under this ECC scheme, multi-pass writes to an ECC block is not allowed. In other words, once data is programmed to an ECC block, it can't be programmed again without erasing it first. Upper layers like file systems need to be given this information so they do not cause error conditions on the flash by attempting multi-pass programming. This can be done by setting 'writesize' in 'struct mtd_info'. Set the default to 1 but allow flashes to modify it in fixup hooks. If more flashes show up with this constraint in the future it might be worth it to add it to 'struct flash_info', but for now increasing its size is not worth it. Signed-off-by: Takahiro Kuwano Acked-by: Tudor Ambarus --- drivers/mtd/spi/spi-nor-core.c | 3 ++- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f86003ca8c..1bfef6797f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2789,6 +2789,7 @@ static int spi_nor_init_params(struct spi_nor *nor, memset(params, 0, sizeof(*params)); /* Set SPI NOR sizes. */ + params->writesize = 1; params->size = info->sector_size * info->n_sectors; params->page_size = info->page_size; @@ -4078,7 +4079,7 @@ int spi_nor_scan(struct spi_nor *nor) mtd->dev = nor->dev; mtd->priv = nor; mtd->type = MTD_NORFLASH; - mtd->writesize = 1; + mtd->writesize = params.writesize; mtd->flags = MTD_CAP_NORFLASH; mtd->size = params.size; mtd->_erase = spi_nor_erase; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d1dbf3eadb..0d37a806c4 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -436,6 +436,7 @@ enum spi_nor_pp_command_index { struct spi_nor_flash_parameter { u64 size; + u32 writesize; u32 page_size; u8 rdsr_dummy; u8 rdsr_addr_nbytes; From patchwork Mon Apr 15 04:33:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Kuwano X-Patchwork-Id: 1923556 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=awbsvWIe; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VHvSp0vzZz1yZ2 for ; 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[106.168.128.197]) by smtp.gmail.com with ESMTPSA id g13-20020a170902d5cd00b001dd88a5dc47sm6902682plh.290.2024.04.14.21.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Apr 2024 21:33:31 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, tudor.ambarus@linaro.org, pratyush@kernel.org, d-gole@ti.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 3/4] mtd: spi-nor-core: Rework default_init() to take flash_parameter Date: Mon, 15 Apr 2024 13:33:10 +0900 Message-Id: <9db9fb39e655b514c21952e0a5005572510ad3ec.1713154967.git.Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano default_init() fixup hook should be used to initialize flash parameters when its information is not provided in SFDP. To support that case, it needs to take flash_parameter structure like as other hooks. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi/spi-nor-core.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 1bfef6797f..8f371a5213 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -203,7 +203,8 @@ struct sfdp_bfpt { * table is broken or not available. */ struct spi_nor_fixups { - void (*default_init)(struct spi_nor *nor); + void (*default_init)(struct spi_nor *nor, + struct spi_nor_flash_parameter *params); int (*post_bfpt)(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt, @@ -2775,10 +2776,11 @@ static void spi_nor_post_sfdp_fixups(struct spi_nor *nor, nor->fixups->post_sfdp(nor, params); } -static void spi_nor_default_init_fixups(struct spi_nor *nor) +static void spi_nor_default_init_fixups(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { if (nor->fixups && nor->fixups->default_init) - nor->fixups->default_init(nor); + nor->fixups->default_init(nor, params); } static int spi_nor_init_params(struct spi_nor *nor, @@ -2885,7 +2887,7 @@ static int spi_nor_init_params(struct spi_nor *nor, } } - spi_nor_default_init_fixups(nor); + spi_nor_default_init_fixups(nor, params); /* Override the parameters with data read from SFDP tables. */ nor->addr_width = 0; @@ -3328,7 +3330,8 @@ static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, return spi_nor_default_setup(nor, info, params); } -static void s25fs_s_default_init(struct spi_nor *nor) +static void s25fs_s_default_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->setup = s25fs_s_setup; } @@ -3452,7 +3455,8 @@ static int s25_s28_setup(struct spi_nor *nor, const struct flash_info *info, return spi_nor_default_setup(nor, info, params); } -static void s25_default_init(struct spi_nor *nor) +static void s25_default_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->setup = s25_s28_setup; } @@ -3544,7 +3548,8 @@ static int s25fl256l_setup(struct spi_nor *nor, const struct flash_info *info, return -ENOTSUPP; /* Bank Address Register is not supported */ } -static void s25fl256l_default_init(struct spi_nor *nor) +static void s25fl256l_default_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->setup = s25fl256l_setup; } @@ -3613,7 +3618,8 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor) return 0; } -static void s28hx_t_default_init(struct spi_nor *nor) +static void s28hx_t_default_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable; nor->setup = s25_s28_setup; @@ -3705,7 +3711,8 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) return 0; } -static void mt35xu512aba_default_init(struct spi_nor *nor) +static void mt35xu512aba_default_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->octal_dtr_enable = spi_nor_micron_octal_dtr_enable; } @@ -3795,7 +3802,8 @@ static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor) return 0; } -static void macronix_octal_default_init(struct spi_nor *nor) +static void macronix_octal_default_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; 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[106.168.128.197]) by smtp.gmail.com with ESMTPSA id g13-20020a170902d5cd00b001dd88a5dc47sm6902682plh.290.2024.04.14.21.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Apr 2024 21:33:35 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, tudor.ambarus@linaro.org, pratyush@kernel.org, d-gole@ti.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 4/4] mtd: spi-nor: Set ECC unit size to MTD writesize in Infineon SEMPER flashes Date: Mon, 15 Apr 2024 13:33:11 +0900 Message-Id: <45f73124ace6e2110cbda2eee9ba44b1320feeae.1713154967.git.Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano The Infineon SEMPER NOR flash family uses 2-bit ECC by default with each ECC block being 16 bytes. Under this scheme multi-pass programming to an ECC block is not allowed. Set the writesize to make sure multi-pass programming is not attempted on the flash. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi/spi-nor-core.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 8f371a5213..773afd4040 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3459,6 +3459,13 @@ static void s25_default_init(struct spi_nor *nor, struct spi_nor_flash_parameter *params) { nor->setup = s25_s28_setup; + + /* + * Programming is supported only in 16-byte ECC data unit granularity. + * Byte-programming, bit-walking, or multiple program operations to the + * same ECC data unit without an erase are not allowed. + */ + params->writesize = 16; } static int s25_s28_post_bfpt_fixup(struct spi_nor *nor, @@ -3623,6 +3630,13 @@ static void s28hx_t_default_init(struct spi_nor *nor, { nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable; nor->setup = s25_s28_setup; + + /* + * Programming is supported only in 16-byte ECC data unit granularity. + * Byte-programming, bit-walking, or multiple program operations to the + * same ECC data unit without an erase are not allowed. + */ + params->writesize = 16; } static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor,