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Inherit the register offsets and naming from the Linux driver. More version specific offsets can be inherited from Linux as needed. Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support") Signed-off-by: Caleb Connolly Reviewed-by: Neil Armstrong --- drivers/mmc/msm_sdhci.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 059cb3da77c5..f23d425144ef 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -32,11 +32,8 @@ #define SDCC_MCI_STATUS2 0x6C #define SDCC_MCI_STATUS2_MCI_ACT 0x1 #define SDCC_MCI_HC_MODE 0x78 -/* Non standard (?) SDHCI register */ -#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c - struct msm_sdhc_plat { struct mmc_config cfg; struct mmc mmc; }; @@ -48,8 +45,10 @@ struct msm_sdhc { }; struct msm_sdhc_variant_info { bool mci_removed; + + u32 core_vendor_spec_capabilities0; }; DECLARE_GLOBAL_DATA_PTR; @@ -180,9 +179,9 @@ static int msm_sdc_probe(struct udevice *dev) */ if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { caps = readl(host->ioaddr + SDHCI_CAPABILITIES); caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; - writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); + writel(caps, host->ioaddr + var_info->core_vendor_spec_capabilities0); } ret = mmc_of_parse(dev, &plat->cfg); if (ret) @@ -243,12 +242,16 @@ static int msm_sdc_bind(struct udevice *dev) } static const struct msm_sdhc_variant_info msm_sdhc_mci_var = { .mci_removed = false, + + .core_vendor_spec_capabilities0 = 0x21c, }; static const struct msm_sdhc_variant_info msm_sdhc_v5_var = { .mci_removed = true, + + .core_vendor_spec_capabilities0 = 0x11c, }; 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Update to use dev_read_* functions instead. Signed-off-by: Caleb Connolly Reviewed-by: Neil Armstrong --- drivers/mmc/msm_sdhci.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index f23d425144ef..5689b4765122 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -205,9 +205,9 @@ static int msm_sdc_remove(struct udevice *dev) var_info = (void *)dev_get_driver_data(dev); /* Disable host-controller mode */ - if (!var_info->mci_removed) + if (!var_info->mci_removed && priv->base) writel(0, priv->base + SDCC_MCI_HC_MODE); clk_release_bulk(&priv->clks); @@ -215,23 +215,33 @@ static int msm_sdc_remove(struct udevice *dev) } static int msm_of_to_plat(struct udevice *dev) { - struct udevice *parent = dev->parent; struct msm_sdhc *priv = dev_get_priv(dev); + const struct msm_sdhc_variant_info *var_info; struct sdhci_host *host = &priv->host; - int node = dev_of_offset(dev); + int ret; + + var_info = (void*)dev_get_driver_data(dev); host->name = strdup(dev->name); host->ioaddr = dev_read_addr_ptr(dev); - host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4); - host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0); - priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob, - dev_of_offset(parent), node, "reg", 1, NULL, false); - if (priv->base == (void *)FDT_ADDR_T_NONE || - host->ioaddr == (void *)FDT_ADDR_T_NONE) + ret = dev_read_u32(dev, "bus-width", &host->bus_width); + if (ret) + host->bus_width = 4; + ret = dev_read_u32(dev, "index", &host->index); + if (ret) + host->index = 0; + priv->base = dev_read_addr_index_ptr(dev, 1); + + if (!host->ioaddr) return -EINVAL; + if (!var_info->mci_removed && !priv->base) { + printf("msm_sdhci: MCI base address not found\n"); + return -EINVAL; + } + return 0; } static int msm_sdc_bind(struct udevice *dev) From patchwork Tue Apr 9 18:03:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 1921560 X-Patchwork-Delegate: caleb.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Signed-off-by: Caleb Connolly Reviewed-by: Neil Armstrong --- drivers/mmc/msm_sdhci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 5689b4765122..ea5d6b4cbbee 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -172,8 +172,10 @@ static int msm_sdc_probe(struct udevice *dev) core_major >>= SDCC_VERSION_MAJOR_SHIFT; core_minor = core_version & SDCC_VERSION_MINOR_MASK; + log_debug("SDCC version %d.%d\n", core_major, core_minor); + /* * Support for some capabilities is not advertised by newer * controller versions and must be explicitly enabled. */ From patchwork Tue Apr 9 18:03:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 1921561 X-Patchwork-Delegate: caleb.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Tue, 09 Apr 2024 11:03:11 -0700 (PDT) From: Caleb Connolly Date: Tue, 09 Apr 2024 20:03:03 +0200 Subject: [PATCH 4/7] mmc: msm_sdhci: use a more sensible default clock rate MIME-Version: 1.0 Message-Id: <20240409-b4-qcom-mmc-fixes-v1-4-5039164ecbf7@linaro.org> References: <20240409-b4-qcom-mmc-fixes-v1-0-5039164ecbf7@linaro.org> In-Reply-To: <20240409-b4-qcom-mmc-fixes-v1-0-5039164ecbf7@linaro.org> To: Caleb Connolly , Neil Armstrong , Sumit Garg , Peng Fan , Jaehoon Chung , Tom Rini , Ramon Fried , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=844; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=b7ukOh81BnIglY63qkvOvISFqDbdcJ+fCYYkTyYzjF8=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmFYLYuGOmjIpGlcYiDSdNWQx0ILo5xeNIbcKHw 1Fp/1A/nfuJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZhWC2AAKCRAFgzErGV9k tnXeEACckNQ2EuQfyGNPEMQZDAy7hduXEsxls5ihyKBJl0Ph3ePhBzQhcIVkz8AjOHiLQSq63BN kKz5oM78ScBS75AWk8AQkrXE0/aEpJFpgHJ8sdtRlcrOpSPFxokV38HGCRp0qzCYnOmG/hiYtDU 3XTUYpWeMu1zzcxazHtrx7ni28WuuZ0xjjNviARSb/FtBYhwkXbLj0GbRw1PPUKZ5U2j3lEU7oO ZxuyA9W5cdCn0JkbPOtwbINx1QA0VG0QXPrxdqULcnjRTkgSogKzG4h+DkaE0VnaXs4D7KGR1TA +QO4HDkn9WtZ0d55DFtoaaBhNuW72eo7yvTtTmq1C9SA+qoJtCZELjFw4tAHWrMg7ttZReU95FG S+/sjFNhMHycr0pQ0UIlhLxSa5ABkRHRVkoN1XPfiSlAw0eahcTUaUffWphYm9wOk5V4DNn3/Hp BIMLSbsWy/bV1d1GI1nmWl+jCe/VNq+wPbkxvd4Nxr1cs/egRip8/nFZhaLmcLqhbTgoaJn71hX CIePe71+42vNekOVs5mdLlzYNrcMxKPHTH8JlD2LbK1qjhGRNDePqh9cJMTaelxgBSDcfBKdWVG XjF8qRjAGj0lgLQ/k9wlc7Xc1ahzaesoZ5FqZNiiiilLVB2IYqqT+l27nOG6X5xpLYPxyQ2ohTW W6LD3uqHanswpJg== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean We currently default to the lowest rate but this actually doesn't work on most platforms. Default to the HS400 speed instead which is most common on Qualcomm platforms. Signed-off-by: Caleb Connolly --- drivers/mmc/msm_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index ea5d6b4cbbee..2144772ac325 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -61,9 +61,9 @@ static int msm_sdc_clk_init(struct udevice *dev) const char *clk_name; ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate)); if (ret) - clk_rate = 400000; + clk_rate = 201500000; ret = clk_get_bulk(dev, &prv->clks); if (ret) { log_warning("Couldn't get mmc clocks: %d\n", ret); From patchwork Tue Apr 9 18:03:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 1921562 X-Patchwork-Delegate: caleb.connolly@linaro.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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Tue, 09 Apr 2024 11:03:13 -0700 (PDT) From: Caleb Connolly Date: Tue, 09 Apr 2024 20:03:04 +0200 Subject: [PATCH 5/7] clk/qcom: sdm845: enable SDCC2 core clock MIME-Version: 1.0 Message-Id: <20240409-b4-qcom-mmc-fixes-v1-5-5039164ecbf7@linaro.org> References: <20240409-b4-qcom-mmc-fixes-v1-0-5039164ecbf7@linaro.org> In-Reply-To: <20240409-b4-qcom-mmc-fixes-v1-0-5039164ecbf7@linaro.org> To: Caleb Connolly , Neil Armstrong , Sumit Garg , Peng Fan , Jaehoon Chung , Tom Rini , Ramon Fried , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2686; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=0V4x2W6N+8jfI8icaL5U6rr4j4Ai8OIHFh8munzyrRI=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmFYLYmsLvJXnBEPCCP1V/+B2UdqoqgWEzsjjfO HqiVKMzUPaJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZhWC2AAKCRAFgzErGV9k tvkjD/wJc+OVwum5FM3HGa98GoFrQxxhkQkBLA3KzuSWA38M5XUrJ+0FSUDp5C01QFbyMN1k/Fx fwZhdMtrhLmoUHNlRjiPDOSm86Yzy/xMdddcMwKNVoeaXCQaPFu2L6ijXaIbqYTF+o9ZSsf07uh S4SASmc1+pzC4jCqPbaz4iR6Etg5qUT06MdHxxKBfjEdV+a+SfO8jfCVV/H6QPI6xxuXhLEQUp3 rojj1/XlytK4dvnpjSMdiqQZRWlTYlDAH/ZFZB1ey5aRWS6+FLQM0SdofjdeZm4ShCGVApgF5vN /DrzmdEq0PTD/Qqxepdi54MAC9hU+QQL2gmNKyz3zD11obrp/4QdPh7WCNLXPEg0jiQa2xA3MQK 2kfiklPflK/dy8cecOAjKIRS1SdQ0p022ef0mbYBd/1UKRTakoQpm4P6uB2OM9nH4VFxNN7Olog zSD4CDnt3TOHTsuXrGxZo93HPrTWgwLefUN15lnwqwGw4DipbSxzzxneLRrgLIaDKM98s4yLr82 LqCvln1swjTGSF8KNJJa+rcIOB1aM4wn7clmii/W2frBkY6AZOik22wB7pVb6K8fAvKkrYpO2DO QzCh+qFGIh+SCuSziATofVYnoC4lBBUAv1UQAJ+ISqnIOakpEcm7PBCoOlGV8kCnt0gIpGod6n1 NisWYHhGZcKyABg== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Allow setting the clock rate for the SD card core clock. This is required for SD card support on SDM845 devices. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-qcom.h | 1 + drivers/clk/qcom/clock-sdm845.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index cc170d8e3f9e..f6445c8f566f 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -12,8 +12,9 @@ #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) #define CFG_CLK_SRC_GPLL9 (2 << 8) #define CFG_CLK_SRC_GPLL6 (4 << 8) #define CFG_CLK_SRC_GPLL7 (3 << 8) +#define CFG_CLK_SRC_GPLL4 (5 << 8) #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) #define RCG_CFG_REG 0x4 diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index e9c61eb480de..782df7da8444 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -23,8 +23,9 @@ #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018 #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030 #define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c +#define SDCC2_APPS_CLK_CMD_RCGR 0x1400c static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), @@ -43,8 +44,19 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), { } }; +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(9600000, CFG_CLK_SRC_CXO, 2, 0, 0), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(201500000, CFG_CLK_SRC_GPLL4, 4, 0, 0), + { } +}; + static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); const struct freq_tbl *freq; @@ -54,8 +66,13 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; + case GCC_SDCC2_APPS_CLK: + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Adjust sdm845_get_pin_name() to return the correct names for the special pins. This fixes a non-fatal -ENOSYS error when probing MMC. Signed-off-by: Caleb Connolly Reviewed-by: Neil Armstrong --- drivers/pinctrl/qcom/pinctrl-sdm845.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 459a4329ec80..c1e5cc01fded 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -65,9 +65,20 @@ static const char *sdm845_get_function_name(struct udevice *dev, static const char *sdm845_get_pin_name(struct udevice *dev, unsigned int selector) { - snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + static const char *special_pins_names[] = { + "ufs_reset", + "sdc2_clk", + "sdc2_cmd", + "sdc2_data", + }; + + if (selector >= 150 && selector <= 154) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 150]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; } static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin, From patchwork Tue Apr 9 18:03:06 2024 Content-Type: text/plain; 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Remove the reference to the xo clock which is on the unsupported rpmhcc clock controller. It isn't needed for MMC functionality. Signed-off-by: Caleb Connolly --- arch/arm/dts/sdm845-db845c-u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi b/arch/arm/dts/sdm845-db845c-u-boot.dtsi index 906f9faa5451..9e4533e603c5 100644 --- a/arch/arm/dts/sdm845-db845c-u-boot.dtsi +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi @@ -6,4 +6,11 @@ */ &pcie0_3p3v_dual { regulator-always-on; }; + +&sdhc_2 { + /* Remove the unsupported rpmhcc xo clock reference */ + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; +};