From patchwork Tue Apr 2 10:29:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1918726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=flYTtX7N; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V841B0f6rz23tF for ; Tue, 2 Apr 2024 21:31:24 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rrbP7-0008NY-Vb; Tue, 02 Apr 2024 06:30:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rrbP2-0008KA-He for qemu-devel@nongnu.org; Tue, 02 Apr 2024 06:30:04 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rrbOy-0003e7-CN for qemu-devel@nongnu.org; Tue, 02 Apr 2024 06:30:03 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4161eb1a9fcso41475e9.3 for ; Tue, 02 Apr 2024 03:29:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712053794; x=1712658594; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kF8DIXj6upaIDgYItyrCELeFAUmDbN8yJ98Yufsh5Fc=; b=flYTtX7Nt/Y7dAXF4qiSRbdWkB3CALX3wLR8eRsetcmx24jgE6KUGdk3caOnM0sgTG y6GlWapFRnsCYl0vyxZM4cj4Y4SZ4YNVolUVe+FvoHBcAgdkmRt0XETpGxUJqxk49OmH SD4afO4UmUYqOg5PZ4eNeec7jzMK5LgFhGSZZ/NeX2DZkAjmQdyxosW88lUp/8snYSLp XaDiARJqzVTrfGEpMudaTt9OVuKXHbWGmdnE4FrXFOa1MtMFDHS7SqvcKIEvDxXGKFUj rwgi3cfThG51m+LXaHCpR58Jg2qTFVJTKuXE2C4fxpS522Ys9mi/oREbJibnW8L5Nkwb fHhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712053794; x=1712658594; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kF8DIXj6upaIDgYItyrCELeFAUmDbN8yJ98Yufsh5Fc=; b=i734Q81r3fVOD57OtojeWJZRormjylJZ5R9tU3N4hUWKlyQCstVSNHJT7h3+Gb8bPi t3ZRQEXVfnkd8Okp+HHYZWsevtmFcQyoIkjwD/tKoLC0EIYzTdr5fAIigyWx0eaj3zdG V/QDIIB3985015i6G0Zjj+Vy1w1dG/QUKlx294fJ2dsCG/UkzmnyUVKeYfC9R4WAbI3G FHAG0UbTfsTTa5zXhe/jOdkbR5AvosljgbVOKoL9ACH/FDi6ruShP90kauL6jRSuwf+O +zYpqmBXVeaeMSAutX41/rHn5VbbxS5OiAEw9dAaHLBSeuRBnZZgHkgTqqWtuJTG/CAA mo1A== X-Gm-Message-State: AOJu0Yym3NdqWVeh2YYMS83M+D+sjaNinaRyd2xErkTrJ/x+Vy+Kyfhx PHBAibcyWKsIFefkUf5m6GKwAipQx0XxdXNIIMS8uhuMkr5JyA68EhT2JnO++o9JUn8GqUYSWtM O X-Google-Smtp-Source: AGHT+IHYHlLqPCEATaXSkGcg8fXvF2071t3vB8QI5daX1CfAmXI295nfjMS/AE6mLULjKIpTmI9lsw== X-Received: by 2002:a05:600c:1c12:b0:415:66ac:614d with SMTP id j18-20020a05600c1c1200b0041566ac614dmr3631159wms.13.1712053793933; Tue, 02 Apr 2024 03:29:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o15-20020a05600c4fcf00b0041488895a37sm20586175wmq.33.2024.04.02.03.29.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 03:29:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/5] target/arm: take HSTR traps of cp15 accesses to EL2, not EL1 Date: Tue, 2 Apr 2024 11:29:47 +0100 Message-Id: <20240402102951.3099078-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402102951.3099078-1-peter.maydell@linaro.org> References: <20240402102951.3099078-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The HSTR_EL2 register allows the hypervisor to trap AArch32 EL1 and EL0 accesses to cp15 registers. We incorrectly implemented this so they trap to EL1 when we detect the need for a HSTR trap at code generation time. (The check in access_check_cp_reg() which we do at runtime to catch traps from EL0 is correctly routing them to EL2.) Use the correct target EL when generating the code to take the trap. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2226 Fixes: 049edada5e93df ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240325133116.2075362-1-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c8a24706750..69585e6003d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4585,7 +4585,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, tcg_gen_andi_i32(t, t, 1u << maskbit); tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); - gen_exception_insn(s, 0, EXCP_UDEF, syndrome); + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); /* * gen_exception_insn() will set is_jmp to DISAS_NORETURN, * but since we're conditionally branching over it, we want From patchwork Tue Apr 2 10:29:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1918727 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=eUKuQhJy; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V841B0ZTfz23t4 for ; Tue, 2 Apr 2024 21:31:24 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rrbP7-0008NE-7l; Tue, 02 Apr 2024 06:30:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rrbP3-0008Kw-Lt for qemu-devel@nongnu.org; Tue, 02 Apr 2024 06:30:05 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rrbOy-0003eR-Im for qemu-devel@nongnu.org; Tue, 02 Apr 2024 06:30:05 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-41569865b2fso11091535e9.3 for ; Tue, 02 Apr 2024 03:29:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712053794; x=1712658594; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QuZfSUVScjt9n5vrw27PPdIk4irfQ7o3hh1IbZPVDZ4=; b=eUKuQhJyhlzuHQHnOz9ENoU8qCx2fi/cgIZ/9uTvRs6G4lauSJgT8Hp+uJV7+0BnXU FAzhfHaZ5YHIERwHns/7TuqcOpMrvb3lo6oRXgALPt4bymGxmBoa0h8SDrhDS5f9x7lU Nm/fFse7uO5iaah6uzEZAEg79lNUpTTy2/fVnzrpoSwjOlIn/O++LeykA5TjGL29Fv2h 6GyGNgubo4EA5WRb23Ktuapv/y6FFmO5QvYll8jDIHTxwRmNaE0JtW6qiuI/c1SjQChr 4X4vpNcZUqVZOgEus19GGbmb8xg2WHVhuSW5tlaZSOIdhQWz+SDWANeOq5o8z0lghtJf F3Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712053794; x=1712658594; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QuZfSUVScjt9n5vrw27PPdIk4irfQ7o3hh1IbZPVDZ4=; b=ie/5bHyKdovHHtPa6BIwwqk/N1TqS5L0aGTfjTcYoUQS8gLYgo7wDOAFSmg67U6YXz tC3VdrNZTnCk5R1Lqs425DPAtYtpd8z4dPJ7AFe+D5hN00QeSkXLFTNlClfF8RvNKVol jneE10kkF6mwH+bM6bNxuEgobcH9cPkxh4RQy4rktLY7GCoV6+45f6+/uslBrPs2mBAX z7BoFkY5N5mw9JUglwzjQWLFAt8XHJO9o7aZz+6s1g5ZUBN0gJ1p7Kq1Rh4jTMCXPRgu AabaWeK9dwVf46Lvdj1+IanyyUTVqxHPfvMIW/8qX3X44qVYHmn8qsSoB4/zKiPh7OCo 99HA== X-Gm-Message-State: AOJu0Yw9M7PspV6Jm1cWCOkwxiQhgZyeen6PXcKGCZ5xNW5w7REnC1pE NfwDwFDY3Me05UHb302OBcrEhSpCmEyE9S06UQA7diUEKs47914Pwx3wx5LiEZa7yKFXvt1M9pu t X-Google-Smtp-Source: AGHT+IF1WVMJqBX8wKcJrjD1tw6r0+MIztUnpOj0+YUY0EPDy6FWPV0smRK0y/FwEhhuv1V0fpIkQQ== X-Received: by 2002:a05:600c:a4b:b0:414:887f:617a with SMTP id c11-20020a05600c0a4b00b00414887f617amr9308484wmq.38.1712053794410; Tue, 02 Apr 2024 03:29:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o15-20020a05600c4fcf00b0041488895a37sm20586175wmq.33.2024.04.02.03.29.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 03:29:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/5] docs: sbsa: update specs, add dt note Date: Tue, 2 Apr 2024 11:29:48 +0100 Message-Id: <20240402102951.3099078-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402102951.3099078-1-peter.maydell@linaro.org> References: <20240402102951.3099078-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Marcin Juszkiewicz Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA specifications. Then BBR defines firmware interface. Added note about DeviceTree data passed from QEMU to firmware. It is very minimal and provides only data we use in firmware. Added NUMA information to list of things reported by DeviceTree. Signed-off-by: Marcin Juszkiewicz Message-id: 20240328163851.1386176-1-marcin.juszkiewicz@linaro.org Reviewed-by: Leif Lindholm Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index bca61608ff8..2bf22a1d0b0 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -1,12 +1,16 @@ Arm Server Base System Architecture Reference board (``sbsa-ref``) ================================================================== -While the ``virt`` board is a generic board platform that doesn't match -any real hardware the ``sbsa-ref`` board intends to look like real -hardware. The `Server Base System Architecture -`_ defines a -minimum base line of hardware support and importantly how the firmware -reports that to any operating system. +The ``sbsa-ref`` board intends to look like real hardware (while the ``virt`` +board is a generic board platform that doesn't match any real hardware). + +The hardware part is defined by two specifications: + + - `Base System Architecture `__ (BSA) + - `Server Base System Architecture `__ (SBSA) + +The `Arm Base Boot Requirements `__ (BBR) +specification defines how the firmware reports that to any operating system. It is intended to be a machine for developing firmware and testing standards compliance with operating systems. @@ -35,16 +39,29 @@ includes both internal hardware and parts affected by the qemu command line (i.e. CPUs and memory). As a result it must have a firmware specifically built to expect a certain hardware layout (as you would in a real machine). +Note +'''' + +QEMU provides the guest EL3 firmware with minimal information about hardware +platform using minimalistic devicetree. This is not a Linux devicetree. It is +not even a firmware devicetree. + +It is information passed from QEMU to describe the information a hardware +platform would have other mechanisms to discover at runtime, that are affected +by the QEMU command line. + +Ultimately this devicetree may be replaced by IPC calls to an emulated SCP. + DeviceTree information '''''''''''''''''''''' -The devicetree provided by the board model to the firmware is not intended -to be a complete compliant DT. It currently reports: +The devicetree reports: - CPUs - memory - platform version - GIC addresses + - NUMA node id for CPUs and memory Platform version '''''''''''''''' @@ -70,4 +87,4 @@ Platform version changes: GIC ITS information is present in devicetree. 0.3 - The USB controller is an XHCI device, not EHCI + The USB controller is an XHCI device, not EHCI. From patchwork Tue Apr 2 10:29:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1918724 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=hq6iGl0t; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V84196rR5z1yZB for ; Tue, 2 Apr 2024 21:31:24 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rrbP5-0008ME-PZ; Tue, 02 Apr 2024 06:30:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rrbP2-0008KM-Uk for qemu-devel@nongnu.org; Tue, 02 Apr 2024 06:30:05 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rrbOy-0003er-F0 for qemu-devel@nongnu.org; Tue, 02 Apr 2024 06:30:04 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-415446af364so24613455e9.0 for ; Tue, 02 Apr 2024 03:29:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712053795; x=1712658595; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=91BZ+bUW9V0rFrI3CQ5Xh/5sgpFgV/x/ACLid6y7DpM=; b=hq6iGl0txrf58Hpo8/N+5s43bnhFAJ2xWkqiccWNH0Mzscb8olzmyuNiR8N4HMD4MF vRYPbfFiAdV+s6DBgi8RlEuFFPK/taiSaxwEnsyk4M9PiS634ZQX+tNt5pt3UCUsUPZM 0psG1XzSPpIpkjZLLp0o0yPmpseeEzCBHOllIGn7Kxed+zzJ6ubFMnyolHU79dO1ZO1T C/Hi9bHiQaj2szIt/Msqy3nfQ1MM19g7pWzLPVARr6JWPiqKHnSzwuJYrv8wLfTdUwfr rF0FPOiDh9cXtUEPGeGbUS6+viM7+DNdx04cqXKrFEaEWwCRr+orHRUnc2wVXppxKasE LRhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712053795; x=1712658595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=91BZ+bUW9V0rFrI3CQ5Xh/5sgpFgV/x/ACLid6y7DpM=; b=GM9GGpw/EvHmAVmG4V9NFq0Up2orBafzIAAoaVruyHkFKL62un3q/SXDITATZ7HqLV RwINwPeckVWcG2YjxZbC3dlXoUUcHmgvOWVkDL0zfkMk2ZZL0sBIOyk4IhMKhYxqcTWf +zxCYmrLliqPRw4aButzZxooDf1eVZ0uNDtWwiA4glg0TYD9LSw1a/PSMepxsCqhHZY2 Dndze+tuE2LsfuoK1VdrUxRv6BYL3S4jSdpEVV/1qznuyApjQHFr4mKD1DC45mpxSLei CvHpFXJEQF0fjdlDQrv5ZAnprCNR+Hq/guL6yRiz4cPWFjeWT9zu+KwE8NEWORkuJcRw hqyg== X-Gm-Message-State: AOJu0Yw2gBahO+1fmECC+P3/feCnkFeNy5nTXEF6MKd5l6FyLwh49dLA s0jba8Gh6+lrU0D0kwowbrXy5lYH1g9zA2qZXDOEWoFUZSC7/xlYprFZH89ghFb3bKQivGH9IAD Y X-Google-Smtp-Source: AGHT+IH3BfhMk5bty9oxx5kF1EE12S369V8AM6q2CsEupBNPmN4oL15EG6JqCTgCcwhBITBRwKAYqA== X-Received: by 2002:a05:600c:4f05:b0:416:1ad7:f1b9 with SMTP id l5-20020a05600c4f0500b004161ad7f1b9mr1383866wmq.17.1712053794876; Tue, 02 Apr 2024 03:29:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o15-20020a05600c4fcf00b0041488895a37sm20586175wmq.33.2024.04.02.03.29.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 03:29:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/5] hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled Date: Tue, 2 Apr 2024 11:29:49 +0100 Message-Id: <20240402102951.3099078-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402102951.3099078-1-peter.maydell@linaro.org> References: <20240402102951.3099078-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org If the group of the highest priority pending interrupt is disabled via ICC_IGRPEN*, the ICC_HPPIR* registers should return INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture specification pseudocode functions ICC_HPPIR1_EL1[] and HighestPriorityPendingInterrupt().) Make HPPIR reads honour the group disable, the way we already do when determining whether to preempt in icc_hppi_can_preempt(). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240328153333.2522667-1-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index e1a60d8c15b..67d8fd07b7f 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1067,7 +1067,7 @@ static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env) */ bool irq_is_secure; - if (cs->hppi.prio == 0xff) { + if (icc_no_enabled_hppi(cs)) { return INTID_SPURIOUS; } @@ -1104,7 +1104,7 @@ static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) */ bool irq_is_secure; - if (cs->hppi.prio == 0xff) { + if (icc_no_enabled_hppi(cs)) { return INTID_SPURIOUS; } From patchwork Tue Apr 2 10:29:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1918728 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=bIfQCa/6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V841M5Scqz1yYB for ; Tue, 2 Apr 2024 21:31:35 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rrbP8-0008Np-LD; Tue, 02 Apr 2024 06:30:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rrbP4-0008L8-8M for qemu-devel@nongnu.org; Tue, 02 Apr 2024 06:30:06 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rrbOy-0003fL-KD for qemu-devel@nongnu.org; Tue, 02 Apr 2024 06:30:05 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-415584360c0so18040185e9.1 for ; Tue, 02 Apr 2024 03:29:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712053795; x=1712658595; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=z0wrG3SHPfvp8oYYuwfJ6UUShS6yr2AWBhFDuw/bUJo=; b=bIfQCa/60y/rKUTJWf/QY3qsnEvE1Nq7twIGYyuRhO3SX3WPbZmcH8uOsil8nqoafW O7SywO37lNrbnU+Xeupk2hO/sC9ezWl/q+1/J5g6v4oVZTpTUeSG09PlDaoJWDOJpcQ4 TDQNxTvTyXzu4+FZ6TV4FYk4PPLZNOPrtS9BBUtpUDKHqhrp6q9nJ6PUE3qCKnsyLxDX ACBAQwIlWsGj0WTcSxIG8kP7syzQTVal8ZBryfRp4RBmdq7qqYWxWxH6siHYCUnFhxxr HKalVemX+dX+h67A7DGK8fXh2OyTg6vuHSqLiH8lA4wSqFiZAkJ1PqmZI8ToDrBW4g3b /htw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712053795; x=1712658595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z0wrG3SHPfvp8oYYuwfJ6UUShS6yr2AWBhFDuw/bUJo=; b=nEqbtIE11e53B85T+U+47cdcq57Xg4vwtLp/rC19HuhirerkRkjOp/KvyXsalQzukd J7S6dOp1QmiNixjNsp4m7a0ubF5MD67y+8n6zEOyJneRPhUlF4ce6JXkEmMHrWxjyJcx tKHJkvSEH0y6YmvA6ay7x0QsknMJhqGMbeBk5u8aK8IJysjqvwydzwLAgv+BilHtN7C1 GXNwi4f8ZFJPnwolJT7U/cRqu30y7Jc75SjWZGr+Zw8Bte9KiPJ5Y97H2dpt8GuaBk1a GqQ64rkwStZOwZbT4N7Qe+LzyrA7FpmyeOozCowgzeLrDLZjGTEVc06+whYiho0RBYuM 1lpg== X-Gm-Message-State: AOJu0YxlkaKq4WavPGT3pAB+wXWpgVm8zAjTWNLCMqhyeRf2OFmIdmy2 DI9EuA91Ki5hsZDqx+gwcsAtQsY5467NxWAAkld4KGcP+6VhvedvRij+tZIbWjQZrtGqDJVzzdo n X-Google-Smtp-Source: AGHT+IGG3jziZXHaZrHtdEtPV3sg+dgHdBj7zdVKW7WJtJrhIUTHv9zkspxgoILz3jeuJo0ebHRFVA== X-Received: by 2002:a05:600c:3587:b0:414:ae9b:7d71 with SMTP id p7-20020a05600c358700b00414ae9b7d71mr9190322wmq.27.1712053795400; Tue, 02 Apr 2024 03:29:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o15-20020a05600c4fcf00b0041488895a37sm20586175wmq.33.2024.04.02.03.29.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 03:29:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/5] tests/qtest: Fix STM32L4x5 GPIO test on 32-bit Date: Tue, 2 Apr 2024 11:29:50 +0100 Message-Id: <20240402102951.3099078-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402102951.3099078-1-peter.maydell@linaro.org> References: <20240402102951.3099078-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Cédric Le Goater The test mangles the GPIO address and the pin number in the qtest_add_data_func data parameter. Doing so, it assumes that the host pointer size is always 64-bit, which breaks on 32-bit : ../tests/qtest/stm32l4x5_gpio-test.c: In function ‘test_gpio_output_mode’: ../tests/qtest/stm32l4x5_gpio-test.c:272:25: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] 272 | unsigned int pin = ((uint64_t)data) & 0xF; | ^ ../tests/qtest/stm32l4x5_gpio-test.c:273:22: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] 273 | uint32_t gpio = ((uint64_t)data) >> 32; | ^ To fix, improve the mangling of the GPIO address and pin number fields by using GPIO_SIZE so that the resulting value fits in a 32-bit pointer. While at it, include some helpers to hide the details. Cc: Arnaud Minier Cc: Inès Varhol Signed-off-by: Cédric Le Goater Message-id: 20240329092747.298259-1-clg@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/stm32l4x5_gpio-test.c | 59 ++++++++++++++++++------------- 1 file changed, 35 insertions(+), 24 deletions(-) diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c index cc56be2031f..0f6bda54d3c 100644 --- a/tests/qtest/stm32l4x5_gpio-test.c +++ b/tests/qtest/stm32l4x5_gpio-test.c @@ -76,6 +76,17 @@ const uint32_t idr_reset[NUM_GPIOS] = { 0x00000000 }; +#define PIN_MASK 0xF +#define GPIO_ADDR_MASK (~(GPIO_SIZE - 1)) + +static inline void *test_data(uint32_t gpio_addr, uint8_t pin) +{ + return (void *)(uintptr_t)((gpio_addr & GPIO_ADDR_MASK) | (pin & PIN_MASK)); +} + +#define test_gpio_addr(data) ((uintptr_t)(data) & GPIO_ADDR_MASK) +#define test_pin(data) ((uintptr_t)(data) & PIN_MASK) + static uint32_t gpio_readl(unsigned int gpio, unsigned int offset) { return readl(gpio + offset); @@ -269,8 +280,8 @@ static void test_gpio_output_mode(const void *data) * Additionally, it checks that values written to ODR * when not in output mode are stored and not discarded. */ - unsigned int pin = ((uint64_t)data) & 0xF; - uint32_t gpio = ((uint64_t)data) >> 32; + unsigned int pin = test_pin(data); + uint32_t gpio = test_gpio_addr(data); unsigned int gpio_id = get_gpio_id(gpio); qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); @@ -304,8 +315,8 @@ static void test_gpio_input_mode(const void *data) * corresponding GPIO line high/low : it should set the * right bit in IDR and send an irq to syscfg. */ - unsigned int pin = ((uint64_t)data) & 0xF; - uint32_t gpio = ((uint64_t)data) >> 32; + unsigned int pin = test_pin(data); + uint32_t gpio = test_gpio_addr(data); unsigned int gpio_id = get_gpio_id(gpio); qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); @@ -333,8 +344,8 @@ static void test_pull_up_pull_down(const void *data) * Test that a floating pin with pull-up sets the pin * high and vice-versa. */ - unsigned int pin = ((uint64_t)data) & 0xF; - uint32_t gpio = ((uint64_t)data) >> 32; + unsigned int pin = test_pin(data); + uint32_t gpio = test_gpio_addr(data); unsigned int gpio_id = get_gpio_id(gpio); qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); @@ -363,8 +374,8 @@ static void test_push_pull(const void *data) * disconnects the pin, that the pin can't be set or reset * externally afterwards. */ - unsigned int pin = ((uint64_t)data) & 0xF; - uint32_t gpio = ((uint64_t)data) >> 32; + unsigned int pin = test_pin(data); + uint32_t gpio = test_gpio_addr(data); uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); @@ -410,8 +421,8 @@ static void test_open_drain(const void *data) * However a pin set low externally shouldn't be disconnected, * and it can be set low externally when in open-drain mode. */ - unsigned int pin = ((uint64_t)data) & 0xF; - uint32_t gpio = ((uint64_t)data) >> 32; + unsigned int pin = test_pin(data); + uint32_t gpio = test_gpio_addr(data); uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); @@ -466,8 +477,8 @@ static void test_bsrr_brr(const void *data) * has the desired effect on ODR. * In BSRR, BSx has priority over BRx. */ - unsigned int pin = ((uint64_t)data) & 0xF; - uint32_t gpio = ((uint64_t)data) >> 32; + unsigned int pin = test_pin(data); + uint32_t gpio = test_gpio_addr(data); gpio_writel(gpio, BSRR, (1 << pin)); g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin)); @@ -507,40 +518,40 @@ int main(int argc, char **argv) * is problematic since the pin was already high. */ qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode", - (void *)((uint64_t)GPIO_C << 32 | 5), + test_data(GPIO_C, 5), test_gpio_output_mode); qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode", - (void *)((uint64_t)GPIO_H << 32 | 3), + test_data(GPIO_H, 3), test_gpio_output_mode); qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1", - (void *)((uint64_t)GPIO_D << 32 | 6), + test_data(GPIO_D, 6), test_gpio_input_mode); qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2", - (void *)((uint64_t)GPIO_C << 32 | 10), + test_data(GPIO_C, 10), test_gpio_input_mode); qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1", - (void *)((uint64_t)GPIO_B << 32 | 5), + test_data(GPIO_B, 5), test_pull_up_pull_down); qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2", - (void *)((uint64_t)GPIO_F << 32 | 1), + test_data(GPIO_F, 1), test_pull_up_pull_down); qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1", - (void *)((uint64_t)GPIO_G << 32 | 6), + test_data(GPIO_G, 6), test_push_pull); qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2", - (void *)((uint64_t)GPIO_H << 32 | 3), + test_data(GPIO_H, 3), test_push_pull); qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1", - (void *)((uint64_t)GPIO_C << 32 | 4), + test_data(GPIO_C, 4), test_open_drain); qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2", - (void *)((uint64_t)GPIO_E << 32 | 11), + test_data(GPIO_E, 11), test_open_drain); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o15-20020a05600c4fcf00b0041488895a37sm20586175wmq.33.2024.04.02.03.29.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 03:29:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/5] raspi4b: Reduce RAM to 1Gb on 32-bit hosts Date: Tue, 2 Apr 2024 11:29:51 +0100 Message-Id: <20240402102951.3099078-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402102951.3099078-1-peter.maydell@linaro.org> References: <20240402102951.3099078-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Cédric Le Goater Change the board revision number and RAM size to 1Gb on 32-bit hosts. On these systems, RAM has a 2047 MB limit and this breaks the tests. Fixes: 7785e8ea2204 ("hw/arm: Introduce Raspberry PI 4 machine") Signed-off-by: Cédric Le Goater Message-id: 20240329150155.357043-1-clg@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/raspi4b.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c index cb1b1f2f147..85877880fc7 100644 --- a/hw/arm/raspi4b.c +++ b/hw/arm/raspi4b.c @@ -112,7 +112,11 @@ static void raspi4b_machine_class_init(ObjectClass *oc, void *data) MachineClass *mc = MACHINE_CLASS(oc); RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc); +#if HOST_LONG_BITS == 32 + rmc->board_rev = 0xa03111; /* Revision 1.1, 1 Gb RAM */ +#else rmc->board_rev = 0xb03115; /* Revision 1.5, 2 Gb RAM */ +#endif raspi_machine_class_common_init(mc, rmc->board_rev); mc->init = raspi4b_machine_init; }