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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id g75sm2822087wmc.47.2018.04.20.06.51.42 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 06:51:42 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de, agraf@suse.de Date: Fri, 20 Apr 2018 15:51:40 +0200 Message-Id: <0662f83f37aa9e9fe96cb1b940ea9bac947512a9.1524232297.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.17.0 Subject: [U-Boot] [PATCH 1/2] arm: Add minimal support for Cortex-R5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This minimal support will be used by Xilinx ZynqMP R5 cpu. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 6 ++++++ arch/arm/cpu/armv7r/Makefile | 4 ++++ arch/arm/cpu/armv7r/config.mk | 3 +++ arch/arm/cpu/armv7r/cpu.c | 24 ++++++++++++++++++++++++ arch/arm/cpu/armv7r/start.S | 17 +++++++++++++++++ 5 files changed, 54 insertions(+) create mode 100644 arch/arm/cpu/armv7r/Makefile create mode 100644 arch/arm/cpu/armv7r/config.mk create mode 100644 arch/arm/cpu/armv7r/cpu.c create mode 100644 arch/arm/cpu/armv7r/start.S diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5fbce03667d..b10804f55224 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -192,6 +192,10 @@ config CPU_V7M select THUMB2_KERNEL select SYS_CACHE_SHIFT_5 +config CPU_V7R + bool + select SYS_CACHE_SHIFT_6 + config CPU_PXA bool select SYS_CACHE_SHIFT_5 @@ -209,6 +213,7 @@ config SYS_CPU default "arm1176" if CPU_ARM1176 default "armv7" if CPU_V7 default "armv7m" if CPU_V7M + default "armv7r" if CPU_V7R default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 default "armv8" if ARM64 @@ -223,6 +228,7 @@ config SYS_ARM_ARCH default 6 if CPU_ARM1176 default 7 if CPU_V7 default 7 if CPU_V7M + default 7 if CPU_V7R default 5 if CPU_PXA default 4 if CPU_SA1100 default 8 if ARM64 diff --git a/arch/arm/cpu/armv7r/Makefile b/arch/arm/cpu/armv7r/Makefile new file mode 100644 index 000000000000..3c66976dfa62 --- /dev/null +++ b/arch/arm/cpu/armv7r/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +extra-y := start.o +obj-y += cpu.o diff --git a/arch/arm/cpu/armv7r/config.mk b/arch/arm/cpu/armv7r/config.mk new file mode 100644 index 000000000000..224d191ff846 --- /dev/null +++ b/arch/arm/cpu/armv7r/config.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +PLATFORM_CPPFLAGS += -mcpu=cortex-r5 -DARMR5 diff --git a/arch/arm/cpu/armv7r/cpu.c b/arch/arm/cpu/armv7r/cpu.c new file mode 100644 index 000000000000..e384a530c5e0 --- /dev/null +++ b/arch/arm/cpu/armv7r/cpu.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) + */ + +#include + +/* + * This is called right before passing control to + * the Linux kernel point. + */ +int cleanup_before_linux(void) +{ + return 0; +} + +/* + * Perform the low-level reset. + */ +void reset_cpu(ulong addr) +{ + while (1) + ; +} diff --git a/arch/arm/cpu/armv7r/start.S b/arch/arm/cpu/armv7r/start.S new file mode 100644 index 000000000000..d6e8eecf54b7 --- /dev/null +++ b/arch/arm/cpu/armv7r/start.S @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 + * Kamil Lulko, + * + */ + +#include + +.globl reset +.type reset, %function +reset: + W(b) _main + +.globl c_runtime_cpu_setup +c_runtime_cpu_setup: + mov pc, lr From patchwork Fri Apr 20 13:51:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 901938 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="d7B8rx/j"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40SHNp4nPdz9s72 for ; Fri, 20 Apr 2018 23:52:42 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 255ECC21D4A; Fri, 20 Apr 2018 13:52:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 46EB0C21E02; Fri, 20 Apr 2018 13:51:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1EB23C21D72; Fri, 20 Apr 2018 13:51:45 +0000 (UTC) Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com [209.85.128.193]) by lists.denx.de (Postfix) with ESMTPS id 6416EC21C27 for ; Fri, 20 Apr 2018 13:51:45 +0000 (UTC) Received: by mail-wr0-f193.google.com with SMTP id o15-v6so23210340wro.11 for ; Fri, 20 Apr 2018 06:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=rgtYTFWBUrRfqjH/98DYgrtSkykupqpoESDfYMOcLEQ=; b=d7B8rx/jN86cmufIY+kLFY53nJQvVQQoRjmJ0yMwO7321IZQz+i3fqirGZkdCRbnAC O/ooRuexxsd1icbVIJ8Mku1C64A9JH1vJorbgkSKoTh94DJcqzAg+x6KzPnaHZPNhNf2 aQ4BDFYFNIUMq0VRJx4Vm3Vns9gw7K7VGXS8qjEdof6/MbezAZw6A5QF/vlbv1t9Ydh1 RA6D4o85RdP84levKFDU3krHRwLsWgAcccs5GtYd+sVZovVtpvWyWu1xt5kCh6fjhyPP CdVw181eIyeLqfqISQYVMk/G63T3gnAofEY32yyZ9mg94ZDOH0ZJzl/Z7nFv40Nlou7x HBLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=rgtYTFWBUrRfqjH/98DYgrtSkykupqpoESDfYMOcLEQ=; b=lP31CdjE04sqQ1cfzVDyDSc6xo7d7K+iWD5XrUiz0TQ/lakSHKNiBvPLoFfsvlzbKb oWqv71gTEB+AbLyY+4tdwBpbBmpIgYYtixVwN7qRhDWMB06moILwva1U+oLnbTbYlg/y NUB2LdA86AfwiVOejFWBABWwO1yMtq93+O7ySd5skqOnI7p8LBaJ1g4JtMZG7EyqzE88 bUpgMgGFf/5yvClbkC6+NXp7UsY0BYHjqX3+YobKlVksbuCZgXpLWodBVbDJPhAAksqa tPrJXKQRj9rA9u1b1d+Z590ftgSx0xINLkQ40+r/uAZwZP/m7rdn6U8grHw44Q7eZyNp 8r6g== X-Gm-Message-State: ALQs6tD07ub0miga8gT8PP7YrYs/cIRAPlndixqsQj1Ib7qPcy+J2vaJ U/0eu5hz1kZMQUwBGM+KZtoaUEKp X-Google-Smtp-Source: AIpwx49SxoayQo1HjwKDbIcRff9tFye2uUmJywgFEXYLo4kB/uvu12xO0broX8cV3DsOlijqWPEktw== X-Received: by 10.28.5.198 with SMTP id 189mr1886949wmf.155.1524232304529; Fri, 20 Apr 2018 06:51:44 -0700 (PDT) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id z72sm1445768wmc.28.2018.04.20.06.51.43 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 06:51:43 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de, agraf@suse.de Date: Fri, 20 Apr 2018 15:51:41 +0200 Message-Id: <9ab906892a3df5a6b224a9235b2f4f1a1f84410c.1524232297.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <0662f83f37aa9e9fe96cb1b940ea9bac947512a9.1524232297.git.michal.simek@xilinx.com> References: <0662f83f37aa9e9fe96cb1b940ea9bac947512a9.1524232297.git.michal.simek@xilinx.com> In-Reply-To: <0662f83f37aa9e9fe96cb1b940ea9bac947512a9.1524232297.git.michal.simek@xilinx.com> References: <0662f83f37aa9e9fe96cb1b940ea9bac947512a9.1524232297.git.michal.simek@xilinx.com> Cc: Maxime Ripard , Heinrich Schuchardt , Icenowy Zheng , Marek Vasut , Andy Shevchenko , Eugeniy Paltsev , Stefan Roese Subject: [U-Boot] [PATCH 2/2] arm: zynqmp: Add ZynqMP minimal R5 support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek --- Changes compare to RFC - Use 500MHz instead of 600MHz - Remove fpu compilation flags - Split arm-r5 code and platform --- MAINTAINERS | 6 +++ arch/arm/Kconfig | 10 ++++ arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/zynqmp-r5.dts | 73 ++++++++++++++++++++++++++++++ arch/arm/mach-zynqmp-r5/Kconfig | 27 +++++++++++ arch/arm/mach-zynqmp-r5/Makefile | 3 ++ arch/arm/mach-zynqmp-r5/cpu.c | 15 ++++++ board/xilinx/zynqmp_r5/MAINTAINERS | 7 +++ board/xilinx/zynqmp_r5/Makefile | 6 +++ board/xilinx/zynqmp_r5/board.c | 25 ++++++++++ configs/xilinx_zynqmp_r5_defconfig | 16 +++++++ drivers/serial/Kconfig | 2 +- include/configs/xilinx_zynqmp_r5.h | 49 ++++++++++++++++++++ 14 files changed, 241 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynqmp-r5.dts create mode 100644 arch/arm/mach-zynqmp-r5/Kconfig create mode 100644 arch/arm/mach-zynqmp-r5/Makefile create mode 100644 arch/arm/mach-zynqmp-r5/cpu.c create mode 100644 board/xilinx/zynqmp_r5/MAINTAINERS create mode 100644 board/xilinx/zynqmp_r5/Makefile create mode 100644 board/xilinx/zynqmp_r5/board.c create mode 100644 configs/xilinx_zynqmp_r5_defconfig create mode 100644 include/configs/xilinx_zynqmp_r5.h diff --git a/MAINTAINERS b/MAINTAINERS index 147551f66fd3..e60d76dbad8a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,6 +295,12 @@ F: include/zynqmppl.h F: tools/zynqimage.c N: zynqmp +ARM ZYNQMP R5 +M: Michal Simek +S: Maintained +T: git git://git.denx.de/u-boot-microblaze.git +F: arch/arm/mach-zynqmp-r5/ + BUILDMAN M: Simon Glass S: Maintained diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b10804f55224..e09ab487b7d0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -771,6 +771,14 @@ config ARCH_ZYNQ imply CMD_SPL imply ARCH_EARLY_INIT_R +config ARCH_ZYNQMP_R5 + bool "Xilinx ZynqMP R5 based platform" + select CPU_V7R + select OF_CONTROL + select DM + select DM_SERIAL + select CLK + config ARCH_ZYNQMP bool "Xilinx ZynqMP based platform" select ARM64 @@ -1289,6 +1297,8 @@ source "arch/arm/cpu/armv7/vf610/Kconfig" source "arch/arm/mach-zynq/Kconfig" +source "arch/arm/mach-zynqmp-r5/Kconfig" + source "arch/arm/cpu/armv7/Kconfig" source "arch/arm/cpu/armv8/zynqmp/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4fa8b38397d9..b4b45f3c6328 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -76,6 +76,7 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq +machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1fb36b3ecdb3..d44a4310081e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -165,6 +165,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zc1751-xm017-dc3.dtb \ zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb +dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ + zynqmp-r5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ am335x-draco.dtb \ am335x-evm.dtb \ diff --git a/arch/arm/dts/zynqmp-r5.dts b/arch/arm/dts/zynqmp-r5.dts new file mode 100644 index 000000000000..ba4d66a167c2 --- /dev/null +++ b/arch/arm/dts/zynqmp-r5.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP R5 + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynqmp-r5"; + model = "Xilinx ZynqMP R5"; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + cpu@0 { + compatible = "arm,cortex-r5"; + device_type = "cpu"; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; + }; + + amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ttc0: timer@ff110000 { + compatible = "cdns,ttc"; + status = "okay"; + reg = <0xff110000 0x1000>; + timer-width = <32>; + clocks = <&clk100>; + }; + + uart1: serial@ff010000 { + u-boot,dm-pre-reloc; + compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + reg = <0xff010000 0x1000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk100 &clk100>; + }; + }; +}; diff --git a/arch/arm/mach-zynqmp-r5/Kconfig b/arch/arm/mach-zynqmp-r5/Kconfig new file mode 100644 index 000000000000..5e0175413395 --- /dev/null +++ b/arch/arm/mach-zynqmp-r5/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_ZYNQMP_R5 + +config SYS_BOARD + string "Board name" + default "zynqmp_r5" + +config SYS_VENDOR + string "Vendor name" + default "xilinx" + +config SYS_SOC + default "zynqmp-r5" + +config SYS_CONFIG_NAME + string "Board configuration name" + default "xilinx_zynqmp_r5" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. + +config SYS_MALLOC_F_LEN + default 0x600 + +endif diff --git a/arch/arm/mach-zynqmp-r5/Makefile b/arch/arm/mach-zynqmp-r5/Makefile new file mode 100644 index 000000000000..0d39e97dd371 --- /dev/null +++ b/arch/arm/mach-zynqmp-r5/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += cpu.o diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c new file mode 100644 index 000000000000..0d86e2d1c886 --- /dev/null +++ b/arch/arm/mach-zynqmp-r5/cpu.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int arch_cpu_init(void) +{ + gd->cpu_clk = CONFIG_CPU_FREQ_HZ; + + return 0; +} diff --git a/board/xilinx/zynqmp_r5/MAINTAINERS b/board/xilinx/zynqmp_r5/MAINTAINERS new file mode 100644 index 000000000000..ac267649781a --- /dev/null +++ b/board/xilinx/zynqmp_r5/MAINTAINERS @@ -0,0 +1,7 @@ +XILINX_ZYNQMP_R5 BOARDS +M: Michal Simek +S: Maintained +F: arch/arm/dts/zynqmp-r5* +F: board/xilinx/zynqmp_r5/ +F: include/configs/xilinx_zynqmp_r5_* +F: configs/xilinx_zynqmp_r5_* diff --git a/board/xilinx/zynqmp_r5/Makefile b/board/xilinx/zynqmp_r5/Makefile new file mode 100644 index 000000000000..c5a3e3d328bd --- /dev/null +++ b/board/xilinx/zynqmp_r5/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# (C) Copyright 2018 Xilinx, Inc. (Michal Simek) +# + +obj-y := board.o diff --git a/board/xilinx/zynqmp_r5/board.c b/board/xilinx/zynqmp_r5/board.c new file mode 100644 index 000000000000..70fb20235498 --- /dev/null +++ b/board/xilinx/zynqmp_r5/board.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) + */ + +#include +#include + +int board_init(void) +{ + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; + + return 0; +} diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig new file mode 100644 index 000000000000..46715242e703 --- /dev/null +++ b/configs/xilinx_zynqmp_r5_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP_R5=y +CONFIG_SYS_TEXT_BASE=0x10000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5" +CONFIG_DEBUG_UART=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SYS_PROMPT="ZynqMP r5> " +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_EMBED=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff010000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_ZYNQ_SERIAL=y +CONFIG_TIMER=y +CONFIG_CADENCE_TTC_TIMER=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 3d5b2bf15f08..3292edbaf240 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -617,7 +617,7 @@ config STM32_SERIAL config ZYNQ_SERIAL bool "Cadence (Xilinx Zynq) UART support" - depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_ZYNQMP_R5) help This driver supports the Cadence UART. It is found e.g. in Xilinx Zynq/ZynqMP. diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h new file mode 100644 index 000000000000..80bbf4d2159d --- /dev/null +++ b/include/configs/xilinx_zynqmp_r5.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) + */ + +#ifndef __CONFIG_ZYNQMP_R5_H +#define __CONFIG_ZYNQMP_R5_H + +#define CONFIG_EXTRA_ENV_SETTINGS + +/* CPU clock */ +#define CONFIG_CPU_FREQ_HZ 500000000 + +/* Serial drivers */ +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +# define CONFIG_ENV_SIZE (128 << 10) + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Boot configuration */ +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ + +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MALLOC_LEN 0x1400000 + +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF + +#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */