From patchwork Thu Apr 19 18:27:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 901432 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=cogentembedded.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=cogentembedded-com.20150623.gappssmtp.com header.i=@cogentembedded-com.20150623.gappssmtp.com header.b="a9L/fK8e"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40RnXY3SD4z9s1w for ; Fri, 20 Apr 2018 04:27:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753132AbeDSS1j (ORCPT ); Thu, 19 Apr 2018 14:27:39 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:46595 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752903AbeDSS1i (ORCPT ); Thu, 19 Apr 2018 14:27:38 -0400 Received: by mail-lf0-f65.google.com with SMTP id j68-v6so1520797lfg.13 for ; Thu, 19 Apr 2018 11:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:cc:references:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=OCS/islHjA4u00vqbayRNA2fOSBqV3CEa3Cb9WY+7RQ=; b=a9L/fK8eEIzw9NqDZRtS7Qcg6HqVnYZQh3T/Zd/Yxz5ZICzu+AewWJNX1O/pCuMwS3 GGALBX55Z4zEDaiMmQUp5YEh4jO8l0BTnKfWVK/9/cG/4v6I+HjVhpzAlgDLrfF7udIu BANH/kbGX9TEqpu/O3od/xA6qSJif5WoVY45M03FGOszHR7cbPoEAp0jrR/j5Jt15H+g wLsHc2HB+HYcyIxDHMIjF8CdEFwMVaMbZqwxQwenYQGOjgm2BTNPGYBSYzg3Pk1YJOGb Upz2SxvBrSWevxxnMSTaR5TubOLe/YbJBBJYCFKTXhWZ4DxPgDFkdS4EzjaM9HxRaJmq tluA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=OCS/islHjA4u00vqbayRNA2fOSBqV3CEa3Cb9WY+7RQ=; b=iPqZ7GIEvdNgOiXjQaWZ9MGZ4P8kqeibVh1Rvb/GWt3NWT11XrkU1wj6p6u6NbUDei uw9YAuGcGb/W1EgoOq0MrUOSB4cjah5OjWz9Hi5O1yLYebUC4oVpCLHlD9K5eZ4sv9XH 8/do8suDhdnjiij6haoUxPdA/MHqeAURJ99peF8TACna8z5K0ch6or42i4+Edk7zW71v VUYl7hjyKnH0whAq6FEHOdu6tnB5BfreyDDg7kb1DUjZ8NXeoWDIS5ndmmWm6KG3iKAl BUejblIcwRDgKwnsm6230Yev+1E91zXkhA3nslQw6b5e/wTrBvIdNsB6Q8b69HeFSTxt e9Ig== X-Gm-Message-State: ALQs6tBdZ3OG/k9SSfvPTOrztbXvgcFGvWlvvnbWeo0j7fdaDWEG46NT xn467TZ6AlIPDrA5/KM3KSy3zcWMZ3Q= X-Google-Smtp-Source: AIpwx48zA8E7uR9rQ92Mx3F5vRXTmIlaxGuexh16++coOB8Rf9Aw3mZbUkEvF4ZSG4v5dkxb2xAGkg== X-Received: by 10.46.60.2 with SMTP id j2mr4886105lja.79.1524162456999; Thu, 19 Apr 2018 11:27:36 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.81.209]) by smtp.gmail.com with ESMTPSA id t66-v6sm872498lff.40.2018.04.19.11.27.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Apr 2018 11:27:35 -0700 (PDT) From: Sergei Shtylyov Subject: [PATCH v2] pinctrl: sh-pfc: r8a77980: add pin I/O voltage control support To: Linus Walleij , Geert Uytterhoeven , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Laurent Pinchart References: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Organization: Cogent Embedded Message-ID: Date: Thu, 19 Apr 2018 21:27:34 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Content-Language: en-MW Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the pin I/O voltage level control support to the R8A77980 PFC driver. Loosely based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo. Changes in version 2: - added IOCTRL33 to *enum* ioctrl_regs and its address to pinmux_ioctrl_regs[]; - fixed the subject; - added Geert's tag. drivers/pinctrl/sh-pfc/pfc-r8a77980.c | 52 ++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c =================================================================== --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77980.c +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c @@ -19,10 +19,10 @@ #include "sh_pfc.h" #define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_22(0, fn, sfx), \ + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_28(1, fn, sfx), \ - PORT_GP_30(2, fn, sfx), \ - PORT_GP_17(3, fn, sfx), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_25(4, fn, sfx), \ PORT_GP_15(5, fn, sfx) @@ -2779,8 +2779,53 @@ static const struct pinmux_cfg_reg pinmu { }, }; +enum ioctrl_regs { + IOCTRL30, + IOCTRL31, + IOCTRL32, + IOCTRL33, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [IOCTRL30] = { 0xe6060380, }, + [IOCTRL31] = { 0xe6060384, }, + [IOCTRL32] = { 0xe6060388, }, + [IOCTRL33] = { 0xe606038c, }, + { /* sentinel */ }, +}; + +static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + int bit = pin & 0x1f; + + *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) + return bit; + else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) + return bit + 22; + + *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg; + if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) + return bit - 10; + if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) || + (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) + return bit + 7; + + *pocctrl = pinmux_ioctrl_regs[IOCTRL32].reg; + if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) + return pin - 25; + + return -EINVAL; +} + +static const struct sh_pfc_soc_operations pinmux_ops = { + .pin_to_pocctrl = r8a77980_pin_to_pocctrl, +}; + const struct sh_pfc_soc_info r8a77980_pinmux_info = { .name = "r8a77980_pfc", + .ops = &pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -2793,6 +2838,7 @@ const struct sh_pfc_soc_info r8a77980_pi .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data),