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Fri, 08 Mar 2024 09:17:59 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 4289Hu9m000777; Fri, 8 Mar 2024 09:17:56 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3wkw6m3h0j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 08 Mar 2024 09:17:56 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4289HuTK000745; Fri, 8 Mar 2024 09:17:56 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4289HtAj000738 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 08 Mar 2024 09:17:55 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id E620A4117D; Fri, 8 Mar 2024 14:47:54 +0530 (+0530) From: Md Sadre Alam To: andersson@kernel.org, konrad.dybcio@linaro.org, broonie@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, manivannan.sadhasivam@linaro.org, neil.armstrong@linaro.org, daniel@makrotopia.org, arnd@arndb.de, chris.packham@alliedtelesis.co.nz, christophe.kerello@foss.st.com, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com Subject: [PATCH v4 1/5] spi: dt-bindings: Introduce qcom,spi-qpic-snand Date: Fri, 8 Mar 2024 14:47:48 +0530 Message-Id: <20240308091752.16136-2-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308091752.16136-1-quic_mdalam@quicinc.com> References: <20240308091752.16136-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: j1DXEjuAZuj7K4ATwQYePAm_2A1kvuN0 X-Proofpoint-ORIG-GUID: j1DXEjuAZuj7K4ATwQYePAm_2A1kvuN0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-08_06,2024-03-06_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1011 malwarescore=0 lowpriorityscore=0 phishscore=0 spamscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403080073 Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. It can work both in serial and parallel mode and supports typical SPI-NAND page cache operations. Signed-off-by: Md Sadre Alam Reviewed-by: Krzysztof Kozlowski --- Change in [v4] * Fix spelling mistake in HW description * Added commit message * Removed '|' from description * Removed minItems in clock * Added blank line * Removed co-developed by Change in [v3] * Updated commit message, removed "dt-bindings" from commit message * Updated compatible name as file name * Added hardware description * Documented clock-name * Moved dma-names property to top * Droped unused label "qpic_nand" * Fixed indentation in example dt node Change in [v2] * Added initial support for dt-bindings Change in [v1] * This patch was not included in [v1] .../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml new file mode 100644 index 000000000000..f0d9f7643849 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QPIC NAND controller + +maintainers: + - Md sadre Alam + +description: + The QCOM QPIC-SPI-NAND flash controller is an extended version of + the QCOM QPIC NAND flash controller. It can work both in serial + and parallel mode. It supports typical SPI-NAND page cache + operations in single, dual or quad IO mode with pipelined ECC + encoding/decoding using the QPIC ECC HW engine. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,spi-qpic-snand + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: core + - const: aon + - const: iom + + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + - description: cmd DMA channel + + dma-names: + items: + - const: tx + - const: rx + - const: cmd + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + spi@79b0000 { + compatible = "qcom,spi-qpic-snand"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; + };