From patchwork Thu Apr 19 13:21:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie DELAUNAY X-Patchwork-Id: 901104 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-rtc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40Rfnz3w05z9s1X for ; Thu, 19 Apr 2018 23:23:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752812AbeDSNWm (ORCPT ); Thu, 19 Apr 2018 09:22:42 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:36367 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751293AbeDSNWk (ORCPT ); Thu, 19 Apr 2018 09:22:40 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3JDEa5f018285; Thu, 19 Apr 2018 15:22:01 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hds2asxre-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 19 Apr 2018 15:22:01 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5FF5B34; Thu, 19 Apr 2018 13:22:00 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 42B5E4EAC; Thu, 19 Apr 2018 13:22:00 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 19 Apr 2018 15:22:00 +0200 Received: from localhost (10.201.20.5) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 19 Apr 2018 15:21:59 +0200 From: Amelie Delaunay To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue CC: , , , , Amelie Delaunay Subject: [PATCH 1/4] rtc: stm32: fix copyright and adopt SPDX identifier Date: Thu, 19 Apr 2018 15:21:40 +0200 Message-ID: <1524144103-21432-2-git-send-email-amelie.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524144103-21432-1-git-send-email-amelie.delaunay@st.com> References: <1524144103-21432-1-git-send-email-amelie.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.5] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-19_05:, , signatures=0 Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org Fix copyright by removing "SA" and "for STMicroelectronics", not required. Adopt SPDX identifier. Signed-off-by: Amelie Delaunay --- drivers/rtc/rtc-stm32.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index f25dabe..79d9e86 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) STMicroelectronics SA 2017 - * Author: Amelie Delaunay for STMicroelectronics. - * License terms: GNU General Public License (GPL), version 2 + * Copyright (C) STMicroelectronics 2017 + * Author: Amelie Delaunay */ #include From patchwork Thu Apr 19 13:21:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie DELAUNAY X-Patchwork-Id: 901105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-rtc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40Rfp829tzz9s1X for ; Thu, 19 Apr 2018 23:24:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752958AbeDSNWh (ORCPT ); Thu, 19 Apr 2018 09:22:37 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:13723 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752947AbeDSNWg (ORCPT ); Thu, 19 Apr 2018 09:22:36 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3JDE5wx018820; Thu, 19 Apr 2018 15:22:01 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hds2hhxu1-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 19 Apr 2018 15:22:01 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5939D38; Thu, 19 Apr 2018 13:22:01 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2B6634EAC; Thu, 19 Apr 2018 13:22:01 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 19 Apr 2018 15:22:01 +0200 Received: from localhost (10.201.20.5) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 19 Apr 2018 15:22:00 +0200 From: Amelie Delaunay To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue CC: , , , , Amelie Delaunay Subject: [PATCH 2/4] rtc: stm32: fix alarm interrupt flags by removing IRQF_TRIGGER_RISING Date: Thu, 19 Apr 2018 15:21:41 +0200 Message-ID: <1524144103-21432-3-git-send-email-amelie.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524144103-21432-1-git-send-email-amelie.delaunay@st.com> References: <1524144103-21432-1-git-send-email-amelie.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.5] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-19_05:, , signatures=0 Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org RTC alarm interrupt is active high and already configured by device tree. So remove IRQF_TRIGGER_RISING from driver. Signed-off-by: Amelie Delaunay --- drivers/rtc/rtc-stm32.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index 79d9e86..6a06078 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -663,8 +663,7 @@ static int stm32_rtc_probe(struct platform_device *pdev) /* Handle RTC alarm interrupts */ ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL, - stm32_rtc_alarm_irq, - IRQF_TRIGGER_RISING | IRQF_ONESHOT, + stm32_rtc_alarm_irq, IRQF_ONESHOT, pdev->name, rtc); if (ret) { dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n", From patchwork Thu Apr 19 13:21:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie DELAUNAY X-Patchwork-Id: 901103 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-rtc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40Rfnn47nbz9s1X for ; Thu, 19 Apr 2018 23:23:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753186AbeDSNWp (ORCPT ); Thu, 19 Apr 2018 09:22:45 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:27931 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753059AbeDSNWn (ORCPT ); Thu, 19 Apr 2018 09:22:43 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3JDEkRP018325; Thu, 19 Apr 2018 15:22:03 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hds2asxrs-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 19 Apr 2018 15:22:03 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 82A9938; Thu, 19 Apr 2018 13:22:02 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 597C64EB0; Thu, 19 Apr 2018 13:22:02 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 19 Apr 2018 15:22:02 +0200 Received: from localhost (10.201.20.5) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 19 Apr 2018 15:22:01 +0200 From: Amelie Delaunay To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue CC: , , , , Amelie Delaunay Subject: [PATCH 3/4] dt-bindings: rtc: update stm32-rtc documentation for st, syscfg property Date: Thu, 19 Apr 2018 15:21:42 +0200 Message-ID: <1524144103-21432-4-git-send-email-amelie.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524144103-21432-1-git-send-email-amelie.delaunay@st.com> References: <1524144103-21432-1-git-send-email-amelie.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.5] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-19_05:, , signatures=0 Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org RTC driver should not be aware of the PWR registers offset and bits position. Furthermore, we can imagine that Disable Backup Protection (DBP) relative register and bit mask could change depending on the SoC. So this patch moves st,syscfg property from single pwrcfg phandle to pwrcfg phandle/offset/mask triplet. Signed-off-by: Amelie Delaunay Acked-by: Alexandre TORGUE --- Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt index a66692a..00f8b5d 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt @@ -14,8 +14,10 @@ Required properties: It is required only on stm32h7. - interrupt-parent: phandle for the interrupt controller. - interrupts: rtc alarm interrupt. -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain - (RTC registers) write protection. +- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to + access control register at offset, and change the dbp (Disable Backup + Protection) bit represented by the mask, mandatory to disable/enable backup + domain (RTC registers) write protection. Optional properties (to override default rtc_ck parent clock): - assigned-clocks: reference to the rtc_ck clock entry. @@ -31,7 +33,7 @@ Example: assigned-clock-parents = <&rcc 1 CLK_LSE>; interrupt-parent = <&exti>; interrupts = <17 1>; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; }; rtc: rtc@58004000 { @@ -44,5 +46,5 @@ Example: interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; }; From patchwork Thu Apr 19 13:21:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie DELAUNAY X-Patchwork-Id: 901099 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-rtc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40RfnN28LWz9s2B for ; Thu, 19 Apr 2018 23:23:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750972AbeDSNWu (ORCPT ); Thu, 19 Apr 2018 09:22:50 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:57453 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753180AbeDSNWq (ORCPT ); Thu, 19 Apr 2018 09:22:46 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3JDEewx018303; Thu, 19 Apr 2018 15:22:08 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hds2asxs8-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 19 Apr 2018 15:22:08 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BD48D31; Thu, 19 Apr 2018 13:22:03 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 86B634EB3; Thu, 19 Apr 2018 13:22:03 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 19 Apr 2018 15:22:03 +0200 Received: from localhost (10.201.20.5) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 19 Apr 2018 15:22:02 +0200 From: Amelie Delaunay To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue CC: , , , , Amelie Delaunay Subject: [PATCH 4/4] rtc: stm32: get DBP register and mask from DT st, syscfg property Date: Thu, 19 Apr 2018 15:21:43 +0200 Message-ID: <1524144103-21432-5-git-send-email-amelie.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524144103-21432-1-git-send-email-amelie.delaunay@st.com> References: <1524144103-21432-1-git-send-email-amelie.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.5] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-19_05:, , signatures=0 Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org RTC driver should not be aware of the PWR registers offset and bits position. Furthermore, we can imagine that DBP relative register and bit mask could change depending on the SoC. So this patch introduces 2 parameters, dbp_reg and dbp_mask, allowing to get PWR_CR and PWR_CR_DBP from device tree. And it prepares next RTC version, backup domain write protection is disabled only if needed. Signed-off-by: Amelie Delaunay --- drivers/rtc/rtc-stm32.c | 59 +++++++++++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 22 deletions(-) diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index 6a06078..de49b5b 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -85,23 +85,17 @@ #define RTC_WPR_2ND_KEY 0x53 #define RTC_WPR_WRONG_KEY 0xFF -/* - * RTC registers are protected against parasitic write access. - * PWR_CR_DBP bit must be set to enable write access to RTC registers. - */ -/* STM32_PWR_CR */ -#define PWR_CR 0x00 -/* STM32_PWR_CR bit field */ -#define PWR_CR_DBP BIT(8) - struct stm32_rtc_data { bool has_pclk; + bool need_dbp; }; struct stm32_rtc { struct rtc_device *rtc_dev; void __iomem *base; struct regmap *dbp; + unsigned int dbp_reg; + unsigned int dbp_mask; struct stm32_rtc_data *data; struct clk *pclk; struct clk *rtc_ck; @@ -498,10 +492,12 @@ static const struct rtc_class_ops stm32_rtc_ops = { static const struct stm32_rtc_data stm32_rtc_data = { .has_pclk = false, + .need_dbp = true, }; static const struct stm32_rtc_data stm32h7_rtc_data = { .has_pclk = true, + .need_dbp = true, }; static const struct of_device_id stm32_rtc_of_match[] = { @@ -576,7 +572,6 @@ static int stm32_rtc_probe(struct platform_device *pdev) { struct stm32_rtc *rtc; struct resource *res; - const struct of_device_id *match; int ret; rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); @@ -588,15 +583,31 @@ static int stm32_rtc_probe(struct platform_device *pdev) if (IS_ERR(rtc->base)) return PTR_ERR(rtc->base); - rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "st,syscfg"); - if (IS_ERR(rtc->dbp)) { - dev_err(&pdev->dev, "no st,syscfg\n"); - return PTR_ERR(rtc->dbp); - } + rtc->data = (struct stm32_rtc_data *) + of_device_get_match_data(&pdev->dev); + + if (rtc->data->need_dbp) { + rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "st,syscfg"); + if (IS_ERR(rtc->dbp)) { + dev_err(&pdev->dev, "no st,syscfg\n"); + return PTR_ERR(rtc->dbp); + } - match = of_match_device(stm32_rtc_of_match, &pdev->dev); - rtc->data = (struct stm32_rtc_data *)match->data; + ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg", + 1, &rtc->dbp_reg); + if (ret) { + dev_err(&pdev->dev, "can't read DBP register offset\n"); + return ret; + } + + ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg", + 2, &rtc->dbp_mask); + if (ret) { + dev_err(&pdev->dev, "can't read DBP register mask\n"); + return ret; + } + } if (!rtc->data->has_pclk) { rtc->pclk = NULL; @@ -624,7 +635,9 @@ static int stm32_rtc_probe(struct platform_device *pdev) if (ret) goto err; - regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, PWR_CR_DBP); + if (rtc->data->need_dbp) + regmap_update_bits(rtc->dbp, rtc->dbp_reg, + rtc->dbp_mask, rtc->dbp_mask); /* * After a system reset, RTC_ISR.INITS flag can be read to check if @@ -684,7 +697,8 @@ static int stm32_rtc_probe(struct platform_device *pdev) clk_disable_unprepare(rtc->pclk); clk_disable_unprepare(rtc->rtc_ck); - regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, 0); + if (rtc->data->need_dbp) + regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); device_init_wakeup(&pdev->dev, false); @@ -707,8 +721,9 @@ static int stm32_rtc_remove(struct platform_device *pdev) if (rtc->data->has_pclk) clk_disable_unprepare(rtc->pclk); - /* Enable backup domain write protection */ - regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, 0); + /* Enable backup domain write protection if needed */ + if (rtc->data->need_dbp) + regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); device_init_wakeup(&pdev->dev, false);