From patchwork Thu Mar 7 09:10:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 1909148 X-Patchwork-Delegate: dario.binacchi@amarulasolutions.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=thorsis.com header.i=@thorsis.com header.a=rsa-sha256 header.s=default header.b=kYU0V4Y/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Tr3bC6PKdz1yX4 for ; Thu, 7 Mar 2024 20:16:55 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D097287F87; Thu, 7 Mar 2024 10:11:13 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=thorsis.com header.i=@thorsis.com header.b="kYU0V4Y/"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 65D5387E63; Thu, 7 Mar 2024 10:10:34 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.thorsis.com (mail.thorsis.com [92.198.35.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3448A87C0A for ; Thu, 7 Mar 2024 10:10:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ada@thorsis.com From: Alexander Dahl DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=default; t=1709802616; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6kmjj9hIxPY5EjRg9Xshnk2BmUaj9gQt0E3a6IZtQ88=; b=kYU0V4Y/BWXlTcXQiJz4zRqiNleHzyuQ8uED/WNCkd+cQwrCWhD8WCPEdG7DB8xgrJOsHO Vrn5wNokXxA1QMffjdop3GlFh232skQ+v9ktwggkO8WJjNMhldUwMBBQWfbEB24Ta079/4 zt/hpjztPBfaZfZiyAI4peEtREFyR4AsEjwYAldQmHdh6GUNZRFSfINEk5BYWRpzXiDQwo SX4xfAj8ZgQ7hbmLp1cGRUfE4j5RRupbP2/zvuXKxCg2UzFp9GZksBtDpafuLaymkzc+k5 MHAKcFnaz1k3QjFiRoWC9QWFUBeLWW9eM/dtEnljOXQoAiEVkDS9zZYA7i4gIw== To: Dario Binacchi , Michael Trimarchi Cc: Balamanikandan Gunasundar , Eugen Hristev , u-boot@lists.denx.de Subject: [PATCH 1/4] mtd: nand: raw: Use macro nand_to_mtd() where appropriate Date: Thu, 7 Mar 2024 10:10:11 +0100 Message-Id: <20240307091014.39796-2-ada@thorsis.com> In-Reply-To: <20240307091014.39796-1-ada@thorsis.com> References: <20240307091014.39796-1-ada@thorsis.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In every other place in this file the macro is used, make it consistent. Fixes: 9d1806fadc24 ("mtd: nand: Get rid of mtd variable in function calls") Signed-off-by: Alexander Dahl Reviewed-By: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index c40a0f23d7b..688d17ba3c2 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4118,7 +4118,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) */ void nand_decode_ext_id(struct nand_chip *chip) { - struct mtd_info *mtd = &chip->mtd; + struct mtd_info *mtd = nand_to_mtd(chip); int extid; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); @@ -4185,7 +4185,7 @@ static int nand_manufacturer_init(struct nand_chip *chip) */ static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) { - struct mtd_info *mtd = &chip->mtd; + struct mtd_info *mtd = nand_to_mtd(chip); mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4265,7 +4265,7 @@ static const struct nand_manufacturer *nand_get_manufacturer_desc(u8 id) int nand_detect(struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type) { - struct mtd_info *mtd = &chip->mtd; + struct mtd_info *mtd = nand_to_mtd(chip); const struct nand_manufacturer *manufacturer_desc; int busw, ret; u8 *id_data = chip->id.data; From patchwork Thu Mar 7 09:10:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 1909146 X-Patchwork-Delegate: dario.binacchi@amarulasolutions.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=thorsis.com header.i=@thorsis.com header.a=rsa-sha256 header.s=default header.b=rVJou6Ks; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BB7FE87E6C; Thu, 7 Mar 2024 10:10:32 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail.thorsis.com (mail.thorsis.com [92.198.35.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3B94B87E03 for ; Thu, 7 Mar 2024 10:10:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ada@thorsis.com From: Alexander Dahl DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=default; t=1709802616; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HpygCROxwXeDRgXstUHxFdSmQ6N9fpUk6wuQSCbDdY4=; b=rVJou6Ks6NHcql6VcwdEbeDCSw1772J0eAsxi1tZvcETjmr9ZH4Ga8wo7fa4iUEWnKkzfR qTvtdZ1rDFqdcQ217shgVynrwS5IUTleHSrc/qLpFvgzC2aMXYxt30V70srCTVCWbpTSlU n7xmxPO1B+HyRbWLnnOU7Okywrpcgt2kqhP7T6PfW7jBf0C4ukpHTjrxsJEWWFYwA1o0m/ wDRX1X85j1CEKIzZmc2g1YnaggvzbgrdZ31ZL9wLtzAo0ekO9mkXbYsneCw13hTtWBkOgw mwocASIjEdBGYtRx8ftQH0lepfUOXt+yKN0teIVC8CRNyj/awCE9J4VQoOEY3Q== To: Dario Binacchi , Michael Trimarchi Cc: Balamanikandan Gunasundar , Eugen Hristev , u-boot@lists.denx.de Subject: [PATCH 2/4] mtd: nand: raw: Port another option flag from Linux Date: Thu, 7 Mar 2024 10:10:12 +0100 Message-Id: <20240307091014.39796-3-ada@thorsis.com> In-Reply-To: <20240307091014.39796-1-ada@thorsis.com> References: <20240307091014.39796-1-ada@thorsis.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Introduced in upstream Linux with commit 7a08dbaedd365 for release v5.0. When the new atmel nand driver was backported to U-Boot with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND driver") that definition was added to the driver instead of the header file. Move it over to the other definitions with the same help text it has in Linux. Code actually using this has not been ported over to raw nand base yet. Signed-off-by: Alexander Dahl Reviewed-by: Michael Trimarchi --- drivers/mtd/nand/raw/atmel/nand-controller.c | 2 -- include/linux/mtd/rawnand.h | 7 +++++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 0e0441472b8..e06523f3298 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1429,8 +1429,6 @@ static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline, return nc->caps->ops->setup_data_interface(nand, csline, conf); } -#define NAND_KEEP_TIMINGS 0x00800000 - static void atmel_nand_init(struct atmel_nand_controller *nc, struct atmel_nand *nand) { diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index fb002ae6411..4abaf4734cf 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -249,6 +249,13 @@ enum nand_ecc_algo { */ #define NAND_USE_BOUNCE_BUFFER 0x00100000 +/* + * Do not try to tweak the timings at runtime. This is needed when the + * controller initializes the timings on itself or when it relies on + * configuration done by the bootloader. + */ +#define NAND_KEEP_TIMINGS 0x00800000 + /* Options set by nand scan */ /* bbt has already been read */ #define NAND_BBT_SCANNED 0x40000000 From patchwork Thu Mar 7 09:10:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 1909144 X-Patchwork-Delegate: dario.binacchi@amarulasolutions.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=thorsis.com header.i=@thorsis.com header.a=rsa-sha256 header.s=default header.b=UFD8AuXf; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Tr3Rn4zKKz1yX8 for ; Thu, 7 Mar 2024 20:10:29 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2A62687E3F; Thu, 7 Mar 2024 10:10:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=thorsis.com header.i=@thorsis.com header.b="UFD8AuXf"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5D89F87E6C; Thu, 7 Mar 2024 10:10:20 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.thorsis.com (mail.thorsis.com [92.198.35.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5400687E06 for ; Thu, 7 Mar 2024 10:10:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ada@thorsis.com From: Alexander Dahl DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=default; t=1709802616; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6KryHI/bkICf/7Qce3xa8QpjOYvLhUk2DEhKAgtt9Z8=; b=UFD8AuXfv5/boeJxoO/AfmxnIky3CYo2nMDp7xbDECWRDM9AtaxYrvrcUHEVNeIqRmlaTI LRPpppgh1tbxHZXS2QvV9hoFOJwRcnj86LHJi+8KcOgl6SqDrqj6Nd3AV7ho3qTLjiDw44 yIJE58yMD64G6DP8R9t4wtyA16TD6FWPeKi1o38rgOTmk8tmnPh5nGJbEraRhhgi+RkRUc v+E2VJB29w0bnBuqiADEJClX4/zMaj48BFGaXX4NctTMPbIYcft24UQx1970EPXtlyD2Od lgedRzKZiYis0lUhf7m8kT8LQJIHLKNZn8lJrXYVK4O/+BuadMsq41o8+rewaw== To: Dario Binacchi , Michael Trimarchi Cc: Balamanikandan Gunasundar , Eugen Hristev , u-boot@lists.denx.de Subject: [PATCH 3/4] mtd: nand: raw: Fix (most) Kconfig indentation Date: Thu, 7 Mar 2024 10:10:13 +0100 Message-Id: <20240307091014.39796-4-ada@thorsis.com> In-Reply-To: <20240307091014.39796-1-ada@thorsis.com> References: <20240307091014.39796-1-ada@thorsis.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean One tab in general. One tab plus two spaces for help text. Signed-off-by: Alexander Dahl Reviewed-by: Michael Trimarchi --- drivers/mtd/nand/raw/Kconfig | 106 +++++++++++++++++------------------ 1 file changed, 53 insertions(+), 53 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bb9994b8626..f6644899b0a 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -1,6 +1,6 @@ - menuconfig MTD_RAW_NAND bool "Raw NAND Device Support" + if MTD_RAW_NAND config SYS_NAND_SELF_INIT @@ -49,12 +49,12 @@ config SYS_NAND_NO_SUBPAGE_WRITE depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD config DM_NAND_ATMEL - bool "Support Atmel NAND controller with DM support" - select SYS_NAND_SELF_INIT - imply SYS_NAND_USE_FLASH_BBT - help - Enable this driver for NAND flash platforms using an Atmel NAND - controller. + bool "Support Atmel NAND controller with DM support" + select SYS_NAND_SELF_INIT + imply SYS_NAND_USE_FLASH_BBT + help + Enable this driver for NAND flash platforms using an Atmel NAND + controller. config NAND_ATMEL bool "Support Atmel NAND controller" @@ -133,35 +133,35 @@ config NAND_BRCMNAND_6753 Enable support for broadcom nand driver on bcm6753. config NAND_BRCMNAND_68360 - bool "Support Broadcom NAND controller on bcm68360" - depends on NAND_BRCMNAND && BCM6856 - help - Enable support for broadcom nand driver on bcm68360. + bool "Support Broadcom NAND controller on bcm68360" + depends on NAND_BRCMNAND && BCM6856 + help + Enable support for broadcom nand driver on bcm68360. config NAND_BRCMNAND_6838 - bool "Support Broadcom NAND controller on bcm6838" - depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 - help - Enable support for broadcom nand driver on bcm6838. + bool "Support Broadcom NAND controller on bcm6838" + depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 + help + Enable support for broadcom nand driver on bcm6838. config NAND_BRCMNAND_6858 - bool "Support Broadcom NAND controller on bcm6858" - depends on NAND_BRCMNAND && BCM6858 - help - Enable support for broadcom nand driver on bcm6858. + bool "Support Broadcom NAND controller on bcm6858" + depends on NAND_BRCMNAND && BCM6858 + help + Enable support for broadcom nand driver on bcm6858. config NAND_BRCMNAND_63158 - bool "Support Broadcom NAND controller on bcm63158" - depends on NAND_BRCMNAND && BCM63158 - help - Enable support for broadcom nand driver on bcm63158. + bool "Support Broadcom NAND controller on bcm63158" + depends on NAND_BRCMNAND && BCM63158 + help + Enable support for broadcom nand driver on bcm63158. config NAND_BRCMNAND_IPROC - bool "Support Broadcom NAND controller on the iproc family" - depends on NAND_BRCMNAND - help - Enable support for broadcom nand driver on the Broadcom - iproc family such as Northstar (BCM5301x, BCM4708...) + bool "Support Broadcom NAND controller on the iproc family" + depends on NAND_BRCMNAND + help + Enable support for broadcom nand driver on the Broadcom + iproc family such as Northstar (BCM5301x, BCM4708...) config NAND_DAVINCI bool "Support TI Davinci NAND controller" @@ -413,10 +413,10 @@ config NAND_VF610_NFC if NAND_VF610_NFC config NAND_VF610_NFC_DT - bool "Support Vybrid's vf610 NAND controller as a DT device" - depends on OF_CONTROL && DM_MTD - help - Enable the driver for Vybrid's vf610 NAND flash on platforms + bool "Support Vybrid's vf610 NAND controller as a DT device" + depends on OF_CONTROL && DM_MTD + help + Enable the driver for Vybrid's vf610 NAND flash on platforms using device tree. choice @@ -472,11 +472,11 @@ config NAND_SUNXI select SPL_NAND_SUPPORT select SPL_SYS_NAND_SELF_INIT imply CMD_NAND - ---help--- - Enable support for NAND. This option enables the standard and - SPL drivers. - The SPL driver only supports reading from the NAND using DMA - transfers. + help + Enable support for NAND. This option enables the standard and + SPL drivers. + The SPL driver only supports reading from the NAND using DMA + transfers. if NAND_SUNXI @@ -577,16 +577,16 @@ config NAND_OCTEONTX select SYS_NAND_SELF_INIT imply CMD_NAND help - This enables Nand flash controller hardware found on the OcteonTX - processors. + This enables Nand flash controller hardware found on the OcteonTX + processors. config NAND_OCTEONTX_HW_ECC bool "Support Hardware ECC for OcteonTX NAND controller" depends on NAND_OCTEONTX default y help - This enables Hardware BCH engine found on the OcteonTX processors to - support ECC for NAND flash controller. + This enables Hardware BCH engine found on the OcteonTX processors to + support ECC for NAND flash controller. config NAND_STM32_FMC2 bool "Support for NAND controller on STM32MP SoCs" @@ -751,37 +751,37 @@ config SYS_NAND_BAD_BLOCK_POS config SYS_NAND_U_BOOT_LOCATIONS bool "Define U-Boot binaries locations in NAND" help - Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. - This option should not be enabled when compiling U-Boot for boards - defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/.h - file. + Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. + This option should not be enabled when compiling U-Boot for boards + defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/.h + file. config SYS_NAND_U_BOOT_OFFS hex "Location in NAND to read U-Boot from" default 0x800000 if NAND_SUNXI depends on SYS_NAND_U_BOOT_LOCATIONS help - Set the offset from the start of the nand where u-boot should be - loaded from. + Set the offset from the start of the nand where u-boot should be + loaded from. config SYS_NAND_U_BOOT_OFFS_REDUND hex "Location in NAND to read U-Boot from" default SYS_NAND_U_BOOT_OFFS depends on SYS_NAND_U_BOOT_LOCATIONS help - Set the offset from the start of the nand where the redundant u-boot - should be loaded from. + Set the offset from the start of the nand where the redundant u-boot + should be loaded from. config SPL_NAND_AM33XX_BCH bool "Enables SPL-NAND driver which supports ELM based" depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX default y - help + help Hardware ECC correction. This is useful for platforms which have ELM hardware engine and use NAND boot mode. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling - SPL-NAND driver with software ECC correction support. + SPL-NAND driver with software ECC correction support. config SPL_NAND_DENALI bool "Support Denali NAND controller for SPL" @@ -810,6 +810,6 @@ config SYS_NAND_HW_ECC_OOBFIRST bool "In SPL, read the OOB first and then the data from NAND" depends on SPL_NAND_SIMPLE -endif +endif # if SPL -endif # if NAND +endif # if MTD_RAW_NAND From patchwork Thu Mar 7 09:10:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 1909145 X-Patchwork-Delegate: dario.binacchi@amarulasolutions.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=thorsis.com header.i=@thorsis.com header.a=rsa-sha256 header.s=default header.b=vnWdXrUA; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Tr3VD748gz1yX8 for ; Thu, 7 Mar 2024 20:12:36 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9021987E06; Thu, 7 Mar 2024 10:10:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=thorsis.com header.i=@thorsis.com header.b="vnWdXrUA"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B4ACC87E71; Thu, 7 Mar 2024 10:10:22 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.thorsis.com (mail.thorsis.com [92.198.35.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7C0C687E39 for ; Thu, 7 Mar 2024 10:10:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ada@thorsis.com From: Alexander Dahl DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=default; t=1709802617; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qXd3xb7uyrh1PNFH/tRLuwWuWvft7EAXNn5j9Ibuyzo=; b=vnWdXrUA6Ju+IS75D5j4vN67f1uaKwFL4E2iv3E4amhU60vDBFao9tMbjPCXVwAT0ZrqjL jyBWZTv6dMC5QO9d5n7hkhFOgSCkWMeAZLYSyK9cFCwinjIrsTzeAkzl0h9ZMSfeaBnX6f Bi3gZbqJjygPdVjfYXYf3SjgUTA1uHq5F4dx3UwI303kg7ZEz+K7Veo6ZWib8vI86Ebgf1 zvdX9XvMJS40tj1wdtE+DqxeWgESMFyTtpxDVcIMmm+IPCSIy1ejpHjxtqfahl8ABJ3XY0 9xRxvcpjW3AXGcRPge6tGbmfM4Jc5bRLHTHakMQXcDN3Ckl3YkGew+kviHVqvQ== To: Dario Binacchi , Michael Trimarchi Cc: Balamanikandan Gunasundar , Eugen Hristev , u-boot@lists.denx.de Subject: [PATCH 4/4] mtd: nand: raw: atmel: Introduce optional debug commands Date: Thu, 7 Mar 2024 10:10:14 +0100 Message-Id: <20240307091014.39796-5-ada@thorsis.com> In-Reply-To: <20240307091014.39796-1-ada@thorsis.com> References: <20240307091014.39796-1-ada@thorsis.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean For now adds one new command 'hsmc' with a single subcommand 'decode' to read and display the content of the registers of the Static Memory Controllers (SMC/HSMC) found in different at91 SoCs. Needed to get a better picture on what raw nand core and atmel nand controller driver try to set as timings based on ONFI parameters of the connected NAND chip. Tested on SAMA5D2 and SAM9X60 based boards. Example output: U-Boot> hsmc decode mck clock rate: 200000000 SMC_SETUP3: 0x00000002 SMC_PULSE3: 0x07040703 SMC_CYCLE3: 0x00070007 SMC_MODE3: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) NCS_WR: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) NWE: setup: 2 (10 ns), pulse: 3 (15 ns), hold: 2 (10 ns), cycle: 7 (35 ns) Standard read is applied. TDF optimization enabled TDF cycles: 15 (75 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal Signed-off-by: Alexander Dahl Tested-by: Mihai Sain Tested-by: Mihai Sain --- drivers/mtd/nand/raw/Kconfig | 9 + drivers/mtd/nand/raw/atmel/nand-controller.c | 249 +++++++++++++++++++ 2 files changed, 258 insertions(+) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index f6644899b0a..43057aa6c5b 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -50,12 +50,21 @@ config SYS_NAND_NO_SUBPAGE_WRITE config DM_NAND_ATMEL bool "Support Atmel NAND controller with DM support" + select MFD_ATMEL_SMC select SYS_NAND_SELF_INIT imply SYS_NAND_USE_FLASH_BBT help Enable this driver for NAND flash platforms using an Atmel NAND controller. +config CMD_NAND_ATMEL_DEBUG + bool "Optional debug commands for Atmel NAND controller" + depends on DM_NAND_ATMEL + help + Add commands for debugging internals of the Atmel NAND flash + controller, for example: + - Decode Static Memory Controller (SMC) registers + config NAND_ATMEL bool "Support Atmel NAND controller" select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index e06523f3298..052d9c7b82a 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -51,11 +51,13 @@ #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -69,6 +71,7 @@ #include #include #include +#include #include "pmecc.h" @@ -216,6 +219,7 @@ struct atmel_nand_controller_ops { int (*ecc_init)(struct nand_chip *chip); int (*setup_data_interface)(struct atmel_nand *nand, int csline, const struct nand_data_interface *conf); + void (*print_info)(struct atmel_nand *nand, int csline); }; struct atmel_nand_controller_caps { @@ -2041,12 +2045,214 @@ err: return ret; } +#ifdef CONFIG_CMD_NAND_ATMEL_DEBUG +u32 atmel_smc_decode_ncycles(u32 reg, u32 shift, u32 msbpos, u32 msbwidth, u32 msbfactor) +{ + /* + * Examples: + * + * NRD setup length = (128 * NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles. + * NRD pulse length = (256 * NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles. + * Read cycle length = (NRD_CYCLE[8:7] * 256) + NRD_CYCLE[6:0] clock cycles. + */ + + reg >>= shift; + + u32 lsbmask = GENMASK(msbpos - 1, 0); + u32 msbmask = GENMASK(msbwidth - 1, 0) << msbpos; + u32 msb = (reg & msbmask) >> msbpos; + u32 lsb = (reg & lsbmask); + + return msb * msbfactor + lsb; +} + +static void atmel_smc_cs_conf_print_raw(struct atmel_smc_cs_conf *conf, int cs) +{ + printf("SMC_SETUP%d: 0x%08x\n", cs, conf->setup); + printf("SMC_PULSE%d: 0x%08x\n", cs, conf->pulse); + printf("SMC_CYCLE%d: 0x%08x\n", cs, conf->cycle); + printf("SMC_MODE%d: 0x%08x\n", cs, conf->mode); +} + +static void atmel_hsmc_cs_conf_print_raw(struct atmel_smc_cs_conf *conf, int cs) +{ + printf("HSMC_SETUP%d: 0x%08x\n", cs, conf->setup); + printf("HSMC_PULSE%d: 0x%08x\n", cs, conf->pulse); + printf("HSMC_CYCLE%d: 0x%08x\n", cs, conf->cycle); + printf("HSMC_TIMINGS%d: 0x%08x\n", cs, conf->timings); + printf("HSMC_MODE%d: 0x%08x\n", cs, conf->mode); +} + +static void atmel_smc_print_reg(const char *name, u32 setup, u32 pulse, + u32 cycle, u32 clk_period_ns) +{ + u32 hold = cycle - pulse - setup; + + printf("%6s: setup: %u (%u ns), pulse: %u (%u ns), hold: %u (%u ns), cycle: %u (%u ns)\n", + name, setup, setup * clk_period_ns, pulse, pulse * clk_period_ns, + hold, hold * clk_period_ns, cycle, cycle * clk_period_ns); +} + +static void atmel_smc_print_ncs_rd(struct atmel_smc_cs_conf *conf, u32 clk_period_ns) +{ + u32 ncs_rd_setup = atmel_smc_decode_ncycles(conf->setup, 24, 5, 1, 128); + u32 ncs_rd_pulse = atmel_smc_decode_ncycles(conf->pulse, 24, 6, 1, 256); + u32 nrd_cycle = atmel_smc_decode_ncycles(conf->cycle, 16, 7, 2, 256); + + atmel_smc_print_reg("NCS_RD", ncs_rd_setup, ncs_rd_pulse, + nrd_cycle, clk_period_ns); +} + +static void atmel_smc_print_nrd(struct atmel_smc_cs_conf *conf, u32 clk_period_ns) +{ + u32 nrd_setup = atmel_smc_decode_ncycles(conf->setup, 16, 5, 1, 128); + u32 nrd_pulse = atmel_smc_decode_ncycles(conf->pulse, 16, 6, 1, 256); + u32 nrd_cycle = atmel_smc_decode_ncycles(conf->cycle, 16, 7, 2, 256); + + atmel_smc_print_reg("NRD", nrd_setup, nrd_pulse, nrd_cycle, clk_period_ns); +} + +static void atmel_smc_print_ncs_wr(struct atmel_smc_cs_conf *conf, u32 clk_period_ns) +{ + u32 ncs_wr_setup = atmel_smc_decode_ncycles(conf->setup, 8, 5, 1, 128); + u32 ncs_wr_pulse = atmel_smc_decode_ncycles(conf->pulse, 8, 6, 1, 256); + u32 nwe_cycle = atmel_smc_decode_ncycles(conf->cycle, 0, 7, 2, 256); + + atmel_smc_print_reg("NCS_WR", ncs_wr_setup, ncs_wr_pulse, + nwe_cycle, clk_period_ns); +} + +static void atmel_smc_print_nwe(struct atmel_smc_cs_conf *conf, u32 clk_period_ns) +{ + u32 nwe_setup = atmel_smc_decode_ncycles(conf->setup, 0, 5, 1, 128); + u32 nwe_pulse = atmel_smc_decode_ncycles(conf->pulse, 0, 6, 1, 256); + u32 nwe_cycle = atmel_smc_decode_ncycles(conf->cycle, 0, 7, 2, 256); + + atmel_smc_print_reg("NWE", nwe_setup, nwe_pulse, nwe_cycle, clk_period_ns); +} + +static void atmel_smc_print_mode(struct atmel_smc_cs_conf *conf, u32 clk_period_ns) +{ + u32 tdf; + u8 dbw; + + if (conf->mode & BIT(24)) { + printf("Asynchronous burst read in Page mode is applied on the corresponding chip select.\n"); + printf("Page Size: %u-byte page\n", + 4 << ((conf->mode & GENMASK(29, 28)) >> 28)); + } else { + printf("Standard read is applied.\n"); + } + + tdf = (conf->mode & GENMASK(19, 16)) >> 16; + printf("TDF optimization %s\n", + (conf->mode & BIT(20)) ? "enabled" : "disabled"); + printf("TDF cycles: %u (%u ns)\n", tdf, tdf * clk_period_ns); + + dbw = 8 << ((conf->mode & GENMASK(13, 12)) >> 12); + printf("Data Bus Width: %u-bit bus\n", dbw); + if (dbw > 8) + printf("Byte %s access type\n", + (conf->mode & BIT(8)) ? "write" : "select"); + + printf("NWAIT Mode: %lu\n", (conf->mode & GENMASK(5, 4)) >> 4); + printf("Write operation controlled by %s signal\n", + (conf->mode & BIT(1)) ? "NWE" : "NCS"); + printf("Read operation controlled by %s signal\n", + (conf->mode & BIT(0)) ? "NRD" : "NCS"); +} + +static void atmel_hsmc_print_mode(struct atmel_smc_cs_conf *conf, u32 clk_period_ns) +{ + u32 tdf; + u8 dbw; + + tdf = (conf->mode & GENMASK(19, 16)) >> 16; + printf("TDF optimization %s\n", + (conf->mode & BIT(20)) ? "enabled" : "disabled"); + printf("TDF cycles: %u (%u ns)\n", tdf, tdf * clk_period_ns); + + dbw = 8 << ((conf->mode & BIT(12)) >> 12); + printf("Data Bus Width: %u-bit bus\n", dbw); + if (dbw > 8) + printf("Byte %s access type\n", + (conf->mode & BIT(8)) ? "write" : "select"); + + printf("NWAIT Mode: %lu\n", (conf->mode & GENMASK(5, 4)) >> 4); + printf("Write operation controlled by %s signal\n", + (conf->mode & BIT(1)) ? "NWE" : "NCS"); + printf("Read operation controlled by %s signal\n", + (conf->mode & BIT(0)) ? "NRD" : "NCS"); +} + +static void atmel_hsmc_print_timings(struct atmel_smc_cs_conf *conf) +{ + /* tbd */ +} + +static void atmel_smc_print_info(struct atmel_nand *nand, int csline) +{ + struct atmel_nand_controller *nc; + struct atmel_smc_cs_conf smcconf; + struct atmel_nand_cs *cs; + u32 mck_period_ns; + + nc = to_nand_controller(nand->controller); + cs = &nand->cs[csline]; + + atmel_smc_cs_conf_init(&smcconf); + atmel_smc_cs_conf_get(nc->smc, cs->id, &smcconf); + + atmel_smc_cs_conf_print_raw(&smcconf, cs->id); + + mck_period_ns = NSEC_PER_SEC / clk_get_rate(nc->mck); + + atmel_smc_print_ncs_rd(&smcconf, mck_period_ns); + atmel_smc_print_nrd(&smcconf, mck_period_ns); + atmel_smc_print_ncs_wr(&smcconf, mck_period_ns); + atmel_smc_print_nwe(&smcconf, mck_period_ns); + + atmel_smc_print_mode(&smcconf, mck_period_ns); +} + +static void atmel_hsmc_print_info(struct atmel_nand *nand, int csline) +{ + struct atmel_hsmc_nand_controller *hsmc_nc; + struct atmel_nand_controller *nc; + struct atmel_smc_cs_conf smcconf; + struct atmel_nand_cs *cs; + u32 mck_period_ns; + + nc = to_nand_controller(nand->controller); + hsmc_nc = to_hsmc_nand_controller(nand->controller); + cs = &nand->cs[csline]; + + atmel_smc_cs_conf_init(&smcconf); + atmel_hsmc_cs_conf_get(nc->smc, hsmc_nc->hsmc_layout, cs->id, &smcconf); + + atmel_hsmc_cs_conf_print_raw(&smcconf, cs->id); + + mck_period_ns = NSEC_PER_SEC / clk_get_rate(nc->mck); + + atmel_smc_print_ncs_rd(&smcconf, mck_period_ns); + atmel_smc_print_nrd(&smcconf, mck_period_ns); + atmel_smc_print_ncs_wr(&smcconf, mck_period_ns); + atmel_smc_print_nwe(&smcconf, mck_period_ns); + + atmel_hsmc_print_mode(&smcconf, mck_period_ns); + atmel_hsmc_print_timings(&smcconf); +} +#endif + static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = { .probe = atmel_hsmc_nand_controller_probe, .remove = atmel_hsmc_nand_controller_remove, .ecc_init = atmel_hsmc_nand_ecc_init, .nand_init = atmel_hsmc_nand_init, .setup_data_interface = atmel_hsmc_nand_setup_data_interface, +#ifdef CONFIG_CMD_NAND_ATMEL_DEBUG + .print_info = atmel_hsmc_print_info, +#endif }; static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = { @@ -2117,6 +2323,9 @@ static const struct atmel_nand_controller_ops atmel_smc_nc_ops = { .ecc_init = atmel_nand_ecc_init, .nand_init = atmel_smc_nand_init, .setup_data_interface = atmel_smc_nand_setup_data_interface, +#ifdef CONFIG_CMD_NAND_ATMEL_DEBUG + .print_info = atmel_smc_print_info, +#endif }; static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = { @@ -2247,3 +2456,43 @@ void board_nand_init(void) printf("Failed to initialize NAND controller. (error %d)\n", ret); } + +#ifdef CONFIG_CMD_NAND_ATMEL_DEBUG +static int do_hsmc_decode(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct atmel_nand_controller *nc; + struct atmel_nand *nand; + struct nand_chip *chip; + struct mtd_info *mtd; + int i, j; + + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) { + putc('\n'); + mtd = get_nand_dev_by_index(i); + if (!mtd) + continue; + + chip = mtd_to_nand(mtd); + nand = to_atmel_nand(chip); + nc = to_nand_controller(nand->controller); + printf("mck clock rate: %lu\n", clk_get_rate(nc->mck)); + if (!nc->caps->ops->print_info) + continue; + + for (j = 0; j < nand->numcs; j++) { + putc('\n'); + nc->caps->ops->print_info(nand, j); + } + } + + return CMD_RET_SUCCESS; +} + +static char hsmc_help_text[] = + "decode - Decode SMC registers\n" + ; + +U_BOOT_CMD_WITH_SUBCMDS(hsmc, "Atmel Static Memory Controller (SMC) debugging", hsmc_help_text, + U_BOOT_SUBCMD_MKENT(decode, 1, 1, do_hsmc_decode)); +#endif