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envelope-from=hchauhan@ventanamicro.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The debug property implements the ratified debug specification v0.13. This specification is superseded by (now frozen) RISC-V debug specification v1.0 It defines sdtrig ISA extension which is forward and backward comptible with the debug specification v0.13. This patch deprecates the debug property and replaces with ext_sdtrig. A deprecation warning is displayed if debug property is used. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 37 ++++++++++++++++++++++++++++++++++--- target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 2 +- 5 files changed, 38 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5ff0192c52..5d5d8f0375 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -996,7 +996,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } @@ -1156,7 +1156,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_cpu_register_gdb_regs_for_features(cs); #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_realize(&cpu->env); } #endif @@ -1718,6 +1718,37 @@ static const PropertyInfo prop_mmu = { .set = prop_mmu_set, }; +static void prop_debug_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + bool value; + + warn_report("\"debug\" property is being deprecated."); + + visit_type_bool(v, name, &value, errp); + + if (cpu->cfg.ext_sdtrig != value && !riscv_cpu_is_dynamic(obj)) { + return; + } + + cpu->cfg.ext_sdtrig = value; +} + +static void prop_debug_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value = RISCV_CPU(obj)->cfg.ext_sdtrig; + + visit_type_bool(v, name, &value, errp); +} + +static const PropertyInfo prop_debug = { + .name = "debug", + .get = prop_debug_get, + .set = prop_debug_set, +}; + static void prop_pmp_set(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2229,7 +2260,7 @@ RISCVCPUProfile *riscv_profiles[] = { }; static Property riscv_cpu_properties[] = { - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + {.name = "debug", .info = &prop_debug}, /* Deprecated */ {.name = "pmu-mask", .info = &prop_pmu_mask}, {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */ diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 833bf58217..9fb4ca577f 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -113,6 +113,7 @@ struct RISCVCPUConfig { bool ext_zvfbfwma; bool ext_zvfh; bool ext_zvfhmin; + bool ext_sdtrig; bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf; @@ -148,7 +149,6 @@ struct RISCVCPUConfig { uint16_t cboz_blocksize; bool mmu; bool pmp; - bool debug; bool misa_w; bool short_isa_string; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d462d95ee1..b2ad97d601 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -129,7 +129,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; } - if (cpu->cfg.debug && !icount_enabled()) { + if (cpu->cfg.ext_sdtrig && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4e8ac13b9..e60599d74e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -546,7 +546,7 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno) static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->debug) { + if (riscv_cpu_cfg(env)->ext_sdtrig) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 81cf22894e..1b775342d2 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -230,7 +230,7 @@ static bool debug_needed(void *opaque) { RISCVCPU *cpu = opaque; - return cpu->cfg.debug; + return cpu->cfg.ext_sdtrig; } static int debug_post_load(void *opaque, int version_id) From patchwork Thu Feb 29 13:37:45 2024 Content-Type: text/plain; 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Thu, 29 Feb 2024 05:38:50 -0800 (PST) Received: from localhost.localdomain ([49.37.249.67]) by smtp.gmail.com with ESMTPSA id g1-20020a170902fe0100b001dc941f145dsm1454918plj.253.2024.02.29.05.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Feb 2024 05:38:50 -0800 (PST) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Himanshu Chauhan Subject: [PATCH v3 2/2] target/riscv: Export sdtrig in ISA string Date: Thu, 29 Feb 2024 19:07:45 +0530 Message-Id: <20240229133745.771154-3-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229133745.771154-1-hchauhan@ventanamicro.com> References: <20240229133745.771154-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=hchauhan@ventanamicro.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled. The sdtrig extension may or may not be implemented in a system. Therefore, the -cpu rv64,sdtrig= option can be used to dynamically turn sdtrig extension on or off. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5d5d8f0375..6f98c0195c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1461,6 +1461,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, true), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), @@ -1724,7 +1725,7 @@ static void prop_debug_set(Object *obj, Visitor *v, const char *name, RISCVCPU *cpu = RISCV_CPU(obj); bool value; - warn_report("\"debug\" property is being deprecated."); + warn_report("\"debug\" property is deprecated; use \"sdtrig\""); visit_type_bool(v, name, &value, errp);