From patchwork Wed Apr 18 20:26:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 900382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=cogentembedded.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=cogentembedded-com.20150623.gappssmtp.com header.i=@cogentembedded-com.20150623.gappssmtp.com header.b="glIHTUs0"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40RDDG32GKz9s0x for ; Thu, 19 Apr 2018 06:26:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751520AbeDRU0h (ORCPT ); Wed, 18 Apr 2018 16:26:37 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:41507 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750872AbeDRU0g (ORCPT ); Wed, 18 Apr 2018 16:26:36 -0400 Received: by mail-lf0-f65.google.com with SMTP id m202-v6so4535729lfe.8 for ; Wed, 18 Apr 2018 13:26:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:cc:references:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Cb39WpbP5ZBtEdzgEf6vYhco5RoSlTuPfBrtd1Oc9PI=; b=glIHTUs0ufllFsLxPUND4hsiaJjqVmU01qGCfpPbSn6E+zldUNB/larPB0664jv7xR uajjmOxOIDk6/Et2eyLPxUrejmJg6fXuvu0JZttJ5Am99sCK0TRz6sN0jlFld0e2wT8a QrntMqyZTtnLrNXL9EvEQSl2cZZqlNz+kVPpI/4+SyvYYpgZZ7ieFjmW9mGVGxTxZsLh p1ya0BiCU2b2NzsKeDJYDbhwl2eKzd5K1c3WApT47xXgHU5xF/G9foWoR2arMM+qh2YO y7OGH9zvH0k+6qaKlMUOI/DiwHZapCBhNkNtPOXiuRJY9R0TLhfLyIqPSEd0nbqzcYYH jRSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=Cb39WpbP5ZBtEdzgEf6vYhco5RoSlTuPfBrtd1Oc9PI=; b=XS46WQrvkl1scjmWz8Qas5vpbipc+SL3AQHcK/BRvms857l+QwsY5jzkcEbzghQJAv Tn/lz5cF7uQTEU9aj2+gO6nvGe4WvDX0e3HTI2QHZ966B06h6n02WhyOGlLL1WJFqwWc Zva6+4/jSgKdAs0pN4Kc8t/sSEMfszRTpLERgMdiaPZnq74S5h++s8F6/Y+dkHZwDGqw p3MgKGV+cicD31Kt+AO078QgIU6v1VDKTfwWLi5hrx+sQMEogTMP9zBXiCV2BTIdKxsG P5+MC4PMydTSvZm3fP6qyc8doZRGulrEB9VKXxdxMRR5ZPTYxeOmnv0RKXATN9h48MhG nL2g== X-Gm-Message-State: ALQs6tBDzCtDDDKFLxG5PJcEqGrjJgo9iJTiERwb0DcjNGOkG/wstrrP fxxJAfFs4YBKfSc3wF1ejSiCbg== X-Google-Smtp-Source: AIpwx484sk4TxzAH2dI513Eabr8sM7S6QTayN8j7HBI5CbjwUPHBOyT0edkFSTqrS4QFeX+kfbw6rw== X-Received: by 2002:a19:d78a:: with SMTP id q10-v6mr2337849lfi.132.1524083194807; Wed, 18 Apr 2018 13:26:34 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.84.112]) by smtp.gmail.com with ESMTPSA id 66-v6sm419140lfp.85.2018.04.18.13.26.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Apr 2018 13:26:33 -0700 (PDT) From: Sergei Shtylyov Subject: [PATCH v2] pinctrl: sh-pfc: r8a77970: fix pin I/O voltage control support To: Linus Walleij , Geert Uytterhoeven , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Laurent Pinchart References: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Organization: Cogent Embedded Message-ID: Date: Wed, 18 Apr 2018 23:26:32 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Content-Language: en-MW Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org I've included the pin I/O voltage control into the R8A77970 PFC driver but it was incomplete because: - SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly; - sh_pfc_soc_info::ioctrl_regs wasn't set at all... Fixes: b92ac66a1819 ("pinctrl: sh-pfc: Add R8A77970 PFC support") Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo. Changes in version 2: - fixed the commit SHA1 in the "Fixes:" tag. drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c =================================================================== --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c @@ -21,13 +21,15 @@ #include "core.h" #include "sh_pfc.h" +#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH + #define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH) + PORT_GP_CFG_22(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_6(4, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_15(5, fn, sfx, CFG_FLAGS) /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -2382,18 +2384,33 @@ static const struct pinmux_cfg_reg pinmu { }, }; +enum ioctrl_regs { + IOCTRL30, + IOCTRL31, + IOCTRL32, + IOCTRL40, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [IOCTRL30] = { 0xe6060380 }, + [IOCTRL31] = { 0xe6060384 }, + [IOCTRL32] = { 0xe6060388 }, + [IOCTRL40] = { 0xe60603c0 }, + { /* sentinel */ }, +}; + static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; - *pocctrl = 0xe6060380; + *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) return bit; if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) return bit + 22; - *pocctrl += 4; + *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg; if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) return bit - 10; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) @@ -2421,6 +2438,7 @@ const struct sh_pfc_soc_info r8a77970_pi .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data),