From patchwork Wed Apr 18 14:46:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900166 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4jp6d7Fz9s4c for ; Thu, 19 Apr 2018 00:48:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752634AbeDROqw (ORCPT ); Wed, 18 Apr 2018 10:46:52 -0400 Received: from smtprelay.synopsys.com ([198.182.60.111]:38740 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751305AbeDROqu (ORCPT ); Wed, 18 Apr 2018 10:46:50 -0400 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 9426110C14B3; Wed, 18 Apr 2018 07:46:50 -0700 (PDT) Received: from pt02.synopsys.com (pt02.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 4B17636FA; Wed, 18 Apr 2018 07:46:50 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id 7487A3E57D; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 1/9] bindings: PCI: designware: Example update Date: Wed, 18 Apr 2018 15:46:36 +0100 Message-Id: <96c1e63ce9e869626996a918fcb2dbcf642519a7.1524062073.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers, however it still be compatible with any previous DT that uses the old reg-name. Replaces the PCIe base address example by a real PCIe base address in use. Signed-off-by: Gustavo Pimentel Reviewed-by: Rob Herring --- Changes v1->v2: - Removed any iATU reference or changes to avoid confusion. - Add "snps,dw-pcie" compatible string following Kishon's suggestion. Changes v2->v3: - Nothing changed, just to follow the patch set version. Changes v3->v4: - Reverted "snps,dw-pcie-rc" compatible string requested by Rob Herring. Changes v4->v5: - Nothing changed, just to follow the patch set version. Changes v5->v6: - Nothing changed, just to follow the patch set version. Documentation/devicetree/bindings/pci/designware-pcie.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 1da7ade..7f9804d 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -1,7 +1,8 @@ * Synopsys DesignWare PCIe interface Required properties: -- compatible: should contain "snps,dw-pcie" to identify the core. +- compatible: + "snps,dw-pcie" for RC mode; - reg: Should contain the configuration address space. - reg-names: Must be "config" for the PCIe configuration space. (The old way of getting the configuration address space from "ranges" @@ -41,11 +42,11 @@ EP mode: Example configuration: - pcie: pcie@dffff000 { + pcie: pcie@dfc00000 { compatible = "snps,dw-pcie"; - reg = <0xdffff000 0x1000>, /* Controller registers */ - <0xd0000000 0x2000>; /* PCI config space */ - reg-names = "ctrlreg", "config"; + reg = <0xdfc00000 0x0001000>, /* IP registers */ + <0xd0000000 0x0002000>; /* Configuration space */ + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -54,5 +55,4 @@ Example configuration: interrupts = <25>, <24>; #interrupt-cells = <1>; num-lanes = <1>; - num-viewport = <3>; }; From patchwork Wed Apr 18 14:46:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900170 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4kv1N26z9s4c for ; Thu, 19 Apr 2018 00:49:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753057AbeDROsp (ORCPT ); Wed, 18 Apr 2018 10:48:45 -0400 Received: from smtprelay.synopsys.com ([198.182.47.9]:50240 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752144AbeDROqv (ORCPT ); Wed, 18 Apr 2018 10:46:51 -0400 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id C099E24E2143; Wed, 18 Apr 2018 07:46:50 -0700 (PDT) Received: from pt02.synopsys.com (pt02.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 4B1B750C6; Wed, 18 Apr 2018 07:46:50 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id 8344F3E580; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 2/9] PCI: dwc: Add support for endpoint mode Date: Wed, 18 Apr 2018 15:46:37 +0100 Message-Id: <25b9e886c7aad2e45ae71b08342ac034af46773f.1524062073.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCIe controller dual mode is capable of operating in host mode as well as endpoint mode by configuration, therefore this patch aims to add endpoint mode support to the designware driver. Signed-off-by: Gustavo Pimentel Acked-by: Kishon Vijay Abraham I --- Change v1->v2: - Removed dw_plat_pcie_stop_link empty function. - Implemented Kishon's suggestions about dw-pcie-rc and dw-pcie strings. compatibility. - Added second entry on pci_epf_test_ids structure. Changes v2->v3: - Reverted additions in dw_pcie_ep_linkup function. - Replaced devm_ioremap by devm_ioremap_resource function. - Moved second entry in pci_epf_test_ids structure into a new patch file. Changes v3->v4: - Reverted "snps,dw-pcie-rc" compatible string requested by Rob Herring. Changes v4->v5: - Nothing changed, just to follow the patch set version. Changes v5->v6: - Removed PCIE_DW_PLAT entry helps and description in order to be hidden. drivers/pci/dwc/Kconfig | 41 ++++++--- drivers/pci/dwc/pcie-designware-plat.c | 149 ++++++++++++++++++++++++++++++--- 2 files changed, 169 insertions(+), 21 deletions(-) diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index 2f3f5c5..62f7cdf 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -7,8 +7,7 @@ config PCIE_DW config PCIE_DW_HOST bool - depends on PCI - depends on PCI_MSI_IRQ_DOMAIN + depends on PCI && PCI_MSI_IRQ_DOMAIN select PCIE_DW config PCIE_DW_EP @@ -51,17 +50,37 @@ config PCI_DRA7XX_EP This uses the DesignWare core. config PCIE_DW_PLAT - bool "Platform bus based DesignWare PCIe Controller" - depends on PCI - depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW_HOST - ---help--- - This selects the DesignWare PCIe controller support. Select this if - you have a PCIe controller on Platform bus. + bool - If you have a controller with this interface, say Y or M here. +config PCIE_DW_PLAT_HOST + bool "Platform bus based DesignWare PCIe Controller - Host mode" + depends on PCI && PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + select PCIE_DW_PLAT + default y + help + Enables support for the PCIe controller in the Designware IP to + work in host mode. There are two instances of PCIe controller in + Designware IP. + This controller can work either as EP or RC. In order to enable + host-specific features PCIE_DW_PLAT_HOST must be selected and in + order to enable device-specific features PCI_DW_PLAT_EP must be + selected. - If unsure, say N. +config PCIE_DW_PLAT_EP + bool "Platform bus based DesignWare PCIe Controller - Endpoint mode" + depends on PCI && PCI_MSI_IRQ_DOMAIN + depends on PCI_ENDPOINT + select PCIE_DW_EP + select PCIE_DW_PLAT + help + Enables support for the PCIe controller in the Designware IP to + work in endpoint mode. There are two instances of PCIe controller + in Designware IP. + This controller can work either as EP or RC. In order to enable + host-specific features PCIE_DW_PLAT_HOST must be selected and in + order to enable device-specific features PCI_DW_PLAT_EP must be + selected. config PCI_EXYNOS bool "Samsung Exynos PCIe controller" diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c index 5416aa8..efc315c 100644 --- a/drivers/pci/dwc/pcie-designware-plat.c +++ b/drivers/pci/dwc/pcie-designware-plat.c @@ -12,19 +12,29 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include "pcie-designware.h" struct dw_plat_pcie { - struct dw_pcie *pci; + struct dw_pcie *pci; + struct regmap *regmap; + enum dw_pcie_device_mode mode; }; +struct dw_plat_pcie_of_data { + enum dw_pcie_device_mode mode; +}; + +static const struct of_device_id dw_plat_pcie_of_match[]; + static int dw_plat_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -42,9 +52,53 @@ static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { .host_init = dw_plat_pcie_host_init, }; -static int dw_plat_add_pcie_port(struct pcie_port *pp, +static int dw_plat_pcie_establish_link(struct dw_pcie *pci) +{ + return 0; +} + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = dw_plat_pcie_establish_link, +}; + +static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar; + + for (bar = BAR_0; bar <= BAR_5; bar++) + dw_pcie_ep_reset_bar(pci, bar); +} + +static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u8 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + dev_err(pci->dev, "EP cannot trigger legacy IRQs\n"); + return -EINVAL; + case PCI_EPC_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + } + + return 0; +} + +static struct dw_pcie_ep_ops pcie_ep_ops = { + .ep_init = dw_plat_pcie_ep_init, + .raise_irq = dw_plat_pcie_ep_raise_irq, +}; + +static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie, struct platform_device *pdev) { + struct dw_pcie *pci = dw_plat_pcie->pci; + struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; int ret; @@ -63,15 +117,44 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp, ret = dw_pcie_host_init(pp); if (ret) { - dev_err(dev, "failed to initialize host\n"); + dev_err(dev, "Failed to initialize host\n"); return ret; } return 0; } -static const struct dw_pcie_ops dw_pcie_ops = { -}; +static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie, + struct platform_device *pdev) +{ + int ret; + struct dw_pcie_ep *ep; + struct resource *res; + struct device *dev = &pdev->dev; + struct dw_pcie *pci = dw_plat_pcie->pci; + + ep = &pci->ep; + ep->ops = &pcie_ep_ops; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); + pci->dbi_base2 = devm_ioremap_resource(dev, res); + if (IS_ERR(pci->dbi_base2)) + return PTR_ERR(pci->dbi_base2); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->phys_base = res->start; + ep->addr_size = resource_size(res); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "Failed to initialize endpoint\n"); + return ret; + } + return 0; +} static int dw_plat_pcie_probe(struct platform_device *pdev) { @@ -80,6 +163,16 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct resource *res; /* Resource from DT */ int ret; + const struct of_device_id *match; + const struct dw_plat_pcie_of_data *data; + enum dw_pcie_device_mode mode; + + match = of_match_device(dw_plat_pcie_of_match, dev); + if (!match) + return -EINVAL; + + data = (struct dw_plat_pcie_of_data *)match->data; + mode = (enum dw_pcie_device_mode)data->mode; dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL); if (!dw_plat_pcie) @@ -93,23 +186,59 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) pci->ops = &dw_pcie_ops; dw_plat_pcie->pci = pci; + dw_plat_pcie->mode = mode; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + if (!res) + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pci->dbi_base = devm_ioremap_resource(dev, res); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); platform_set_drvdata(pdev, dw_plat_pcie); - ret = dw_plat_add_pcie_port(&pci->pp, pdev); - if (ret < 0) - return ret; + switch (dw_plat_pcie->mode) { + case DW_PCIE_RC_TYPE: + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST)) + return -ENODEV; + + ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev); + if (ret < 0) + return ret; + break; + case DW_PCIE_EP_TYPE: + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP)) + return -ENODEV; + + ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev); + if (ret < 0) + return ret; + break; + default: + dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode); + } return 0; } +static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = { + .mode = DW_PCIE_RC_TYPE, +}; + +static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = { + .mode = DW_PCIE_EP_TYPE, +}; + static const struct of_device_id dw_plat_pcie_of_match[] = { - { .compatible = "snps,dw-pcie", }, + { + .compatible = "snps,dw-pcie", + .data = &dw_plat_pcie_rc_of_data, + }, + { + .compatible = "snps,dw-pcie-ep", + .data = &dw_plat_pcie_ep_of_data, + }, {}, }; From patchwork Wed Apr 18 14:46:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900161 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4j84Bwsz9s4c for ; Thu, 19 Apr 2018 00:47:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752864AbeDROqy (ORCPT ); Wed, 18 Apr 2018 10:46:54 -0400 Received: from smtprelay4.synopsys.com ([198.182.47.9]:50234 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752135AbeDROqv (ORCPT ); Wed, 18 Apr 2018 10:46:51 -0400 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 9A6CD24E206E; Wed, 18 Apr 2018 07:46:50 -0700 (PDT) Received: from pt02.synopsys.com (pt02.internal.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 36AA53A28; Wed, 18 Apr 2018 07:46:50 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id 9073E3E584; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 3/9] PCI: endpoint: functions/pci-epf-test: Add second entry Date: Wed, 18 Apr 2018 15:46:38 +0100 Message-Id: <9efd4af2f91e1be2b65d2df93444b35871673e8b.1524062073.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Adds a seconds entry on the pci_epf_test_ids structure that disables the linkup_notifier parameter on driver for the designware EP. This allows designware EPs that doesn't have linkup notification signal to work with pcitest. Updates the binding documentation accordingly. Signed-off-by: Gustavo Pimentel Acked-by: Kishon Vijay Abraham I --- Change v2->v3: - Added second entry in pci_epf_test_ids structure. - Remove test_reg_bar field assignment on second entry. Changes v3->v4: - Nothing changed, just to follow the patch set version. Changes v4->v5: - Changed pci_epf_test_cfg2 to pci_epf_test_designware. Changes v5->v6: - Changed name field from pci_epf_test_designware to pci_epf_test_dw. Documentation/PCI/endpoint/function/binding/pci-test.txt | 2 ++ drivers/pci/endpoint/functions/pci-epf-test.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.txt b/Documentation/PCI/endpoint/function/binding/pci-test.txt index 3b68b95..dc39f47 100644 --- a/Documentation/PCI/endpoint/function/binding/pci-test.txt +++ b/Documentation/PCI/endpoint/function/binding/pci-test.txt @@ -1,6 +1,8 @@ PCI TEST ENDPOINT FUNCTION name: Should be "pci_epf_test" to bind to the pci_epf_test driver. +name: Should be "pci_epf_test_dw" to bind to the pci_epf_test driver + with a custom configuration for the designware EP. Configurable Fields: vendorid : should be 0x104c diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 7cef851..b7dff87 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -459,10 +459,18 @@ static int pci_epf_test_bind(struct pci_epf *epf) return 0; } +static const struct pci_epf_test_data data_cfg2 = { + .linkup_notifier = false +}; + static const struct pci_epf_device_id pci_epf_test_ids[] = { { .name = "pci_epf_test", }, + { + .name = "pci_epf_test_dw", + .driver_data = (kernel_ulong_t)&data_cfg2, + }, {}, }; From patchwork Wed Apr 18 14:46:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900163 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4jB1lz4z9s4c for ; Thu, 19 Apr 2018 00:47:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752806AbeDROqx (ORCPT ); Wed, 18 Apr 2018 10:46:53 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:50226 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751256AbeDROqu (ORCPT ); Wed, 18 Apr 2018 10:46:50 -0400 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 894FD24E200A; Wed, 18 Apr 2018 07:46:50 -0700 (PDT) Received: from pt02.synopsys.com (pt02.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 44B4F36F9; Wed, 18 Apr 2018 07:46:50 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id 9D3933E587; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 4/9] bindings: PCI: designware: Add support for the EP in Designware driver Date: Wed, 18 Apr 2018 15:46:39 +0100 Message-Id: <9ead29e037d7e399b2a647efc1393c6556feb8b2.1524062073.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add device tree binding documentation for the Endpoint in PCIe Designware driver. Signed-off-by: Gustavo Pimentel Reviewed-by: Rob Herring --- Change v1->v2: - Add a missing log description. - Add "snps,dw-pcie" compatible string following Kishon's suggestion. Change v2->v3: - Reverted pcie_ep name to pcie. Changes v3->v4: - Reverted "snps,dw-pcie-rc" compatible string requested by Rob Herring. Changes v4->v5: - Removed device_type entry from EP requested by Rob Herring. Changes v5->v6: - Nothing changed, just to follow the patch set version. Documentation/devicetree/bindings/pci/designware-pcie.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 7f9804d..c124f9b 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -3,6 +3,7 @@ Required properties: - compatible: "snps,dw-pcie" for RC mode; + "snps,dw-pcie-ep" for EP mode; - reg: Should contain the configuration address space. - reg-names: Must be "config" for the PCIe configuration space. (The old way of getting the configuration address space from "ranges" @@ -56,3 +57,14 @@ Example configuration: #interrupt-cells = <1>; num-lanes = <1>; }; +or + pcie: pcie@dfc00000 { + compatible = "snps,dw-pcie-ep"; + reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ + <0xdfc01000 0x0001000>, /* IP registers 2 */ + <0xd0000000 0x2000000>; /* Configuration space */ + reg-names = "dbi", "dbi2", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-lanes = <1>; + }; From patchwork Wed Apr 18 14:46:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900168 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4kJ6vVqz9s4n for ; Thu, 19 Apr 2018 00:48:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753050AbeDROsQ (ORCPT ); Wed, 18 Apr 2018 10:48:16 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:50245 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752162AbeDROqv (ORCPT ); Wed, 18 Apr 2018 10:46:51 -0400 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 5675024E2149; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from pt02.synopsys.com (pt02.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 170EA3714; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id B02CD3E58A; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 5/9] misc: pci_endpoint_test: Add designware EP entry Date: Wed, 18 Apr 2018 15:46:40 +0100 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Adds the designware EP device ID entry to pci_endpoint_test driver table to allow this device to be recognize and handle by the pci_endpoint_test driver. Signed-off-by: Gustavo Pimentel Acked-by: Kishon Vijay Abraham I --- Change v1->v2: - Changed device id following Kishon's suggestion. Change v2->v3: - Nothing changed, just to follow the patch set version. Changes v3->v4: - Nothing changed, just to follow the patch set version. Changes v4->v5: - Nothing changed, just to follow the patch set version. Changes v5->v6: - Reverted Kishon's suggestion by Bjorn request. drivers/misc/pci_endpoint_test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index fe8897e..58a88ba 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -634,6 +634,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) }, + { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); From patchwork Wed Apr 18 14:46:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900171 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4ky4WP4z9s4c for ; Thu, 19 Apr 2018 00:49:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752705AbeDROso (ORCPT ); Wed, 18 Apr 2018 10:48:44 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111]:38743 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752159AbeDROqv (ORCPT ); Wed, 18 Apr 2018 10:46:51 -0400 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 53E3510C1518; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from pt02.synopsys.com (pt02.internal.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 11D9C3A4E; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id BB4553E58D; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 6/9] PCI: dwc: Define maximum number of vectors Date: Wed, 18 Apr 2018 15:46:41 +0100 Message-Id: <94ef244ea1b69bb610e282b59be77baea555797a.1524062073.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Adds a callback that defines the maximum number of vectors that can be use by the Root Complex. Since this is a parameter associated to each SoC IP setting, makes sense to be configurable and easily visible to future modifications. The designware IP supports a maximum of 256 vectors. Signed-off-by: Gustavo Pimentel Acked-by: Joao Pinto --- Change v1->v2: - Nothing changed, just to follow the patch set version. Change v2->v3: - Nothing changed, just to follow the patch set version. Changes v3->v4: - Nothing changed, just to follow the patch set version. Changes v4->v5: - Nothing changed, just to follow the patch set version. Changes v5->v6: - Nothing changed, just to follow the patch set version. drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c index efc315c..5937fed 100644 --- a/drivers/pci/dwc/pcie-designware-plat.c +++ b/drivers/pci/dwc/pcie-designware-plat.c @@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp) return 0; } +static void dw_plat_set_num_vectors(struct pcie_port *pp) +{ + pp->num_vectors = MAX_MSI_IRQS; +} + static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { .host_init = dw_plat_pcie_host_init, + .set_num_vectors = dw_plat_set_num_vectors, }; static int dw_plat_pcie_establish_link(struct dw_pcie *pci) From patchwork Wed Apr 18 14:46:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900164 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4jX4dkYz9s4n for ; Thu, 19 Apr 2018 00:48:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753251AbeDROrn (ORCPT ); Wed, 18 Apr 2018 10:47:43 -0400 Received: from smtprelay2.synopsys.com ([198.182.60.111]:38753 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752532AbeDROqw (ORCPT ); Wed, 18 Apr 2018 10:46:52 -0400 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 979D010C152B; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from pt02.synopsys.com (pt02.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 2D9F2371A; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id C76773E599; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 7/9] PCI: dwc: Replace lower into upper case characters Date: Wed, 18 Apr 2018 15:46:42 +0100 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Replaces lower into upper case characters in comments and debug printks. This is an attempt to keep the messages coherent within the designware driver. Also fixed code style on dw_pcie_irq_domain_free function. Signed-off-by: Gustavo Pimentel Acked-by: Jingoo Han Acked-by: Joao Pinto --- Change v1->v2: - Added an extra log description line about code style following Fabio Estevam suggestion. Change v2->v3: - Nothing changed, just to follow the patch set version. Changes v3->v4: - Nothing changed, just to follow the patch set version. Changes v4->v5: - Nothing changed, just to follow the patch set version. Changes v5->v6: - Nothing changed, just to follow the patch set version. drivers/pci/dwc/pcie-designware-ep.c | 16 ++++++++-------- drivers/pci/dwc/pcie-designware-host.c | 35 ++++++++++++++++++---------------- drivers/pci/dwc/pcie-designware.c | 22 ++++++++++----------- 3 files changed, 38 insertions(+), 35 deletions(-) diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c index f07678b..15b22a6 100644 --- a/drivers/pci/dwc/pcie-designware-ep.c +++ b/drivers/pci/dwc/pcie-designware-ep.c @@ -75,7 +75,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar, free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows); if (free_win >= ep->num_ib_windows) { - dev_err(pci->dev, "no free inbound window\n"); + dev_err(pci->dev, "No free inbound window\n"); return -EINVAL; } @@ -100,7 +100,7 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr, free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows); if (free_win >= ep->num_ob_windows) { - dev_err(pci->dev, "no free outbound window\n"); + dev_err(pci->dev, "No free outbound window\n"); return -EINVAL; } @@ -204,7 +204,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size); if (ret) { - dev_err(pci->dev, "failed to enable address\n"); + dev_err(pci->dev, "Failed to enable address\n"); return ret; } @@ -348,21 +348,21 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); if (ret < 0) { - dev_err(dev, "unable to read *num-ib-windows* property\n"); + dev_err(dev, "Unable to read *num-ib-windows* property\n"); return ret; } if (ep->num_ib_windows > MAX_IATU_IN) { - dev_err(dev, "invalid *num-ib-windows*\n"); + dev_err(dev, "Invalid *num-ib-windows*\n"); return -EINVAL; } ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows); if (ret < 0) { - dev_err(dev, "unable to read *num-ob-windows* property\n"); + dev_err(dev, "Unable to read *num-ob-windows* property\n"); return ret; } if (ep->num_ob_windows > MAX_IATU_OUT) { - dev_err(dev, "invalid *num-ob-windows*\n"); + dev_err(dev, "Invalid *num-ob-windows*\n"); return -EINVAL; } @@ -389,7 +389,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) epc = devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { - dev_err(dev, "failed to create epc device\n"); + dev_err(dev, "Failed to create epc device\n"); return PTR_ERR(epc); } diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 6c409079..5a23f78 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -248,8 +248,10 @@ static void dw_pcie_irq_domain_free(struct irq_domain *domain, unsigned long flags; raw_spin_lock_irqsave(&pp->lock, flags); + bitmap_release_region(pp->msi_irq_in_use, data->hwirq, order_base_2(nr_irqs)); + raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -266,7 +268,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { - dev_err(pci->dev, "failed to create IRQ domain\n"); + dev_err(pci->dev, "Failed to create IRQ domain\n"); return -ENOMEM; } @@ -274,7 +276,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) &dw_pcie_msi_domain_info, pp->irq_domain); if (!pp->msi_domain) { - dev_err(pci->dev, "failed to create MSI domain\n"); + dev_err(pci->dev, "Failed to create MSI domain\n"); irq_domain_remove(pp->irq_domain); return -ENOMEM; } @@ -301,13 +303,13 @@ void dw_pcie_msi_init(struct pcie_port *pp) page = alloc_page(GFP_KERNEL); pp->msi_data = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); if (dma_mapping_error(dev, pp->msi_data)) { - dev_err(dev, "failed to map MSI data\n"); + dev_err(dev, "Failed to map MSI data\n"); __free_page(page); return; } msi_target = (u64)pp->msi_data; - /* program the msi_data */ + /* Program the msi_data */ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, lower_32_bits(msi_target)); dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, @@ -335,7 +337,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_base = cfg_res->start; pp->cfg1_base = cfg_res->start + pp->cfg0_size; } else if (!pp->va_cfg0_base) { - dev_err(dev, "missing *config* reg space\n"); + dev_err(dev, "Missing *config* reg space\n"); } bridge = pci_alloc_host_bridge(0); @@ -357,7 +359,7 @@ int dw_pcie_host_init(struct pcie_port *pp) case IORESOURCE_IO: ret = pci_remap_iospace(win->res, pp->io_base); if (ret) { - dev_warn(dev, "error %d: failed to map resource %pR\n", + dev_warn(dev, "Error %d: failed to map resource %pR\n", ret, win->res); resource_list_destroy_entry(win); } else { @@ -391,7 +393,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg->start, resource_size(pp->cfg)); if (!pci->dbi_base) { - dev_err(dev, "error with ioremap\n"); + dev_err(dev, "Error with ioremap\n"); ret = -ENOMEM; goto error; } @@ -403,7 +405,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, pp->cfg0_base, pp->cfg0_size); if (!pp->va_cfg0_base) { - dev_err(dev, "error with ioremap in function\n"); + dev_err(dev, "Error with ioremap in function\n"); ret = -ENOMEM; goto error; } @@ -414,7 +416,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg1_base, pp->cfg1_size); if (!pp->va_cfg1_base) { - dev_err(dev, "error with ioremap\n"); + dev_err(dev, "Error with ioremap\n"); ret = -ENOMEM; goto error; } @@ -586,7 +588,7 @@ static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, return 0; } - /* access only one slot on each root port */ + /* Access only one slot on each root port */ if (bus->number == pp->root_bus_nr && dev > 0) return 0; @@ -652,11 +654,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) for (ctrl = 0; ctrl < num_ctrls; ctrl++) dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4, &pp->irq_status[ctrl]); - /* setup RC BARs */ + + /* Setup RC BARs */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); - /* setup interrupt pins */ + /* Setup interrupt pins */ dw_pcie_dbi_ro_wr_en(pci); val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); val &= 0xffff00ff; @@ -664,13 +667,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); dw_pcie_dbi_ro_wr_dis(pci); - /* setup bus numbers */ + /* Setup bus numbers */ val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); val &= 0xff000000; val |= 0x00ff0100; dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); - /* setup command register */ + /* Setup command register */ val = dw_pcie_readl_dbi(pci, PCI_COMMAND); val &= 0xffff0000; val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | @@ -683,7 +686,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { - /* get iATU unroll support */ + /* Get iATU unroll support */ pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? "enabled" : "disabled"); @@ -701,7 +704,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) /* Enable write permission for the DBI read-only register */ dw_pcie_dbi_ro_wr_en(pci); - /* program correct class for RC */ + /* Program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); /* Better disable write permission right after the update */ dw_pcie_dbi_ro_wr_dis(pci); diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 1b7282e..778c4f7 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -69,7 +69,7 @@ u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, ret = dw_pcie_read(base + reg, size, &val); if (ret) - dev_err(pci->dev, "read DBI address failed\n"); + dev_err(pci->dev, "Read DBI address failed\n"); return val; } @@ -86,7 +86,7 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, ret = dw_pcie_write(base + reg, size, val); if (ret) - dev_err(pci->dev, "write DBI address failed\n"); + dev_err(pci->dev, "Write DBI address failed\n"); } static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) @@ -137,7 +137,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); } - dev_err(pci->dev, "outbound iATU is not being enabled\n"); + dev_err(pci->dev, "Outbound iATU is not being enabled\n"); } void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, @@ -180,7 +180,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); } - dev_err(pci->dev, "outbound iATU is not being enabled\n"); + dev_err(pci->dev, "Outbound iATU is not being enabled\n"); } static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg) @@ -238,7 +238,7 @@ static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); } - dev_err(pci->dev, "inbound iATU is not being enabled\n"); + dev_err(pci->dev, "Inbound iATU is not being enabled\n"); return -EBUSY; } @@ -284,7 +284,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar, usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); } - dev_err(pci->dev, "inbound iATU is not being enabled\n"); + dev_err(pci->dev, "Inbound iATU is not being enabled\n"); return -EBUSY; } @@ -313,16 +313,16 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) { int retries; - /* check if the link is up or not */ + /* Check if the link is up or not */ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { if (dw_pcie_link_up(pci)) { - dev_info(pci->dev, "link up\n"); + dev_info(pci->dev, "Link up\n"); return 0; } usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); } - dev_err(pci->dev, "phy link never came up\n"); + dev_err(pci->dev, "Phy link never came up\n"); return -ETIMEDOUT; } @@ -351,7 +351,7 @@ void dw_pcie_setup(struct dw_pcie *pci) if (ret) lanes = 0; - /* set the number of lanes */ + /* Set the number of lanes */ val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_MODE_MASK; switch (lanes) { @@ -373,7 +373,7 @@ void dw_pcie_setup(struct dw_pcie *pci) } dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - /* set link width speed control register */ + /* Set link width speed control register */ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val &= ~PORT_LOGIC_LINK_WIDTH_MASK; switch (lanes) { From patchwork Wed Apr 18 14:46:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900169 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4kN123Pz9s4c for ; Thu, 19 Apr 2018 00:48:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752599AbeDROsQ (ORCPT ); Wed, 18 Apr 2018 10:48:16 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:50252 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752511AbeDROqv (ORCPT ); Wed, 18 Apr 2018 10:46:51 -0400 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 7809124E214C; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from pt02.synopsys.com (pt02.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 316F1371B; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id D57C73E59C; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 8/9] PCI: dwc: Small computation improvement Date: Wed, 18 Apr 2018 15:46:43 +0100 Message-Id: <6d3c32707fbae671715d502d72fc87e881c79d28.1524062073.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Replaces a simple division by 2 to a right shift rotation of 1 bit. Probably any recent and decent compiler does this kind of substitution in order to improve code performance. Nevertheless it's a coding good practice whenever there is a division / multiplication by multiple of 2 to replace it by the equivalent operation in this case, the shift rotation. Signed-off-by: Gustavo Pimentel Acked-by: Jingoo Han Acked-by: Joao Pinto --- Change v1->v2: - Nothing changed, just to follow the patch set version. Change v2->v3: - Nothing changed, just to follow the patch set version. Changes v3->v4: - Added a small explication to the log description. Changes v4->v5: - Nothing changed, just to follow the patch set version. Changes v5->v6: - Nothing changed, just to follow the patch set version. drivers/pci/dwc/pcie-designware-host.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 5a23f78..fc55fde 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -332,8 +332,8 @@ int dw_pcie_host_init(struct pcie_port *pp) cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (cfg_res) { - pp->cfg0_size = resource_size(cfg_res) / 2; - pp->cfg1_size = resource_size(cfg_res) / 2; + pp->cfg0_size = resource_size(cfg_res) >> 1; + pp->cfg1_size = resource_size(cfg_res) >> 1; pp->cfg0_base = cfg_res->start; pp->cfg1_base = cfg_res->start + pp->cfg0_size; } else if (!pp->va_cfg0_base) { @@ -377,8 +377,8 @@ int dw_pcie_host_init(struct pcie_port *pp) break; case 0: pp->cfg = win->res; - pp->cfg0_size = resource_size(pp->cfg) / 2; - pp->cfg1_size = resource_size(pp->cfg) / 2; + pp->cfg0_size = resource_size(pp->cfg) >> 1; + pp->cfg1_size = resource_size(pp->cfg) >> 1; pp->cfg0_base = pp->cfg->start; pp->cfg1_base = pp->cfg->start + pp->cfg0_size; break; From patchwork Wed Apr 18 14:46:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 900165 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40R4jm0Yysz9s4s for ; Thu, 19 Apr 2018 00:48:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753183AbeDROrm (ORCPT ); Wed, 18 Apr 2018 10:47:42 -0400 Received: from smtprelay2.synopsys.com ([198.182.60.111]:38759 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752617AbeDROqw (ORCPT ); Wed, 18 Apr 2018 10:46:52 -0400 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id B635910C1541; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from pt02.synopsys.com (pt02.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 31955371C; Wed, 18 Apr 2018 07:46:51 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id E05853E59F; Wed, 18 Apr 2018 15:46:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v6 9/9] PCI: dwc: Replace magic number by defines Date: Wed, 18 Apr 2018 15:46:44 +0100 Message-Id: <4eaca0f71b6966178ac2085450bdb813c692f858.1524062073.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Replace magic numbers by a well known define in order to make the code human readable and also facilitate the code reusability. Signed-off-by: Gustavo Pimentel Acked-by: Jingoo Han --- Change v1->v2: - Nothing changed, just to follow the patch set version. Change v2->v3: - Nothing changed, just to follow the patch set version. Changes v3->v4: - Nothing changed, just to follow the patch set version. Changes v4->v5: - Nothing changed, just to follow the patch set version. Changes v5->v6: - Nothing changed, just to follow the patch set version. drivers/pci/dwc/pcie-designware-host.c | 34 ++++++++++++++++++++-------------- drivers/pci/dwc/pcie-designware.h | 1 + 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index fc55fde..a7657ab 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -83,18 +83,23 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; for (i = 0; i < num_ctrls; i++) { - dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, - &val); + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + + (i * MSI_REG_CTRL_BLOCK_SIZE), + 4, &val); if (!val) continue; ret = IRQ_HANDLED; pos = 0; - while ((pos = find_next_bit((unsigned long *) &val, 32, - pos)) != 32) { - irq = irq_find_mapping(pp->irq_domain, i * 32 + pos); + while ((pos = find_next_bit((unsigned long *) &val, + MAX_MSI_IRQS_PER_CTRL, + pos)) != MAX_MSI_IRQS_PER_CTRL) { + irq = irq_find_mapping(pp->irq_domain, + (i * MAX_MSI_IRQS_PER_CTRL) + + pos); generic_handle_irq(irq); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + + (i * MSI_REG_CTRL_BLOCK_SIZE), 4, 1 << pos); pos++; } @@ -157,9 +162,9 @@ static void dw_pci_bottom_mask(struct irq_data *data) if (pp->ops->msi_clear_irq) { pp->ops->msi_clear_irq(pp, data->hwirq); } else { - ctrl = data->hwirq / 32; - res = ctrl * 12; - bit = data->hwirq % 32; + ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; pp->irq_status[ctrl] &= ~(1 << bit); dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, @@ -180,9 +185,9 @@ static void dw_pci_bottom_unmask(struct irq_data *data) if (pp->ops->msi_set_irq) { pp->ops->msi_set_irq(pp, data->hwirq); } else { - ctrl = data->hwirq / 32; - res = ctrl * 12; - bit = data->hwirq % 32; + ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; pp->irq_status[ctrl] |= 1 << bit; dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, @@ -652,8 +657,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp) /* Initialize IRQ Status array */ for (ctrl = 0; ctrl < num_ctrls; ctrl++) - dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4, - &pp->irq_status[ctrl]); + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, &pp->irq_status[ctrl]); /* Setup RC BARs */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index fe811db..bee4e25 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -110,6 +110,7 @@ #define MAX_MSI_IRQS 256 #define MAX_MSI_IRQS_PER_CTRL 32 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) +#define MSI_REG_CTRL_BLOCK_SIZE 12 #define MSI_DEF_NUM_VECTORS 32 /* Maximum number of inbound/outbound iATUs */