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Tue, 13 Feb 2024 03:21:54 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41D3Lrru010121 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 13 Feb 2024 03:21:53 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 12 Feb 2024 19:21:53 -0800 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] aarch64: Use vec_perm_indices::new_shrunk_vector in aarch64_evpc_reencode Date: Mon, 12 Feb 2024 19:21:29 -0800 Message-ID: <20240213032129.3744441-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gDeB4CFATVcQKUyiGlNV458BgtDsSD9S X-Proofpoint-ORIG-GUID: gDeB4CFATVcQKUyiGlNV458BgtDsSD9S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_20,2024-02-12_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402130023 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org While working on PERM related stuff, I can across that aarch64_evpc_reencode was manually figuring out if we shrink the perm indices instead of using vec_perm_indices::new_shrunk_vector; shrunk was added after reencode was added. Built and tested for aarch64-linux-gnu with no regressions. gcc/ChangeLog: PR target/113822 * config/aarch64/aarch64.cc (aarch64_evpc_reencode): Use vec_perm_indices::new_shrunk_vector instead of manually going through the indices. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64.cc | 24 +++++------------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 32eae49d4e9..f4ed8b86532 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -25431,7 +25431,6 @@ static bool aarch64_evpc_reencode (struct expand_vec_perm_d *d) { expand_vec_perm_d newd; - unsigned HOST_WIDE_INT nelt; if (d->vec_flags != VEC_ADVSIMD) return false; @@ -25446,24 +25445,10 @@ aarch64_evpc_reencode (struct expand_vec_perm_d *d) if (new_mode == word_mode) return false; - /* to_constant is safe since this routine is specific to Advanced SIMD - vectors. */ - nelt = d->perm.length ().to_constant (); - - vec_perm_builder newpermconst; - newpermconst.new_vector (nelt / 2, nelt / 2, 1); + vec_perm_indices newpermindices; - /* Convert the perm constant if we can. Require even, odd as the pairs. */ - for (unsigned int i = 0; i < nelt; i += 2) - { - poly_int64 elt0 = d->perm[i]; - poly_int64 elt1 = d->perm[i + 1]; - poly_int64 newelt; - if (!multiple_p (elt0, 2, &newelt) || maybe_ne (elt0 + 1, elt1)) - return false; - newpermconst.quick_push (newelt.to_constant ()); - } - newpermconst.finalize (); + if (!newpermindices.new_shrunk_vector (d->perm, 2)) + return false; newd.vmode = new_mode; newd.vec_flags = VEC_ADVSIMD; @@ -25475,7 +25460,8 @@ aarch64_evpc_reencode (struct expand_vec_perm_d *d) newd.testing_p = d->testing_p; newd.one_vector_p = d->one_vector_p; - newd.perm.new_vector (newpermconst, newd.one_vector_p ? 1 : 2, nelt / 2); + newd.perm.new_vector (newpermindices.encoding (), newd.one_vector_p ? 1 : 2, + newpermindices.nelts_per_input ()); return aarch64_expand_vec_perm_const_1 (&newd); }