From patchwork Thu Feb 8 15:21:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1896640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TW11n0K3Cz23hn for ; Fri, 9 Feb 2024 02:22:19 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DE3F73858417 for ; Thu, 8 Feb 2024 15:22:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 495913858C5F for ; Thu, 8 Feb 2024 15:21:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 495913858C5F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 495913858C5F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707405714; cv=none; b=PTN2aibjeEekdr5ncrPTdNKTctbtBUAiiwyQLSGIwHsguArZ6OWwj5/TRAWKNXVsOUd/XwRPjPRt6O/M9poqd4do48/gewcKwu9HIJo2lU+HBAGq8jRoQeQMPUMqezmqCcs1TySnI+bVSy+2CU7yEzEB2qQ7FyDb++e21UU5cRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707405714; c=relaxed/simple; bh=USNrvrTFjalmo+QYbcJ1dzawB5+auUB49e8ghGQFhgI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=C+EX0Tv3LY8R7fJzS9z2mNo5akw18HKAlbKGzcnHlipiZjYv04OdDs1qvdUaGNPpWZLpxyjYr+PexdT8qwfMFqc1QDxkSDpX5ys7BL7/C0A8SnXl/J2jS6wc+CzHYztOf8bWOHz6U17Xnq6xuk3pjMqL3drsLwhXbA3JUKxXT7g= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 10B701FB; Thu, 8 Feb 2024 07:22:32 -0800 (PST) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.78.54]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 389AB3F64C; Thu, 8 Feb 2024 07:21:49 -0800 (PST) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH] arm: testsuite: fix issues relating to fp16 alternative testing Date: Thu, 8 Feb 2024 15:21:26 +0000 Message-Id: <20240208152126.1327674-1-rearnsha@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org The v*_fp16_xN_1.c tests on Arm have been unstable since they were added. This is not a problem with the tests themselves, or even the patches that were added, but with the testsuite infrastructure. It turned out that another set of dg- tests for fp16 were corrupting the cached set of options used by the new tests, leading to running the tests with incorrect flags. So the primary goal of this patch is to fix the incorrect internal caching of the options needed to enable fp16 alternative format on Arm: the code was storing the result in the same variable that was being used for neon_fp16 and this was leading to testsuite instability for tests that were checking for neon with fp16. But in cleaning this up I also noted that we weren't then applying the flags correctly having detected what they were, so we also address that. I suspect there are still some further issues to address here, since the framework does not correctly test that the multilibs and startup code enable alternative format; but this is still an improvement over what we had before. gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_arm_fp16_alternative_ok_nocache): Use et_arm_fp16_alternative_flags to cache the result. Improve test for FP16 availability. (add_options_for_arm_fp16_alternative): Use et_arm_fp16_alternative_flags. * g++.dg/ext/arm-fp16/arm-fp16-ops-3.C: Update dg-* flags. * g++.dg/ext/arm-fp16/arm-fp16-ops-4.C: Likewise. * gcc.dg/torture/arm-fp16-int-convert-alt.c: Likewise. * gcc.dg/torture/arm-fp16-ops-3.c: Likewise. * gcc.dg/torture/arm-fp16-ops-4.c: Likewise. * gcc.target/arm/fp16-aapcs-3.c: Likewise. * gcc.target/arm/fp16-aapcs-4.c: Likewise. * gcc.target/arm/fp16-compile-alt-1.c: Likewise. * gcc.target/arm/fp16-compile-alt-10.c: Likewise. * gcc.target/arm/fp16-compile-alt-11.c: Likewise. * gcc.target/arm/fp16-compile-alt-12.c: Likewise. * gcc.target/arm/fp16-compile-alt-2.c: Likewise. * gcc.target/arm/fp16-compile-alt-3.c: Likewise. * gcc.target/arm/fp16-compile-alt-4.c: Likewise. * gcc.target/arm/fp16-compile-alt-5.c: Likewise. * gcc.target/arm/fp16-compile-alt-6.c: Likewise. * gcc.target/arm/fp16-compile-alt-7.c: Likewise. * gcc.target/arm/fp16-compile-alt-8.c: Likewise. * gcc.target/arm/fp16-compile-alt-9.c: Likewise. * gcc.target/arm/fp16-rounding-alt-1.c: Likewise. --- .../g++.dg/ext/arm-fp16/arm-fp16-ops-3.C | 2 +- .../g++.dg/ext/arm-fp16/arm-fp16-ops-4.C | 3 ++- .../gcc.dg/torture/arm-fp16-int-convert-alt.c | 2 +- gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c | 2 +- gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c | 3 ++- gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c | 3 ++- gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c | 3 ++- .../gcc.target/arm/fp16-compile-alt-1.c | 2 +- .../gcc.target/arm/fp16-compile-alt-10.c | 3 ++- .../gcc.target/arm/fp16-compile-alt-11.c | 3 ++- .../gcc.target/arm/fp16-compile-alt-12.c | 2 +- .../gcc.target/arm/fp16-compile-alt-2.c | 2 +- .../gcc.target/arm/fp16-compile-alt-3.c | 2 +- .../gcc.target/arm/fp16-compile-alt-4.c | 2 +- .../gcc.target/arm/fp16-compile-alt-5.c | 2 +- .../gcc.target/arm/fp16-compile-alt-6.c | 2 +- .../gcc.target/arm/fp16-compile-alt-7.c | 3 ++- .../gcc.target/arm/fp16-compile-alt-8.c | 2 +- .../gcc.target/arm/fp16-compile-alt-9.c | 2 +- .../gcc.target/arm/fp16-rounding-alt-1.c | 4 +++- gcc/testsuite/lib/target-supports.exp | 16 ++++++++-------- 21 files changed, 37 insertions(+), 28 deletions(-) diff --git a/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C index 29080c7514f..5eceb3074df 100644 --- a/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C @@ -1,6 +1,6 @@ /* Test various operators on __fp16 and mixed __fp16/float operands. */ /* { dg-do run { target arm*-*-* } } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ #include "arm-fp16-ops.h" diff --git a/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C index 4be8883faad..d86019f1469 100644 --- a/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C @@ -1,6 +1,7 @@ /* Test various operators on __fp16 and mixed __fp16/float operands. */ /* { dg-do run { target arm*-*-* } } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative -ffast-math" } */ +/* { dg-options "-ffast-math" } */ +/* { dg-add-options arm_fp16_alternative } */ #include "arm-fp16-ops.h" diff --git a/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c b/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c index f013b59ddde..42171d4e83e 100644 --- a/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c @@ -1,7 +1,7 @@ /* Test floating-point conversions. Standard types and __fp16. */ /* { dg-do run { target arm*-*-* } } */ /* { dg-require-effective-target arm_fp16_alternative_ok } -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ #include "fp-int-convert.h" #define FP16_MANT_DIG 11 diff --git a/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c index 7716baf818e..3f0aecf357b 100644 --- a/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c @@ -1,6 +1,6 @@ /* Test various operators on __fp16 and mixed __fp16/float operands. */ /* { dg-do run { target arm*-*-* } } */ /* { dg-require-effective-target arm_fp16_alternative_ok } -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ #include "arm-fp16-ops.h" diff --git a/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c index 1940f4320d0..846515b5eab 100644 --- a/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c @@ -1,6 +1,7 @@ /* Test various operators on __fp16 and mixed __fp16/float operands. */ /* { dg-do run { target arm*-*-* } } */ /* { dg-require-effective-target arm_fp16_alternative_ok } -/* { dg-options "-mfp16-format=alternative -ffast-math" } */ +/* { dg-options "-ffast-math" } */ +/* { dg-add-options arm_fp16_alternative } */ #include "arm-fp16-ops.h" diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c index 858181cdd85..56a3ae26184 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c @@ -1,7 +1,8 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-O2 -mfp16-format=alternative" } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_fp16_alternative } */ /* Test __fp16 arguments and return value in registers (hard-float). */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c index ae65fb86184..daac29137ae 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfloat-abi=softfp -O2 -mfp16-format=alternative" } */ +/* { dg-options "-mfloat-abi=softfp -O2" } */ +/* { dg-add-options arm_fp16_alternative } */ /* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */ /* Test __fp16 arguments and return value in registers (softfp). */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c index 0845e886a83..ab5e1d5f430 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ __fp16 xx = 0.0; diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c index a8772a19ae0..985299d2645 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */ +/* { dg-options "-pedantic -std=gnu99" } */ +/* { dg-add-options arm_fp16_alternative } */ #include diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c index 1cb3d2c4963..7c506e9a884 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */ +/* { dg-options "-pedantic -std=gnu99" } */ +/* { dg-add-options arm_fp16_alternative } */ #include diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c index 3c3bd2f02f6..f7cb3f04558 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ float xx __attribute__((mode(HF))) = 0.0; diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c index 8a45f1f4ae1..a3eebfee189 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ /* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ /* 0x3c00 = 15360 */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c index 7221766284e..c1ae6de7c11 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ /* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ /* 0xc000 = 49152 */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c index cfeb61aaea7..e244bd1745e 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ /* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ /* 0x7bff = 31743 */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c index 3b741ae62dc..373a59a4fb6 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ /* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ /* 0x3555 = 13653 */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c index abffff5fa60..a8503ddb51f 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ /* This number is the maximum value representable in the alternative encoding. */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c index c339f197cd7..0e59234cfd4 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative -pedantic" } */ +/* { dg-options "-pedantic" } */ +/* { dg-add-options arm_fp16_alternative } */ /* This number overflows the range of the alternative encoding. Since this encoding doesn't have infinities, we should get a pedantic warning, diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c index deeb5cd5574..36e71c36d4e 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ /* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ /* This is the minimum normalized value. */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c index f9f565453e7..5a2eef7df2f 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-add-options arm_fp16_alternative } */ /* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ /* This is the minimum denormalized value. */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c b/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c index 27bb40dcfee..2ad03afbcd1 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c +++ b/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c @@ -3,8 +3,10 @@ __fp16 via float. */ /* { dg-do run } */ +/* { dg-require-effective-target arm_fp16_hw } */ /* { dg-require-effective-target arm_fp16_alternative_ok } */ -/* { dg-options "-mfp16-format=alternative" } */ +/* { dg-options "-std=c99" } */ +/* { dg-add-options arm_fp16_alternative } */ #include diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index b1faaf4aa95..6ce8557c9a9 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -5247,25 +5247,25 @@ proc add_options_for_aarch64_sve { flags } { # Return 1 if this is an ARM target supporting the FP16 alternative # format. Some multilibs may be incompatible with the options needed. Also -# set et_arm_neon_fp16_flags to the best options to add. +# set et_arm_fp16_alternative_flags to the best options to add. proc check_effective_target_arm_fp16_alternative_ok_nocache { } { if { [istarget *-*-vxworks7*] } { # Not supported by the target system. return 0 } - global et_arm_neon_fp16_flags - set et_arm_neon_fp16_flags "" + global et_arm_fp16_alternative_flags + set et_arm_fp16_alternative_flags "" if { [check_effective_target_arm32] } { foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16" "-mfpu=neon-fp16 -mfloat-abi=softfp"} { if { [check_no_compiler_messages_nocache \ arm_fp16_alternative_ok object { - #if !defined (__ARM_FP16_FORMAT_ALTERNATIVE) + #if !defined (__ARM_FP16_FORMAT_ALTERNATIVE) || ! (__ARM_FP & 2) #error __ARM_FP16_FORMAT_ALTERNATIVE not defined #endif } "$flags -mfp16-format=alternative"] } { - set et_arm_neon_fp16_flags "$flags -mfp16-format=alternative" + set et_arm_fp16_alternative_flags "$flags -mfp16-format=alternative" return 1 } } @@ -5404,11 +5404,11 @@ proc add_options_for_arm_fp16_ieee { flags } { # half-precision support. This is valid for ARM targets. proc add_options_for_arm_fp16_alternative { flags } { - if { ! [check_effective_target_arm_fp16_ok] } { + if { ! [check_effective_target_arm_fp16_alternative_ok] } { return "$flags" } - global et_arm_fp16_flags - return "$flags $et_arm_fp16_flags -mfp16-format=alternative" + global et_arm_fp16_alternative_flags + return "$flags $et_arm_fp16_alternative_flags" } # Return 1 if this is an ARM target that can support a VFP fp16 variant.