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bh=e9nIvUf2AnlJC0l02+sDQj/bT7XAsTM4acYEf/+pOEE=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=fUWa6PTJOZi5Rl6m9zJpv1xA5qmFRErMDErHizX/5gkOrL89ruTzvaLwBM1FOCF4U4zLjZoc+OldEPil0Uu3lXX6ZUyB++97AYpHqy1nMeKDhnGIkniUoQMUJbECTGYFmrUbUbotkvE0DIfhnA25lLcREwOwc4xSFybfsSRWagA= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp73t1706777008tr9av9hy X-QQ-Originating-IP: O4Sx3lLqWuecLxgSeEFSUYRhODANRbWxnKNkDPm7Ny8= Received: from server1.localdomain ( [58.60.1.8]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 01 Feb 2024 16:43:26 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: +ynUkgUhZJnUmNrZO7baHbZ2sLn3W1MXE+6J5tO39ifFf6TP9VdIBzqVczNg6 YYp4DFNy1ntI/f3xMPjDuBNvhGowpy6N1dUuG/2FIPilg4EGAgs2XImXRH66oYYb1qapl8l 8+y7aKvH9/5kilkJSufsNk4Lvf7YyICSPxv6FYeJyMxIsQcNomeuAjUycSv9rvn2LcJhStI z63JalhRQrTqOUjz2NM6mIJnz99weYr9A+kPBp3JVRZzSNbT41OLpglbbKcYOuPtc/vbZrO cOh4E4dJ63hXqi1Gwn/wWMslGgs04Tcl47qg1bFgw9vX8PC+dKkL0MFeb9khkmRCOb4lFLB VsDibosoG6rFK8sHNyhYlYfo1xzoNFkeLI/foitzKfkkTygOKrVgUt3q+d3T5wTOvgOZPS2 Db2Zsph2osg= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 4266870430224566103 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Disable the vsetvl fusion for conflict successors Date: Thu, 1 Feb 2024 16:43:24 +0800 Message-Id: <20240201084324.335561-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch fixes the following ineffective vsetvl insertion: #include "riscv_vector.h" void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2) { for (size_t i = 0; i < n; i++) { if (i == cond) { vint8mf8_t v = *(vint8mf8_t*)(in + i + 100); *(vint8mf8_t*)(out + i + 100) = v; } else if (i == cond2) { vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 200); *(vfloat32mf2_t*)(out + i + 200) = v; } else if (i == (cond2 - 1)) { vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300); *(vuint16mf2_t*)(out + i + 300) = v; } else { vint8mf4_t v = *(vint8mf4_t*)(in + i + 400); *(vint8mf4_t*)(out + i + 400) = v; } } } Before this patch: f: .LFB0: .cfi_startproc beq a2,zero,.L12 addi a7,a0,400 addi a6,a1,400 addi a0,a0,1600 addi a1,a1,1600 li a5,0 addi t6,a4,-1 vsetvli t3,zero,e8,mf8,ta,ma ---> ineffective uplift .L7: beq a3,a5,.L15 beq a4,a5,.L16 beq t6,a5,.L17 vsetvli t1,zero,e8,mf4,ta,ma vle8.v v1,0(a0) vse8.v v1,0(a1) vsetvli t3,zero,e8,mf8,ta,ma .L4: addi a5,a5,1 addi a7,a7,4 addi a6,a6,4 addi a0,a0,4 addi a1,a1,4 bne a2,a5,.L7 .L12: ret .L15: vle8.v v1,0(a7) vse8.v v1,0(a6) j .L4 .L17: vsetvli t1,zero,e8,mf4,ta,ma addi t5,a0,-400 addi t4,a1,-400 vle16.v v1,0(t5) vse16.v v1,0(t4) vsetvli t3,zero,e8,mf8,ta,ma j .L4 .L16: addi t5,a0,-800 addi t4,a1,-800 vle32.v v1,0(t5) vse32.v v1,0(t4) j .L4 It's obvious that we are hoisting the e8mf8 vsetvl to the top. It's ineffective since e8mf8 comes from low probability block which is if (i == cond). For this case, we disable such fusion. After this patch: f: beq a2,zero,.L12 addi a7,a0,400 addi a6,a1,400 addi a0,a0,1600 addi a1,a1,1600 li a5,0 addi t6,a4,-1 .L7: beq a3,a5,.L15 beq a4,a5,.L16 beq t6,a5,.L17 vsetvli t1,zero,e8,mf4,ta,ma vle8.v v1,0(a0) vse8.v v1,0(a1) .L4: addi a5,a5,1 addi a7,a7,4 addi a6,a6,4 addi a0,a0,4 addi a1,a1,4 bne a2,a5,.L7 .L12: ret .L15: vsetvli t3,zero,e8,mf8,ta,ma vle8.v v1,0(a7) vse8.v v1,0(a6) j .L4 .L17: addi t5,a0,-400 addi t4,a1,-400 vsetvli t1,zero,e8,mf4,ta,ma vle16.v v1,0(t5) vse16.v v1,0(t4) j .L4 .L16: addi t5,a0,-800 addi t4,a1,-800 vsetvli t3,zero,e32,mf2,ta,ma vle32.v v1,0(t5) vse32.v v1,0(t4) j .L4 Tested on both RV32/RV64 no regression. Ok for trunk ? PR target/113696 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Suppress vsetvl fusion. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr113696.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 14 ++++++++++ .../gcc.target/riscv/rvv/vsetvl/pr113696.c | 26 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index cec862329c5..79fc2ec2401 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -2959,6 +2959,20 @@ pre_vsetvl::earliest_fuse_vsetvl_info (int iter) src_block_info.set_empty_info (); src_block_info.probability = profile_probability::uninitialized (); + /* See PR113696, we should reset immediate dominator to + empty since we may uplift ineffective vsetvl which + locate at low probability block. */ + basic_block dom + = get_immediate_dominator (CDI_DOMINATORS, eg->src); + auto &dom_block_info = get_block_info (dom); + if (dom_block_info.has_info () + && !m_dem.compatible_p ( + dom_block_info.get_exit_info (), curr_info)) + { + dom_block_info.set_empty_info (); + dom_block_info.probability + = profile_probability::uninitialized (); + } changed = true; } /* Choose the one with higher probability. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c new file mode 100644 index 00000000000..5d7c5f52ead --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2) +{ + for (size_t i = 0; i < n; i++) + { + if (i == cond) { + vint8mf8_t v = *(vint8mf8_t*)(in + i + 100); + *(vint8mf8_t*)(out + i + 100) = v; + } else if (i == cond2) { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 200); + *(vfloat32mf2_t*)(out + i + 200) = v; + } else if (i == (cond2 - 1)) { + vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300); + *(vuint16mf2_t*)(out + i + 300) = v; + } else { + vint8mf4_t v = *(vint8mf4_t*)(in + i + 400); + *(vint8mf4_t*)(out + i + 400) = v; + } + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */