From patchwork Mon Jan 22 02:49:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juzhe-Zhong X-Patchwork-Id: 1888972 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TJF751lfYz1yPv for ; Mon, 22 Jan 2024 13:49:35 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 413F83858409 for ; Mon, 22 Jan 2024 02:49:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 1C5223858D3C for ; Mon, 22 Jan 2024 02:49:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1C5223858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1C5223858D3C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.243.244.52 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705891756; cv=none; b=iVLKRwtljR3IWLKfCseQIoFqXUOsgbkSouwXej/03kFafYfYbihAgUkML8d+vv0bj1lXmkLLoS0LMSs66eyFavAuv4DUUNeO/ZDQRDsvHkPkpRZ2pNG0Gyx9zlv5dHiD51um+9QpO3SVHof4emvNRxw9Dgkeao61j+kNBhGI1gU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705891756; c=relaxed/simple; bh=s3EkPNNSemoLd6MMqmvM5oIPdz0sw2/Lb9ns4cigmFs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=sbLhc4NR/f+tztNm7fx1O3+sjWkRSG2ylrd8biSN8+VU5SwHC/cqfLT6gGQmSJZe9WwvLeBh79EnrbW8k8TGP/N76+42vOeJj/+VNLlkjB4jJV8TzewRIENKcfyCINMYl8o30l+M6Y4wFO8Zea6EMBnPI/XeP56GHUd4d5NPCe4= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp62t1705891747t9uj4gep X-QQ-Originating-IP: 2oTNc/Fwwc8JornYgQN6P6fPW3eJPtH++FTRfQF+DDE= Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 22 Jan 2024 10:49:06 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: swyrzWPvyR3S7V1dW2+JI7pMplOlpi5/4u51m3VZSW6bLHk8icAWGllmOldRC J25fLq3I+uYH63rLa1DOjnOUpi23WUQ/B24Wk0o6Sk9FWxqi1BWunJyGDAqZZcCuqrfNDQn RS4T+pGKEb4+Z5CdAgR4L6wyZOGDE0hZW13yPGqsH7TYtAmIIQwSbVidoiWA118zRdBX0o1 3kfliMZaNsU6/paz/UzxcQB7IHIHSzYt9HqdyU2F4n2n6fzIPGV/qR9+LuwYZnx3xqzYS0Q AwnSqXrP/w/N+Ki/zKlV1S5ORliqokAVtLDUuxFe8xIBJI+yls0TB7y4uJQWnC3+CeCIOyZ 6WiCha9bMoCVdQtgmjS4TpGbo8fRzYw0Oa78Kd64LHaaCxBv74= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 14880611150535284262 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix vfirst/vmsbf/vmsif/vmsof ratio attributes Date: Mon, 22 Jan 2024 10:49:05 +0800 Message-Id: <20240122024905.1543475-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org vfirst/vmsbf/vmsif/vmsof instructions are supposed to demand ratio instead of demanding sew_lmul. But my previous typo makes VSETVL PASS miss honor the risc-v v spec. Consider this following simple case: int foo4 (void * in, void * out) { vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); v = __riscv_vadd_vv_i32m1 (v, v, 4); vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32(v); mask = __riscv_vmsof_m_b32(mask, 4); return __riscv_vfirst_m_b32(mask, 4); } Before this patch: foo4: vsetivli zero,4,e32,m1,ta,ma vle32.v v1,0(a0) vadd.vv v1,v1,v1 vsetvli zero,zero,e8,mf4,ta,ma ----> redundant. vmsof.m v2,v1 vfirst.m a0,v2 ret After this patch: foo4: vsetivli zero,4,e32,m1,ta,ma vle32.v v1,0(a0) vadd.vv v1,v1,v1 vmsof.m v2,v1 vfirst.m a0,v2 ret Confirm RVV spec and Clang, this patch makes VSETVL PASS match the correct behavior. Tested on both RV32/RV64, no regression. gcc/ChangeLog: * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/attribute-1.c: New test. --- gcc/config/riscv/vector.md | 2 +- .../gcc.target/riscv/rvv/vsetvl/attribute-1.c | 47 +++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index cfc54ae5eac..307d9a8c952 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -433,7 +433,7 @@ vialu,vshift,vicmp,vimul,vidiv,vsalu,\ vext,viwalu,viwmul,vicalu,vnshift,\ vimuladd,vimerge,vaalu,vsmul,vsshift,\ - vnclip,viminmax,viwmuladd,vmffs,vmsfs,\ + vnclip,viminmax,viwmuladd,\ vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\ vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\ vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c new file mode 100644 index 00000000000..28dcf986bac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +int +foo (void *in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + v = __riscv_vadd_vv_i32m1 (v, v, 4); + vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v); + return __riscv_vfirst_m_b32 (mask, 4); +} + +int +foo2 (void *in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + v = __riscv_vadd_vv_i32m1 (v, v, 4); + vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v); + mask = __riscv_vmsbf_m_b32 (mask, 4); + return __riscv_vfirst_m_b32 (mask, 4); +} + +int +foo3 (void *in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + v = __riscv_vadd_vv_i32m1 (v, v, 4); + vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v); + mask = __riscv_vmsif_m_b32 (mask, 4); + return __riscv_vfirst_m_b32 (mask, 4); +} + +int +foo4 (void *in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + v = __riscv_vadd_vv_i32m1 (v, v, 4); + vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v); + mask = __riscv_vmsof_m_b32 (mask, 4); + return __riscv_vfirst_m_b32 (mask, 4); +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 4 } } */ +/* { dg-final { scan-assembler-times {vsetivli} 4 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */