From patchwork Thu Dec 7 15:41:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 1873270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com header.b=siG5d0tM; dkim=pass (1024-bit key) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com header.b=siG5d0tM; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SmJRj4hn5z23nW for ; Fri, 8 Dec 2023 02:42:09 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A9A95385DC07 for ; Thu, 7 Dec 2023 15:42:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-he1eur01on2059.outbound.protection.outlook.com [40.107.13.59]) by sourceware.org (Postfix) with ESMTPS id 09D5F385AC2C for ; Thu, 7 Dec 2023 15:41:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 09D5F385AC2C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 09D5F385AC2C Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.13.59 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1701963687; cv=pass; b=g8sZ3JNnqvHDHWQO67YzPIz7j/pJjy+XUrQV4OLZpHMZwQ+P10dVFyjRzoLwTU6z9rHlsHMfyOh7RcnJ+6EwngUNVg/unlv4UIjh8M/5+Z0ONaYmJ202o4uz1ZDuuC0IWMpbuD8FISepsq9hBRbxauKkVnjhJBg7PU8zYvqsIm4= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1701963687; c=relaxed/simple; bh=CdW++5JjeCoyQFX5Sk1u83cllkcsdAnUScCh9MTf3Ic=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=n4MhEV/ZA0ykM/6WcONYQ9EcdNDherGSjKkeBcnDQB/g33VnHIuWO6bW1c1IXpVExRqm/9n9+w4QjK3pUFGZ/f/Yr9Y6935MMpM+VU8BlWqZ9BC3nExKGJXJEL2H+O3hhPyHcUXoO6lNQ1Zh6SU88Jd9/T6vwS1eHL7fC806VIM= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=QH347m/fqSqaWzER5d9uhxzCgM+QLTXA8EnYOY/rC2u0cgWcgAJT55J9HwHDVUTU3DZnIEYkw6sijfKox0ebmURCXEIHPkgwA8JVkYe1cg7AKnTNWrPAXcWwyBc2t1/xEd6duWGplq8Ifk40XS1XDMDXPGotkIp8oLl88hcdeNlUWMnDMnOp6IDL4Ydc1eLlerR7rsVzIyK6U6oUusABWSl08LXB6v8n/ojnaVnJbW1V+Av7tzv6e55e7IsunGhArzc1sATg9QIGbmC86iv8Xy9SuhOl4cGTda0hZYddCQMIBZ3FwodjBT9ZGeY3p576oKWpYtlBylZ6fFRUPTM/dg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=th0mcBSG0+LRGdQB27sEtza59VR2ZHEq0t+MaCf8K/c=; b=XTD1AvQpuaf7j4oQCOeX1YP+Lv9FH0Vk/LMNX3tHQoGzsLaT10WGTmSnwVKGs/Rcoa3+TS+0t8wtaah0R1Fa0kSbFPeXCnG9mX1MUutKLjvXh43VDmGygFvk38oTLpZeeEX3ak1/fLr1C77gyTA2Lp26GdJo3tLTJcUkL9o4mHvV/FV8JC7soGkXt2HDrPziTAych3+Xtecut+UQtfMWVgr7gGJFiIGbuFeVocmrig0u8aHACrYJIjWWkfNBz4PmaphTSdgXCF09Zc7eiHRvp6hYiuAhlr0q0cO5AAAG3jd6XW9rFdb+GBkcXsXz6H7DRCJ11KKSqWytdYzn8jxu/A== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=th0mcBSG0+LRGdQB27sEtza59VR2ZHEq0t+MaCf8K/c=; b=siG5d0tMiUHSJOHJu2SC/OvAOoZyCOmqfVpL0eDhPKTg6gIpnKFiybVGRxYjbKJ/RAUBNHfy+UOAmPXZZJA75yros2odoSu2l2inDLV5+FLgNorf8Ry+VoaxWkIrrUDDCbVn9rKcnpZH9tRRpT/M8E+vUKkaU59MaJyFaWa/0ng= Received: from DB8PR09CA0022.eurprd09.prod.outlook.com (2603:10a6:10:a0::35) by AM9PR08MB6642.eurprd08.prod.outlook.com (2603:10a6:20b:2ff::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.27; Thu, 7 Dec 2023 15:41:19 +0000 Received: from DU2PEPF0001E9C0.eurprd03.prod.outlook.com (2603:10a6:10:a0:cafe::32) by DB8PR09CA0022.outlook.office365.com (2603:10a6:10:a0::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.34 via Frontend Transport; Thu, 7 Dec 2023 15:41:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DU2PEPF0001E9C0.mail.protection.outlook.com (10.167.8.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.23 via Frontend Transport; Thu, 7 Dec 2023 15:41:19 +0000 Received: ("Tessian outbound 7671e7ddc218:v228"); Thu, 07 Dec 2023 15:41:19 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: e77afff27c54bcb6 X-CR-MTA-TID: 64aa7808 Received: from c62ed8b20d77.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id E9FF45A0-F02A-4578-B633-F1015FA8EC98.1; Thu, 07 Dec 2023 15:41:12 +0000 Received: from EUR05-DB8-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id c62ed8b20d77.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 07 Dec 2023 15:41:12 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=c7xvzd9Ks9kRPo9v6g+x4rwHGsrxgt8HqQEE/QCYpFTqK2+ddGEDoyxLe+ZreW3QZ6ytVNBRbFiVGBVQBBqROx1cB+tG709lQxNZ06xgJxHsnyFBrcfXJ5txt4pXzg39R2PBUOLCEg5VfscfKLsGpPDOJlrxe3KkWLMsOpw3pjwOiX+XScparjZhw/xGkoufX3VG40SmJrBHFQ2i6JHg+lKuJMuw9iI3Gx72KjTHcORuudG6QdCcoa2uRPfFEhqmt2apgHRWpSoEzyZtgqir1jnBHc5u5Kbljim7EKI055TV2ZuziXQyatPWiMFVugopRuzf0PWwq75dhmd27br1iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=th0mcBSG0+LRGdQB27sEtza59VR2ZHEq0t+MaCf8K/c=; b=eZFwe09eIFkXtAfszn3eC4apoH5gll4ZefPWn5zwWbMBBZ9twaRNJki3QIOclvCCeBL5Gdc7R0+VUlo0kLNzVHrGkTVYUgmt8d9H7R62ch4zX9ccBxecH9Z5XpFHDFczgKGVqwRCh4bge1AlNPRITFZqgftVu3zai9eSvZrR4asZsVt/1lCM6uFNUF+bqIZN7R0CT3tuGAqvJ/fPZCp9zbyicWKtd7aLz2oiklnz9x3roXwa+bLjem3b+dwfck/tE9v94YDBfMeSk6SAx1i0rxSAw8g/s5u2wMPbuNPZqaYRiwWoPnO/7RZz3WH0l31GNnUIdLXD4isx+gq9rixHbA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=th0mcBSG0+LRGdQB27sEtza59VR2ZHEq0t+MaCf8K/c=; b=siG5d0tMiUHSJOHJu2SC/OvAOoZyCOmqfVpL0eDhPKTg6gIpnKFiybVGRxYjbKJ/RAUBNHfy+UOAmPXZZJA75yros2odoSu2l2inDLV5+FLgNorf8Ry+VoaxWkIrrUDDCbVn9rKcnpZH9tRRpT/M8E+vUKkaU59MaJyFaWa/0ng= Received: from AM0PR01CA0082.eurprd01.prod.exchangelabs.com (2603:10a6:208:10e::23) by GV1PR08MB7681.eurprd08.prod.outlook.com (2603:10a6:150:60::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.27; Thu, 7 Dec 2023 15:41:08 +0000 Received: from AMS0EPF000001B1.eurprd05.prod.outlook.com (2603:10a6:208:10e:cafe::89) by AM0PR01CA0082.outlook.office365.com (2603:10a6:208:10e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.34 via Frontend Transport; Thu, 7 Dec 2023 15:41:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AMS0EPF000001B1.mail.protection.outlook.com (10.167.16.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7068.20 via Frontend Transport; Thu, 7 Dec 2023 15:41:08 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Thu, 7 Dec 2023 15:41:07 +0000 Received: from e127754.cambridge.arm.com (10.1.34.67) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Thu, 7 Dec 2023 15:41:07 +0000 From: To: CC: Subject: [PATCH v2 1/3] [GCC] arm: vld1_types_x2 ACLE intrinsics Date: Thu, 7 Dec 2023 15:41:04 +0000 Message-ID: <20231207154106.4808-2-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20231207154106.4808-1-Ezra.Sitorus@arm.com> References: <20231207154106.4808-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001B1:EE_|GV1PR08MB7681:EE_|DU2PEPF0001E9C0:EE_|AM9PR08MB6642:EE_ X-MS-Office365-Filtering-Correlation-Id: 0bb4b71a-e121-4974-f240-08dbf73af528 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: KU74d8U34XF4xMXXGOgJt/8wmxxa175PAggUJM5sHnHANN+L7u9awMO2K3LWIAwpgnzeeUwHhtlhzEiYh9uZ/a+cXHWAO/QskY4qVUNR2nk2+75n+4M7Rj93HY9od1zjqzyfQ3i+7oDLOLsa4k/CDXN2KHGQxydCGyUP5wS+EN9XmsLATM2iGRPyzD16bQFw/FT/tTgXu4Qk50VxIzJa4URrjpyIL8acTUTX0oVlQXnHoE0y+KeyR9TTNlPvR6oDgEola0HxVeZ8A1lIuBRu578tQGx0Lj+p7jnzZ5Djtqc1NPN7odPtKdWgwAyGZzLAPosVW7zcbRAlLvtMJ/TBIPGvpi/j9hDjwdSsBL3ZMipk1J0em2P0bdmwOTesWZ125DTwB3ZQ5pKhwY8ODmd/4clUjFSRCaHOsZmMSY5wJKhlwKGDq/ppfXnQ4FVjdItetU+mAg/Ldj7TQUasawvFHiXMZErNEl7lafnP96QFySzs5ZWpoviGT7504iolOEuScT/8+xGW1JVDE4piLlvG8zqwddSnK5bske3LTokTW7K2+SdEKoXHDL3u62jLvgPSVtbFowJIUKec7ktGlhJM4PLcVp/2eSd9y+WS5Q8AIkP+GLeDErxv1BnZVCD9bdIwgUz9H4xQNPWU/n5HHZdNj2FhIAZ/EKH3QbvDt26iFedevngjuzR/TW3pfp2BAFxnC0ONAYcnkog5qMgDeZBTFF4wSraP8nAZ0ujYsHtXp8tNLWU7s7ECYOQJpMayIdokWiWWPXIkICod3JnsFSoXHTilYyf9j/UpMwwP7//kNcg= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(376002)(396003)(346002)(136003)(230922051799003)(82310400011)(451199024)(186009)(1800799012)(64100799003)(40470700004)(46966006)(36840700001)(84970400001)(40480700001)(1076003)(426003)(336012)(6666004)(26005)(2616005)(40460700003)(81166007)(86362001)(82740400003)(36756003)(356005)(47076005)(83380400001)(5660300002)(7696005)(36860700001)(30864003)(70206006)(70586007)(966005)(316002)(8676002)(6916009)(2876002)(2906002)(41300700001)(8936002)(478600001)(4326008)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB7681 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DU2PEPF0001E9C0.eurprd03.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 65268a54-27f4-4b38-b6e6-08dbf73aee91 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: c5d7uby6IWBjqIo6eq4yBKw5u2mTDvUwhVXqAVgYRtuYhpYKDOUdM6j8Y34IL0VGH98/sv9TCAE/klleWQSCemIFkW7V7D9iFseWqc14lf5eLiz36Mv5EUgEHbFn5DsGy55z8L266qphqyBkjQgS9UStadStcisiDk+1lYiiHT/7HpMeBEDZ8q6MlOHaA3tlJRnlWL+a5nMfAon5mVyqKlf2P341pZqPGrD6in1EaoG6gz4sB2Nrmavyy/yPwfT0IecbrvYXLGl4g5uvbZvz4Q4xSRGNw22kuZnCXXYdg7Iwkmq8HAPaeEksMZJ3PXZXu4CyrY2D+S8y8BNC0ArJUEUEEYwAr+Pz+OVkA4ITB2dtz7nd7kg62HbEV+NuIbUcfyP4XRKmyy4U93tUpquZJ8nH3HL4HsHJCXAczl4M7HSMo+SftTYOIig74gHSJf2pv10JvsYtz7RNyH+lGnTPEClvoef1W0b2/sotVQdvECLQntDppn3m6givzgnp/2ev82EN3VvAMx2xj+lNeL0zKIuD03tZTd/cPS27sONWi2nNB9jVvPBa22/CSCD8SMaXWyvqdZ1JU9cJLtfk7oOtJhSmUQ43Mt/YCf3uxYzsrJguBd80iGqqoJ5JaXN0VPOlUGjSGd00eOHVxuITIu/VRNtrBF5WmoQ+uQVlO0FU79gUwydaJOMDor/0bYXAQUUZrqZCLNdeCPvtel975xZylgei30zO9GpZ6BxcCmhDoSdlmHF80Wam1WcqKuX88uV6n+ncSL0OgwMjo70WflmoAg== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(376002)(39860400002)(346002)(396003)(136003)(230922051799003)(82310400011)(186009)(1800799012)(64100799003)(451199024)(46966006)(40470700004)(36840700001)(2876002)(2906002)(30864003)(40480700001)(84970400001)(40460700003)(5660300002)(36860700001)(6666004)(4326008)(478600001)(8676002)(36756003)(81166007)(966005)(8936002)(82740400003)(6916009)(83380400001)(336012)(26005)(2616005)(7696005)(41300700001)(426003)(70586007)(86362001)(70206006)(316002)(47076005)(1076003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 15:41:19.6322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bb4b71a-e121-4974-f240-08dbf73af528 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C0.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6642 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vld1 intrinsic for the arm port. This patch adds the _x2 variants of the vld1 intrinsic. The previous vld1_x2 has been updated to vld1q_x2 to take into account that it works with 4-word-length types. vld1_x2 is now only for 2-word-length types. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New. (vld1_f16_x2, vld1_f32_x2): New. (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New. (vld1_bf16_x2): New. (vld1q_types_x2): Updated to use vld1q_x2 from arm_neon_builtins.def * config/arm/arm_neon_builtins.def (vld1_x2): Updated entries. (vld1q_x2): New entries, but comes from the old vld1_x2 * config/arm/neon.md (neon_vld1_x2): Updated from neon_vld1_x2. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 156 ++++++++++++++++-- gcc/config/arm/arm_neon_builtins.def | 3 +- gcc/config/arm/neon.md | 10 +- .../gcc.target/arm/simd/vld1_base_xN_1.c | 66 ++++++++ .../gcc.target/arm/simd/vld1_bf16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vld1_fp16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vld1_p64_xN_1.c | 13 ++ 7 files changed, 254 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index af1f747f262..669b8fffb40 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -10307,6 +10307,15 @@ vld1_p64 (const poly64_t * __a) return (poly64x1_t) { *__a }; } +__extension__ extern __inline poly64x1x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p64_x2 (const poly64_t * __a) +{ + union { poly64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #pragma GCC pop_options __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10336,6 +10345,42 @@ vld1_s64 (const int64_t * __a) return (int64x1_t) { *__a }; } +__extension__ extern __inline int8x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s8_x2 (const int8_t * __a) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s16_x2 (const int16_t * __a) +{ + union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int32x2x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s32_x2 (const int32_t * __a) +{ + union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline int64x1x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s64_x2 (const int64_t * __a) +{ + union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) __extension__ extern __inline float16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10352,6 +10397,26 @@ vld1_f32 (const float32_t * __a) return (float32x2_t)__builtin_neon_vld1v2sf ((const __builtin_neon_sf *) __a); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline float16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f16_x2 (const float16_t * __a) +{ + union { float16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4hf (__a); + return __rv.__i; +} +#endif + +__extension__ extern __inline float32x2x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f32_x2 (const float32_t * __a) +{ + union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v2sf ((const __builtin_neon_sf *) __a); + return __rv.__i; +} + __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_u8 (const uint8_t * __a) @@ -10380,6 +10445,42 @@ vld1_u64 (const uint64_t * __a) return (uint64x1_t) { *__a }; } +__extension__ extern __inline uint8x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u8_x2 (const uint8_t * __a) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u16_x2 (const uint16_t * __a) +{ + union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint32x2x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u32_x2 (const uint32_t * __a) +{ + union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint64x1x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u64_x2 (const uint64_t * __a) +{ + union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + __extension__ extern __inline poly8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_p8 (const poly8_t * __a) @@ -10394,6 +10495,24 @@ vld1_p16 (const poly16_t * __a) return (poly16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a); } +__extension__ extern __inline poly8x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p8_x2 (const poly8_t * __a) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline poly16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p16_x2 (const poly16_t * __a) +{ + union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + #pragma GCC push_options #pragma GCC target ("fpu=crypto-neon-fp-armv8") __extension__ extern __inline poly64x2_t @@ -10408,7 +10527,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p64_x2 (const poly64_t * __a) { union { poly64x2x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10464,7 +10583,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s8_x2 (const int8_t * __a) { union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10473,7 +10592,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s16_x2 (const int16_t * __a) { union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10482,7 +10601,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s32_x2 (const int32_t * __a) { union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x2v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10491,7 +10610,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s64_x2 (const int64_t * __a) { union { int64x2x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10589,7 +10708,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f16_x2 (const float16_t * __a) { union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8hf (__a); + __rv.__o = __builtin_neon_vld1q_x2v8hf (__a); return __rv.__i; } #endif @@ -10599,7 +10718,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f32_x2 (const float32_t * __a) { union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v4sf ((const __builtin_neon_sf *) __a); + __rv.__o = __builtin_neon_vld1q_x2v4sf ((const __builtin_neon_sf *) __a); return __rv.__i; } @@ -10676,7 +10795,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u8_x2 (const uint8_t * __a) { union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10685,7 +10804,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u16_x2 (const uint16_t * __a) { union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10694,7 +10813,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u32_x2 (const uint32_t * __a) { union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x2v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10703,7 +10822,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u64_x2 (const uint64_t * __a) { union { uint64x2x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10798,7 +10917,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p8_x2 (const poly8_t * __a) { union { poly8x16x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10807,7 +10926,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p16_x2 (const poly16_t * __a) { union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -20816,6 +20935,15 @@ vld1_bf16 (bfloat16_t const * __ptr) return __builtin_neon_vld1v4bf (__ptr); } +__extension__ extern __inline bfloat16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_bf16_x2 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4bf ((const __builtin_neon_bf *) __ptr); + return __rv.__i; +} + __extension__ extern __inline bfloat16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16 (const bfloat16_t * __ptr) @@ -20828,7 +20956,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16_x2 (const bfloat16_t * __ptr) { union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8bf ((const __builtin_neon_bf *) __ptr); + __rv.__o = __builtin_neon_vld1q_x2v8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 55e09722748..07750c03c08 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -301,7 +301,8 @@ VAR1 (TERNOP, vtbx4, v8qi) VAR13 (LOAD1, vld1, v8qi, v4hi, v4hf, v2si, v2sf, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) -VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) +VAR7 (LOAD1, vld1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (LOAD1, vld1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR12 (LOAD1LANE, vld1_lane, diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index e069ceb651c..75add42777d 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -4957,11 +4957,11 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_load1_1reg")] ) -(define_insn "neon_vld1_x2" - [(set (match_operand:OI 0 "s_register_operand" "=w") - (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") - (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - UNSPEC_VLD1))] +(define_insn "neon_vld1_x2" + [(set (match_operand:VMEMX2 0 "s_register_operand" "=w") + (unspec:VMEMX2 [(match_operand:VMEMX2 1 "neon_struct_operand" "Um") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD1))] "TARGET_NEON" "vld1.\t%h0, %A1" [(set_attr "type" "neon_load1_2reg")] diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c new file mode 100644 index 00000000000..6b0e78d94d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c @@ -0,0 +1,66 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +uint8x8x2_t test_vld1_u8_x2 (uint8_t * a) +{ + return vld1_u8_x2 (a); +} + +uint16x4x2_t test_vld1_u16_x2 (uint16_t * a) +{ + return vld1_u16_x2 (a); +} + +uint32x2x2_t test_vld1_u32_x2 (uint32_t * a) +{ + return vld1_u32_x2 (a); +} + +uint64x1x2_t test_vld1_u64_x2 (uint64_t * a) +{ + return vld1_u64_x2 (a); +} + +int8x8x2_t test_vld1_s8_x2 (int8_t * a) +{ + return vld1_s8_x2 (a); +} + +int16x4x2_t test_vld1_s16_x2 (int16_t * a) +{ + return vld1_s16_x2 (a); +} + +int32x2x2_t test_vld1_s32_x2 (int32_t * a) +{ + return vld1_s32_x2 (a); +} + +int64x1x2_t test_vld1_s64_x2 (int64_t * a) +{ + return vld1_s64_x2 (a); +} + +float32x2x2_t test_vld1_f32_x2 (float32_t * a) +{ + return vld1_f32_x2 (a); +} + +poly8x8x2_t test_vld1_p8_x2 (poly8_t * a) +{ + return vld1_p8_x2 (a); +} + +poly16x4x2_t test_vld1_p16_x2 (poly16_t * a) +{ + return vld1_p16_x2 (a); +} + +/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c new file mode 100644 index 00000000000..3ec7a5e1986 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ + +#include "arm_neon.h" + +bfloat16x4x2_t test_vld1_bf16_x2 (bfloat16_t * a) +{ + return vld1_bf16_x2 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c new file mode 100644 index 00000000000..c0e5ea49142 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +float16x4x2_t test_vld1_f16_x2 (float16_t * a) +{ + return vld1_f16_x2 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c new file mode 100644 index 00000000000..3ccea520ddc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +poly64x1x2_t test_vld1_p64_x2 (poly64_t * a) +{ + return vld1_p64_x2 (a); +} + +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ From patchwork Thu Dec 7 15:41:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 1873269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com header.b=yStPon+2; dkim=pass (1024-bit key) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com header.b=yStPon+2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SmJRF1WBzz23yf for ; Fri, 8 Dec 2023 02:41:45 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 349C738618AD for ; Thu, 7 Dec 2023 15:41:43 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2050.outbound.protection.outlook.com [40.107.20.50]) by sourceware.org (Postfix) with ESMTPS id E1F71385AC12 for ; Thu, 7 Dec 2023 15:41:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E1F71385AC12 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E1F71385AC12 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.20.50 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1701963686; cv=pass; b=hAWtvbYCP7milRupRx6ZqOT5A2vizby3IA0T7VWgeNTfwir2vjwP7eVCC6M/ukfoghrrjzhM7ZAduWTNnLwUawOMntjn1LjARH4ORZvKuimCv7k/9J4h3uSiLJCAtrP1skRX26rE0VeFxQWu3eXAgeZhXW+ETLDPtALW+O8QR/4= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1701963686; c=relaxed/simple; bh=tTPxj8MUm3V34M8CQfkFaLY2ZkBaHhkQtGf6omii85c=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=U6Tu4Jq453M+h1Q3RGDQdGaHJ2x1pY2EY9D81yfuC4o7zWW6VrweCfSL/sjjZZCt2V8ebeBj7FjLusPw7g9yDY2NVf974G46qmLJvLhW7nd7WuG4LG1sMy0s7lZHrnbpLysifNrlonWOW2O0uUeMFZcL/3zRV34NtWnw1fCFvxM= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=YlJki8gee2Z1YHtYjAJxk6qElin+sZfN8POFsAu11FGaRUd4h/g9cXdfY4CrGc9HGbMvlB4Xdu21WsN0aTIcv1ewdHExOCqx7hqakeySMqD8BDWDprjW1KV1eK3eFx0a9ss6d7mBrs2NvWRDbJ275gVw+7Xxc1YIprv/0UIqy+p5DSmzVPSFPXXF89T1IEIWMzhO3DujlI6zWUEmvaTaxQj28w+BBkqtY2pB0a6j5E8VuWcfR4qpH3Z7rX+y91vKiTS8HO902Rwc0HqQhFMBoHsImewSN6j1hi2icEUIoXhOTaJYdkf5mSgXMP3jkLUA6JGhvpZsIjivXEK+lhBwTw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VeMOo49J0hxPyTnq9c8HzhfdZYI1cKvnVHlFj3BU334=; b=OOjBAX3mu/XUknKreLuHbHi5W0VNt0ZjhO1wr7EEmD0XK4QL/sDeZUGD87nPbobgL+8CVVCgS1iUPBeV9xpAwzmJyf6X19jeFQ3i3E9bsrR77LfrJQ2BCMERLS4eaZI0ZjeH3gLc7s1puLjecgIyRyi9SFufcrSNLEQrhWGoBgf+uOoD6MMmDuCAxM3CK+/scSXAtmRjiB1RMo8VfYcF8VEoXGYGG6pWOd9uLtMSPQifAVu9AL053VAYMBbu4SjQwc0gnKriAb22aJKvxaNnzSYv12f44oGDtyfIEM1wA5VEThRDOpHKH+rwnRX9jLjPlwv2KlUjXED0IqAwfF+ZGA== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VeMOo49J0hxPyTnq9c8HzhfdZYI1cKvnVHlFj3BU334=; b=yStPon+2An7JrakXr8jZcESslloE7wk9DW7BI7n3idkc3YwrFXdv1/8rXJ0KEtk41moVM3bRlXGu4SScAy81wQKOHfFTo9yTxj7z/QVEEh20BbpzmRmZwl3a8rCxSy68SYzLRLXf5hlvlUAcmnqzpLRl+/43THazEZIb5/2AX1k= Received: from DU2PR04CA0304.eurprd04.prod.outlook.com (2603:10a6:10:2b5::9) by DU0PR08MB7738.eurprd08.prod.outlook.com (2603:10a6:10:3be::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.25; Thu, 7 Dec 2023 15:41:20 +0000 Received: from DB5PEPF00014B96.eurprd02.prod.outlook.com (2603:10a6:10:2b5:cafe::fa) by DU2PR04CA0304.outlook.office365.com (2603:10a6:10:2b5::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.34 via Frontend Transport; Thu, 7 Dec 2023 15:41:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5PEPF00014B96.mail.protection.outlook.com (10.167.8.234) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.20 via Frontend Transport; Thu, 7 Dec 2023 15:41:20 +0000 Received: ("Tessian outbound 5d213238733f:v228"); Thu, 07 Dec 2023 15:41:19 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: e8b47c3edc859f1d X-CR-MTA-TID: 64aa7808 Received: from 06908445bd28.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 51D2E2B7-4119-4305-8412-E7B4C0EE23AC.1; Thu, 07 Dec 2023 15:41:13 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 06908445bd28.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 07 Dec 2023 15:41:13 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aho/gEBvMR982x8rD8NKgxeM4OxY5Tedw6/Xq+b00IBHi3LZqaqmkAViX8OqQMenZHYtS+ty2Ot+oV9EQF7f+/AL/XywV0RxpL6lM6mD1+ezo0fwMH99gNQdP7cm4/LMF5WaSN4DypQttSAS2cKnR4UXAGpr++lLAbpwLwbkYleb5wUXbcg3qyUaIVFRn7KRmsiD0ZwdPRFyxmBbGNuNY4askhCUMV99MxIvPiEQYBszn3Ias7YXbgkY27cf/QI5tzA/LM6RC3i729DvzYJDol+uYy3tEE6cEtsKFgzBO/7ejQPqCXNLCV6+RqqvvUVk1/rZyc/qX4O5wr35U3y4XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VeMOo49J0hxPyTnq9c8HzhfdZYI1cKvnVHlFj3BU334=; b=A8TVg+o30Q5BhtAVKCu9kIkRzBCDFSfM/SCCxdP2t+1POuo5Oo2hirm3m9SmFkztuvuHDDE4SjlUjF4QUzbE2IvDNQnOR2uEUs7vLCxj3LuHovirgysqVkH0r9g1qFJyMmLKBu31aJ7ZCISAw0jEEYXOnNjim7z719XN4IIw7UdWEUHuaLa8zE6xYkfMIATAKTlDxnzI1KR3x1kS2WNP+Nq4Xwv+VGMdcArryMh/1+zYh+YaIMeelp8ypQI5u48ytBpuhqkbw0s9RRSk+OMhouisNenW0+ntl3obx9QasY9uWphQ5M7UyqUu7ho2T03ABj4b3lkc3PzNTnjF+siCNA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VeMOo49J0hxPyTnq9c8HzhfdZYI1cKvnVHlFj3BU334=; b=yStPon+2An7JrakXr8jZcESslloE7wk9DW7BI7n3idkc3YwrFXdv1/8rXJ0KEtk41moVM3bRlXGu4SScAy81wQKOHfFTo9yTxj7z/QVEEh20BbpzmRmZwl3a8rCxSy68SYzLRLXf5hlvlUAcmnqzpLRl+/43THazEZIb5/2AX1k= Received: from AS8PR04CA0172.eurprd04.prod.outlook.com (2603:10a6:20b:331::27) by DU0PR08MB9822.eurprd08.prod.outlook.com (2603:10a6:10:445::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.25; Thu, 7 Dec 2023 15:41:09 +0000 Received: from AMS0EPF000001B4.eurprd05.prod.outlook.com (2603:10a6:20b:331:cafe::40) by AS8PR04CA0172.outlook.office365.com (2603:10a6:20b:331::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.34 via Frontend Transport; Thu, 7 Dec 2023 15:41:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AMS0EPF000001B4.mail.protection.outlook.com (10.167.16.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7068.20 via Frontend Transport; Thu, 7 Dec 2023 15:41:08 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Thu, 7 Dec 2023 15:41:07 +0000 Received: from e127754.cambridge.arm.com (10.1.34.67) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Thu, 7 Dec 2023 15:41:07 +0000 From: To: CC: Subject: [PATCH v2 2/3] [GCC] arm: vld1_types_x3 ACLE intrinsics Date: Thu, 7 Dec 2023 15:41:05 +0000 Message-ID: <20231207154106.4808-3-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20231207154106.4808-1-Ezra.Sitorus@arm.com> References: <20231207154106.4808-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001B4:EE_|DU0PR08MB9822:EE_|DB5PEPF00014B96:EE_|DU0PR08MB7738:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c9a05cf-a0e1-4ea6-222b-08dbf73af564 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: s1e2nSUlBBp/xb2t7N5ghe9s+orxS/E/04J87leMOLPAakQFPrvHjkgJ/ijIFBnnFYM2P7d20DBv+DZ4tqtcSe0fzAZZwPhSAe4OvDPPXizCS63x1wJNNvpQzJDrpCx88/odJa+VbLxe0VapVLn7KZ+F3b3HLAAWu0zwpCINYfV8udTYJKeRFKdozujNiR+J8fX2HyiqK7WZhmWsJ3oq4ocnGiXgQH5631Z0Id5XRHA9N26T8tE9/vIdu10CaRFe/R80yMmbJacthp59E4Q9FGoZSA+gxcViQPgbnpECCrkK+WOQZPTowamv2RU6pARlzl0KAz3sp8T4PDoXwa+slvfjZRv9cMiQhbFR4LZC3C0W186HNzTcOa36dHwfMB35pdnoM0hbDNDGx24caCz4FfvWOcYOBV/8JHaZlsGqCF/8qQOcEVHGw9ijo179ajU9tRYv63axq0QHYB8Zcjx4EJTfRyo9YmajrW9Qd2Dbph6G7778HKas1up7n50OpSeQQ/UdaSPnrdR+U76F/Em0Ry899KwhMwygXSAw2AQme1iGKoAUpNqtfWUZBccbEvips4PEDdZoULVhMwpCahb4fT4X2hjTkKxWil2resSKKhD2YGWyBDG1JUAm/wQegmeXRKpTaVqfRi29UjxPBBjs73gleEkgQkNrrddy1thIV7z0/dFo+oT3Z71c3Lerv7/RHQtfmnErTWGOiJtq7VRCoWeQBwFoT+nHpWE1iXEbdyrOelERf8jp7V9quID1fSsvZrVYxmHfgc2iQQls8nEl590cjCwcNkxWbgUTczz0YQ4= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(136003)(376002)(39860400002)(346002)(396003)(230922051799003)(82310400011)(1800799012)(451199024)(64100799003)(186009)(40470700004)(36840700001)(46966006)(41300700001)(36756003)(5660300002)(40460700003)(2906002)(30864003)(2876002)(82740400003)(426003)(36860700001)(83380400001)(7696005)(966005)(478600001)(47076005)(356005)(8936002)(4326008)(1076003)(8676002)(2616005)(26005)(336012)(86362001)(40480700001)(6916009)(81166007)(316002)(84970400001)(70586007)(70206006)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9822 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5PEPF00014B96.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 655cfd1d-ec29-453d-b772-08dbf73aeead X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tmqQcmKd1qyPkCnKRtZtnuycAI8+cd3XIe+ryzWp+fkOl9ZanUTQciQrJIi/DHiyWLFA6OlUWYgVxv8U+3GdF5vECO8fZr72kZpz6B1kj5C1Kpl3RYy5ufjZ4+UY5I3wxfF1jBURJsltpFLa3la+lqvSh0aSZVJKDWKWk8QO+lAgg02ekOi1DyvV7KpI6e/J/vObi6bPePqkPq1K+xuaMhJsZm+9Z8HwryYS8iXb6yzKVnuNOM36rhqf5rSfMCPx04cMoAPaEGBoVAocBB4RVNCzE8qqTKOjysJQ9p5JdM2eOqBibMYpJoQ6WMTL0AWsb3ZtENWwb8s2wZF+eDL7jMG1K0xZSdVhjnAC7yhwOAaJuDLatUDl1SCcjMqu8HuvFr/OQfCijTZ8VkXm4RT3v/EDlykBF3mTZCiv2W3BbkXtGZDQwowTUPF45707fRVDmaQzaiiGeO3i/wbZfusDEdTQFNrqPi9wAGOH1SGPhJMko79Soq39rKUBLZE6iH/UpacoOdyO8LINYRGLGCeQZtcfSu7cM2kKr+MUKKsQnDuf7x/CZ6rO+8dsrR4WliF1hBtVFT5Th+M8Gbh/tND8qtWuAHRoggNK3EFriaPOuEWynfl5UnybYx1lAVM2PeByMj/iJYoclG3JdfCZm5tuNS2K4U4viKW7w5IXAuA37RVTG3PGbl7Y6YAD8l+YCD1hMI1MBRRMcKWtk7mAV1ljWOzgKUlxKd7Lka2+67JG/1QPSxRnKxTC/krdnNsGBMT5VOd9Si/ItQCx8XAWHVHyUg== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(376002)(39860400002)(346002)(136003)(396003)(230922051799003)(64100799003)(451199024)(82310400011)(1800799012)(186009)(46966006)(40470700004)(36840700001)(7696005)(83380400001)(426003)(40460700003)(1076003)(2616005)(336012)(26005)(316002)(70206006)(70586007)(6916009)(84970400001)(40480700001)(5660300002)(30864003)(4326008)(2906002)(86362001)(2876002)(8936002)(8676002)(36756003)(41300700001)(966005)(82740400003)(81166007)(478600001)(36860700001)(47076005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 15:41:20.0201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c9a05cf-a0e1-4ea6-222b-08dbf73af564 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B96.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7738 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vld1 intrinsic for the arm port. This patch adds the _x3 variants of the vld1 intrinsic. The previous vld1_x3 has been updated to vld1q_x3 to take into account that it works with 4-word-length types. vld1_x3 is now only for 2-word-length types. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New. (vld1_f16_x3, vld1_f32_x3): New. (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New. (vld1_bf16_x3): New. (vld1q_types_x3): Updated to use vld1q_x3 from arm_neon_builtins.def * config/arm/arm_neon_builtins.def (vld1_x3): Updated entries. (vld1q_x3): New entries, but comes from the old vld1_x2 * config/arm/neon.md (neon_vld1q_x3): Updated from neon_vld1_x3. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 156 ++++++++++++++++-- gcc/config/arm/arm_neon_builtins.def | 3 +- gcc/config/arm/neon.md | 10 ++ .../gcc.target/arm/simd/vld1_base_xN_1.c | 63 ++++++- .../gcc.target/arm/simd/vld1_bf16_xN_1.c | 7 +- .../gcc.target/arm/simd/vld1_fp16_xN_1.c | 7 +- .../gcc.target/arm/simd/vld1_p64_xN_1.c | 7 +- 7 files changed, 231 insertions(+), 22 deletions(-) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 669b8fffb40..dbc37cafe28 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -10316,6 +10316,15 @@ vld1_p64_x2 (const poly64_t * __a) return __rv.__i; } +__extension__ extern __inline poly64x1x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p64_x3 (const poly64_t * __a) +{ + union { poly64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #pragma GCC pop_options __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10381,6 +10390,42 @@ vld1_s64_x2 (const int64_t * __a) return __rv.__i; } +__extension__ extern __inline int8x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s8_x3 (const int8_t * __a) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s16_x3 (const int16_t * __a) +{ + union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int32x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s32_x3 (const int32_t * __a) +{ + union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline int64x1x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s64_x3 (const int64_t * __a) +{ + union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) __extension__ extern __inline float16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10417,6 +10462,26 @@ vld1_f32_x2 (const float32_t * __a) return __rv.__i; } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline float16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f16_x3 (const float16_t * __a) +{ + union { float16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4hf (__a); + return __rv.__i; +} +#endif + +__extension__ extern __inline float32x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f32_x3 (const float32_t * __a) +{ + union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2sf ((const __builtin_neon_sf *) __a); + return __rv.__i; +} + __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_u8 (const uint8_t * __a) @@ -10481,6 +10546,42 @@ vld1_u64_x2 (const uint64_t * __a) return __rv.__i; } +__extension__ extern __inline uint8x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u8_x3 (const uint8_t * __a) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u16_x3 (const uint16_t * __a) +{ + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint32x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u32_x3 (const uint32_t * __a) +{ + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint64x1x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u64_x3 (const uint64_t * __a) +{ + union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + __extension__ extern __inline poly8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_p8 (const poly8_t * __a) @@ -10513,6 +10614,24 @@ vld1_p16_x2 (const poly16_t * __a) return __rv.__i; } +__extension__ extern __inline poly8x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p8_x3 (const poly8_t * __a) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline poly16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p16_x3 (const poly16_t * __a) +{ + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + #pragma GCC push_options #pragma GCC target ("fpu=crypto-neon-fp-armv8") __extension__ extern __inline poly64x2_t @@ -10536,7 +10655,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p64_x3 (const poly64_t * __a) { union { poly64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10619,7 +10738,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s8_x3 (const uint8_t * __a) { union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10628,7 +10747,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s16_x3 (const uint16_t * __a) { union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10637,7 +10756,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s32_x3 (const int32_t * __a) { union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x3v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10646,7 +10765,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s64_x3 (const int64_t * __a) { union { int64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10728,7 +10847,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f16_x3 (const float16_t * __a) { union { float16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hf (__a); + __rv.__o = __builtin_neon_vld1q_x3v8hf (__a); return __rv.__i; } #endif @@ -10738,7 +10857,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f32_x3 (const float32_t * __a) { union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4sf ((const __builtin_neon_sf *) __a); + __rv.__o = __builtin_neon_vld1q_x3v4sf ((const __builtin_neon_sf *) __a); return __rv.__i; } @@ -10831,7 +10950,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u8_x3 (const uint8_t * __a) { union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10840,7 +10959,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u16_x3 (const uint16_t * __a) { union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10849,7 +10968,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u32_x3 (const uint32_t * __a) { union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x3v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10858,7 +10977,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u64_x3 (const uint64_t * __a) { union { uint64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10935,7 +11054,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p8_x3 (const poly8_t * __a) { union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10944,7 +11063,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p16_x3 (const poly16_t * __a) { union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -20944,6 +21063,15 @@ vld1_bf16_x2 (const bfloat16_t * __ptr) return __rv.__i; } +__extension__ extern __inline bfloat16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_bf16_x3 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4bf ((const __builtin_neon_bf *) __ptr); + return __rv.__i; +} + __extension__ extern __inline bfloat16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16 (const bfloat16_t * __ptr) @@ -20965,7 +21093,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16_x3 (const bfloat16_t * __ptr) { union { bfloat16x8x3_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8bf ((const __builtin_neon_bf *) __ptr); + __rv.__o = __builtin_neon_vld1q_x3v8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 07750c03c08..c74f0db645b 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -303,7 +303,8 @@ VAR13 (LOAD1, vld1, v4bf, v8bf) VAR7 (LOAD1, vld1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (LOAD1, vld1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) -VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) +VAR7 (LOAD1, vld1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (LOAD1, vld1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR12 (LOAD1LANE, vld1_lane, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 75add42777d..e67cbc247d9 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -4968,6 +4968,16 @@ if (BYTES_BIG_ENDIAN) ) (define_insn "neon_vld1_x3" + [(set (match_operand:EI 0 "s_register_operand" "=w") + (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD1))] + "TARGET_NEON" + "vld1.\t%h0, %A1" + [(set_attr "type" "neon_load1_3reg")] +) + +(define_insn "neon_vld1q_x3" [(set (match_operand:CI 0 "s_register_operand" "=w") (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c index 6b0e78d94d7..95314bbe0de 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c @@ -60,7 +60,62 @@ poly16x4x2_t test_vld1_p16_x2 (poly16_t * a) return vld1_p16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ \ No newline at end of file +uint8x8x3_t test_vld1_u8_x3 (uint8_t * a) +{ + return vld1_u8_x3 (a); +} + +uint16x4x3_t test_vld1_u16_x3 (uint16_t * a) +{ + return vld1_u16_x3 (a); +} + +uint32x2x3_t test_vld1_u32_x3 (uint32_t * a) +{ + return vld1_u32_x3 (a); +} + +uint64x1x3_t test_vld1_u64_x3 (uint64_t * a) +{ + return vld1_u64_x3 (a); +} + +int8x8x3_t test_vld1_s8_x3 (int8_t * a) +{ + return vld1_s8_x3 (a); +} + +int16x4x3_t test_vld1_s16_x3 (int16_t * a) +{ + return vld1_s16_x3 (a); +} + +int32x2x3_t test_vld1_s32_x3 (int32_t * a) +{ + return vld1_s32_x3 (a); +} + +int64x1x3_t test_vld1_s64_x3 (int64_t * a) +{ + return vld1_s64_x3 (a); +} + +float32x2x3_t test_vld1_f32_x3 (float32_t * a) +{ + return vld1_f32_x3 (a); +} + +poly8x8x3_t test_vld1_p8_x3 (poly8_t * a) +{ + return vld1_p8_x3 (a); +} + +poly16x4x3_t test_vld1_p16_x3 (poly16_t * a) +{ + return vld1_p16_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c index 3ec7a5e1986..c1935da0a4c 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c @@ -10,4 +10,9 @@ bfloat16x4x2_t test_vld1_bf16_x2 (bfloat16_t * a) return vld1_bf16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ \ No newline at end of file +bfloat16x4x3_t test_vld1_bf16_x3 (bfloat16_t * a) +{ + return vld1_bf16_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c index c0e5ea49142..20363239f5b 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c @@ -10,4 +10,9 @@ float16x4x2_t test_vld1_f16_x2 (float16_t * a) return vld1_f16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +float16x4x3_t test_vld1_f16_x3 (float16_t * a) +{ + return vld1_f16_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c index 3ccea520ddc..210de511c71 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c @@ -10,4 +10,9 @@ poly64x1x2_t test_vld1_p64_x2 (poly64_t * a) return vld1_p64_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ +poly64x1x3_t test_vld1_p64_x3 (poly64_t * a) +{ + return vld1_p64_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ From patchwork Thu Dec 7 15:41:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 1873268 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com header.b=Ql7ZTdeY; dkim=pass (1024-bit key) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com header.b=Ql7ZTdeY; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SmJRD6KQQz23nW for ; Fri, 8 Dec 2023 02:41:44 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E27633861856 for ; Thu, 7 Dec 2023 15:41:42 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2079.outbound.protection.outlook.com [40.107.6.79]) by sourceware.org (Postfix) with ESMTPS id 034FE385C6D7 for ; Thu, 7 Dec 2023 15:41:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 034FE385C6D7 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 034FE385C6D7 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.6.79 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1701963689; cv=pass; b=Utc1TGdys9/LdirbvlsqmZB2bPgKKpEAMMuCmf8g9wOTtpeIdUsRr+RPvlK4vPzuHuTSGExI0GWX8bhlXTktAP3ZCG8l7fry6maAlL0R0kdgqUZn0RlUYjkfxil1sZkNnOK8myghzeHAzPxc0hcdXarVHxI52dOSG3BzcCXB7gg= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1701963689; c=relaxed/simple; bh=YgkSLMLXusfAVEpsApKabQ/CGOIHicwoqE6/3GuKFPA=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=BWKfnhdZViT5WqR/0fy1QlIamvDUJJh7Pe/uP/Cos+Da7bltvTuHbkfM8TDlaPipa0nJlpbFNZskX89ONqsC6WxR6XIou9/vqsU+hcyKjSdR2XhxPvS5fhNFCBZ5ko6OuoD2zLxJ+VXB/zGSid3G86BMRHlNMx+RnRoi5MjV2Yk= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=Av6ROFhXaMVQ7ci6L40hwzvBzxpYG8erDgDywH5rgjibCZIVEVCDA+mxGa1L0YYdT1K5+xk4/3CQ1MqK07vTuqoDRNNxo1urwHD6xFODNN94aLCwhPF6X0Vj7dY0l48ylCHBjg6WWHaEhQBvAd6KoNUetFYsZ2D7GRKTJTLFiEfWvbVJNcyxwgjcRbTnLvFYjCQSlGCmq5k104Ik39bhQ1HlcJ6SF0wtNVS1laKAcoGxMBB96+ZYF2EK6QC2jvTQrgemG1RjCbkKXU5Nu/2IsZShV9AOOmv4d0w4Qf3/VN8ux081168OL6cs5M0rLvDfl/HtEbB8uJDTFy8caytpVQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=w8Lp+n69enoNPCq1/RjIDaRAYoUZO8LnF3X6x2YASLY=; b=ALcADQeCubw4UOaW6BZ/SftY+Dt7RpmEbRdYIp5CSDaZiegNzWecj31GG5lsUsduDjOA6Q8QGsp2ASpCLTrw9wx2L8CQx37xEEopXEqnST3YirkSCd20z8Xp85zdwOb8j7LHDVhaDUAlBuKtHtj6Ea2F3RJSQAP1RXZOu5lQEgPB3/eWnqzmye8dlClRoefCnISZXCi6xSQsi7LHlkMOYcLqmRQGMkL9nOcTKvqwpraPOUFIaZhvjzFgL6P9Nw4M+P9QlrMHNbbVxrDhgo8JoY9qzj8/LoKyWoi3IGmp5UkG4Akc3zrUeYWPYTxa3mX+sR0bMgQEtyv4zqdK42CGJg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=w8Lp+n69enoNPCq1/RjIDaRAYoUZO8LnF3X6x2YASLY=; b=Ql7ZTdeYXWudU91UY+119aZ8ovwE3OkYSfHd0Y4re7gcv5DyD4i3JqT26qoHYL2hgPwkxbxFCkTLfMb7V5LZfhtnlGbiO4zTznl21DCXidFbQBIWqptt1fXxcqIgUUQ87C35SJPPjL58m6dShWdANvqK9BuKjgRt4bY0oBGuAzg= Received: from DU2PR04CA0056.eurprd04.prod.outlook.com (2603:10a6:10:234::31) by PAWPR08MB9470.eurprd08.prod.outlook.com (2603:10a6:102:2e9::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.27; Thu, 7 Dec 2023 15:41:19 +0000 Received: from DB5PEPF00014B9C.eurprd02.prod.outlook.com (2603:10a6:10:234:cafe::e) by DU2PR04CA0056.outlook.office365.com (2603:10a6:10:234::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.34 via Frontend Transport; Thu, 7 Dec 2023 15:41:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5PEPF00014B9C.mail.protection.outlook.com (10.167.8.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.20 via Frontend Transport; Thu, 7 Dec 2023 15:41:19 +0000 Received: ("Tessian outbound 7c4ecdadb9e7:v228"); Thu, 07 Dec 2023 15:41:19 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 340d43c16494807a X-CR-MTA-TID: 64aa7808 Received: from f9e3908a06b2.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 0F060CCE-6614-48AB-AF90-2C85C48DD6F9.1; Thu, 07 Dec 2023 15:41:12 +0000 Received: from EUR04-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id f9e3908a06b2.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 07 Dec 2023 15:41:12 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IJUncCFXhjH7ME+ufbmBKwTtD4/4mhIYVma9mKph+hKJq0W5Cm1yyHhoG1kSvMWnOJKpFsEfmz2x6z83X61ca3z4t4hu/uzBKyCSO4XxHMmfZlQ4Rgeq7vTVRD4ZwD90qP66MI+3GPE2Gxhsuc+mvX+cECuKC9UQbZD/FRf45EaBaFav0X/yFS2Twtpo/7ZubydFWYrlzedEVtza5ECZLmk4dl78tU/mxEoTp0qfVgGylpn8bmaqUmtdkhwLIy/Ey8MPKpqbfDnA72JV8ghVpBJPyjbDgR20QC0nNuYDY6Dadwv00gTd4I/BvKbuf9k5lGG8N98bPk46xp969hVs0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=w8Lp+n69enoNPCq1/RjIDaRAYoUZO8LnF3X6x2YASLY=; b=JISb6gLiSmnoTEWpwq19PoEW55DHH7zh3Z4DPA7y4AnXQe+71macJIjxgkF9Wo3JmfeSRF+k3VW5Bv1K4ZYV+GgwwbaJUldC0h4HuSuEeifZSapNi2ryr8pkBkOXxr+lY7vH8RAfdkMkcIoOvmMSY6jCsK9FcNwXbZMfVXN14pNlVpoXUBNHrFE34hz7elX+7eDqo3/fj8M5Hl1fpCVDYKmpSUe2xqZ698RR6rh1zWa3VVpwhKVf4SZ7B6T4gzMRXqNi4IsHJig7qVnohXI+HY+TLzQW3BurUxuRT5REl66rdnx/jNNBq0NsMJGAkMSYAiPk/jDwFGvc0vrDT713NA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=w8Lp+n69enoNPCq1/RjIDaRAYoUZO8LnF3X6x2YASLY=; b=Ql7ZTdeYXWudU91UY+119aZ8ovwE3OkYSfHd0Y4re7gcv5DyD4i3JqT26qoHYL2hgPwkxbxFCkTLfMb7V5LZfhtnlGbiO4zTznl21DCXidFbQBIWqptt1fXxcqIgUUQ87C35SJPPjL58m6dShWdANvqK9BuKjgRt4bY0oBGuAzg= Received: from AS9PR05CA0123.eurprd05.prod.outlook.com (2603:10a6:20b:497::13) by PA4PR08MB6174.eurprd08.prod.outlook.com (2603:10a6:102:e6::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.27; Thu, 7 Dec 2023 15:41:09 +0000 Received: from AMS0EPF000001B7.eurprd05.prod.outlook.com (2603:10a6:20b:497:cafe::88) by AS9PR05CA0123.outlook.office365.com (2603:10a6:20b:497::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.33 via Frontend Transport; Thu, 7 Dec 2023 15:41:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AMS0EPF000001B7.mail.protection.outlook.com (10.167.16.171) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7068.20 via Frontend Transport; Thu, 7 Dec 2023 15:41:09 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Thu, 7 Dec 2023 15:41:08 +0000 Received: from e127754.cambridge.arm.com (10.1.34.67) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Thu, 7 Dec 2023 15:41:08 +0000 From: To: CC: Subject: [PATCH v2 3/3] [GCC] arm: vld1_types_x4 ACLE intrinsics Date: Thu, 7 Dec 2023 15:41:06 +0000 Message-ID: <20231207154106.4808-4-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20231207154106.4808-1-Ezra.Sitorus@arm.com> References: <20231207154106.4808-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001B7:EE_|PA4PR08MB6174:EE_|DB5PEPF00014B9C:EE_|PAWPR08MB9470:EE_ X-MS-Office365-Filtering-Correlation-Id: 31d6db56-8ed3-419a-09e6-08dbf73af504 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: EIPLIZnOqLBFEAtoh5FaSqkYKCuQvWXzttuU2xHreOpqmOaCzR5AAI7CqJyI5jPf7+hRG+Zz+4/AL43JCv4eMb0nxpQ9Yg3/O+Fj1Dnqupp909EnGP1FxVkyXsVOzieJ11xCtsFbidjSnZZz2IMvDvT4nUnVOJky233HApBcWW6Zs+05G4jF5snTamsouE8g2TKA5l/TARAqOoTaRe/KT9GJMFlDQQ1Iy7tT5S9ZMxCjCZDFdLwkOI2lWz07EKI/PK0oNJyE4VqJHPS51shlKnZpZHanFkLKsfLplELW0eFodiJJSvaMkB8UAlpcRX8zvVc4s0qcv/ANbWAA0QZ2jb4IuP/CnNBrZz5XBX1/gxkfc3JoOCbbN9D/tavoRnAqToHSt60afmTxdMWW/3s0UcrfTArQs3rFK838oKnh3KJg9qaeFasGMtdhhM++EX7BZlAV9Rp92oq9c+aiob9quFQnQgTgfMbSUWw3C/ITKFjrHbWgLKvHm9d9ZT1FSovRU3VThxQYi5x2127Bcd/ASjLcuLtLJcyzRWkig3sOGHZFEEMPH0AlPAYkm9SA4V/D76Y012N9nfsntoc9MR5jCWR9uVSSP9lvT271hWXjRzm3u8A3b4cML5gwN2moY6+JoJa6k4bbAIt6wQ7D5HKHS1JqAfTPG3yWVhuSJCfzaNuyfsr3HGcFw2AMcgEjLB/N5Z4Uo06/1KfLxepc4ld1OzNvwqs61698/wVYSt3XV7H55ITqELGPLfcubSXF6t4mkt5iFSXUC63Q4dflLyb/LnLWaym63l/qjTiL2A0z7sQ= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(346002)(136003)(396003)(376002)(230922051799003)(64100799003)(82310400011)(451199024)(1800799012)(186009)(36840700001)(40470700004)(46966006)(2876002)(2906002)(8676002)(4326008)(8936002)(30864003)(5660300002)(84970400001)(40480700001)(316002)(82740400003)(81166007)(40460700003)(356005)(966005)(70586007)(6916009)(70206006)(86362001)(36860700001)(478600001)(41300700001)(36756003)(7696005)(336012)(426003)(47076005)(26005)(2616005)(83380400001)(1076003)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6174 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5PEPF00014B9C.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: f40bb73c-c7fc-4fb2-4841-08dbf73aeef3 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1lhzuBQs6YzdJRvY2Q4j5B6vulBB9sGtZBFbzLoKlPG/XUFz/NQA29BhSYJIYyNSjKOswph4xZmKLXlKdG9M03Cd2JYXozGwwU2XnFvnT9nJrtoMMctZaDhQkSVVwnqcRGQxYxY2EPfcb8+Gsvy3JPjqJ0q6HYarkr7enLTtjqM0ZEjl0rYnQ0dOA2xstAS7MQ0/Ie1qaLLXyx9c3R1UQqbgrXMYU915JoS+eXegahcrLWmTY19z4wFVIP085VRoWS2CBlpUEvrGkKCgW+qFeiSWW0Yp4UDsSqOhhACVIHZbhEC7zcdzIfj8q7Lhkhb6A14O2vuRkFSf+UueiCdhnuVOEMsAZT6yH7hvgplKh9vj6FCIsUkUBV6UgYm+aw6ZMSPQFnMne3Fx0KRUC7SaroBPSWAMl6nsJFcYZjscQwWpbqilbAGDkee5cM0RAyBTn+AEz2Qd3Hd6ErPSVD8xbLZdT5EHpwR7pyvJGAAX3Flmh5k/tPhwugFufJthR+Sd0359mfVHpGf152ybjd6LVDQHRxBXORm0QvAQvrHIhHxXflDC0hh4UfVS/CmT8FLxWbsyypQSr1c2DNcT2uQytxiPJjiQvIPpHqXZFOYsJR/RCIYL/WLwswuXHLC4aE8iDDnlwJkVdp4f1rmvaT6Yd33CcKiewwManUB2HYEPSd6iXUqn5xlhegxCUPE0rk2iJU5A6wIo6zImHHNH75Cdj6POiad5Wd97TOEE3had3gNwnln147t2OpykwnAhnxTHcDXtwczAhoUIX74eDh8GfA== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(376002)(136003)(346002)(39860400002)(396003)(230922051799003)(1800799012)(186009)(451199024)(64100799003)(82310400011)(36840700001)(46966006)(40470700004)(47076005)(82740400003)(40460700003)(36860700001)(83380400001)(36756003)(41300700001)(26005)(336012)(426003)(966005)(316002)(7696005)(8936002)(8676002)(4326008)(86362001)(6916009)(70586007)(70206006)(478600001)(2876002)(2616005)(30864003)(1076003)(2906002)(5660300002)(81166007)(84970400001)(40480700001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 15:41:19.3903 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31d6db56-8ed3-419a-09e6-08dbf73af504 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B9C.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB9470 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vld1 intrinsic for the arm port. This patch adds the _x4 variants of the vld1 intrinsic. The previous vld1_x4 has been updated to vld1q_x4 to take into account that it works with 4-word-length types. vld1_x4 is now only for 2-word-length types. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New. (vld1_f16_x4, vld1_f32_x4): New. (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New. (vld1_bf16_x4): New. (vld1q_types_x4): Updated to use vld1q_x4 from arm_neon_builtins.def * config/arm/arm_neon_builtins.def (vld1_x4): Updated entries. (vld1q_x4): New entries, but comes from the old vld1_x2 * config/arm/neon.md (neon_vld1q_x4): Updated from neon_vld1_x4. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 156 ++++++++++++++++-- gcc/config/arm/arm_neon_builtins.def | 3 +- gcc/config/arm/neon.md | 10 ++ .../gcc.target/arm/simd/vld1_base_xN_1.c | 63 ++++++- .../gcc.target/arm/simd/vld1_bf16_xN_1.c | 7 +- .../gcc.target/arm/simd/vld1_fp16_xN_1.c | 7 +- .../gcc.target/arm/simd/vld1_p64_xN_1.c | 7 +- 7 files changed, 231 insertions(+), 22 deletions(-) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index dbc37cafe28..8bcf1d6325e 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -10325,6 +10325,15 @@ vld1_p64_x3 (const poly64_t * __a) return __rv.__i; } +__extension__ extern __inline poly64x1x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p64_x4 (const poly64_t * __a) +{ + union { poly64x1x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #pragma GCC pop_options __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10426,6 +10435,42 @@ vld1_s64_x3 (const int64_t * __a) return __rv.__i; } +__extension__ extern __inline int8x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s8_x4 (const int8_t * __a) +{ + union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int16x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s16_x4 (const int16_t * __a) +{ + union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int32x2x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s32_x4 (const int32_t * __a) +{ + union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline int64x1x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s64_x4 (const int64_t * __a) +{ + union { int64x1x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) __extension__ extern __inline float16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10482,6 +10527,26 @@ vld1_f32_x3 (const float32_t * __a) return __rv.__i; } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline float16x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f16_x4 (const float16_t * __a) +{ + union { float16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v4hf (__a); + return __rv.__i; +} +#endif + +__extension__ extern __inline float32x2x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f32_x4 (const float32_t * __a) +{ + union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v2sf ((const __builtin_neon_sf *) __a); + return __rv.__i; +} + __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_u8 (const uint8_t * __a) @@ -10582,6 +10647,42 @@ vld1_u64_x3 (const uint64_t * __a) return __rv.__i; } +__extension__ extern __inline uint8x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u8_x4 (const uint8_t * __a) +{ + union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint16x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u16_x4 (const uint16_t * __a) +{ + union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint32x2x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u32_x4 (const uint32_t * __a) +{ + union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint64x1x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u64_x4 (const uint64_t * __a) +{ + union { uint64x1x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + __extension__ extern __inline poly8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_p8 (const poly8_t * __a) @@ -10632,6 +10733,24 @@ vld1_p16_x3 (const poly16_t * __a) return __rv.__i; } +__extension__ extern __inline poly8x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p8_x4 (const poly8_t * __a) +{ + union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline poly16x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p16_x4 (const poly16_t * __a) +{ + union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + #pragma GCC push_options #pragma GCC target ("fpu=crypto-neon-fp-armv8") __extension__ extern __inline poly64x2_t @@ -10664,7 +10783,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p64_x4 (const poly64_t * __a) { union { poly64x2x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x4v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10774,7 +10893,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s8_x4 (const uint8_t * __a) { union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x4v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10783,7 +10902,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s16_x4 (const uint16_t * __a) { union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x4v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10792,7 +10911,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s32_x4 (const int32_t * __a) { union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x4v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10801,7 +10920,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s64_x4 (const int64_t * __a) { union { int64x2x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x4v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10867,7 +10986,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f16_x4 (const float16_t * __a) { union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v8hf (__a); + __rv.__o = __builtin_neon_vld1q_x4v8hf (__a); return __rv.__i; } #endif @@ -10877,7 +10996,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f32_x4 (const float32_t * __a) { union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v4sf ((const __builtin_neon_sf *) __a); + __rv.__o = __builtin_neon_vld1q_x4v4sf ((const __builtin_neon_sf *) __a); return __rv.__i; } @@ -10986,7 +11105,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u8_x4 (const uint8_t * __a) { union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x4v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10995,7 +11114,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u16_x4 (const uint16_t * __a) { union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x4v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -11004,7 +11123,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u32_x4 (const uint32_t * __a) { union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x4v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -11013,7 +11132,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u64_x4 (const uint64_t * __a) { union { uint64x2x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x4v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -11072,7 +11191,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p8_x4 (const poly8_t * __a) { union { poly8x16x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x4v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -11081,7 +11200,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p16_x4 (const poly16_t * __a) { union { poly16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x4v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -21072,6 +21191,15 @@ vld1_bf16_x3 (const bfloat16_t * __ptr) return __rv.__i; } +__extension__ extern __inline bfloat16x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_bf16_x4 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x4v4bf ((const __builtin_neon_bf *) __ptr); + return __rv.__i; +} + __extension__ extern __inline bfloat16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16 (const bfloat16_t * __ptr) @@ -21102,7 +21230,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16_x4 (const bfloat16_t * __ptr) { union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x4v8bf ((const __builtin_neon_bf *) __ptr); + __rv.__o = __builtin_neon_vld1q_x4v8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index c74f0db645b..20dfcae7de5 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -305,7 +305,8 @@ VAR7 (LOAD1, vld1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (LOAD1, vld1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (LOAD1, vld1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (LOAD1, vld1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) -VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) +VAR7 (LOAD1, vld1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (LOAD1, vld1q_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR12 (LOAD1LANE, vld1_lane, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf) VAR10 (LOAD1, vld1_dup, diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index e67cbc247d9..30f5bf8e40e 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5005,6 +5005,16 @@ if (BYTES_BIG_ENDIAN) ) (define_insn "neon_vld1_x4" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD1))] + "TARGET_NEON" + "vld1.\t%h0, %A1" + [(set_attr "type" "neon_load1_4reg")] +) + +(define_insn "neon_vld1q_x4" [(set (match_operand:XI 0 "s_register_operand" "=w") (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um") (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c index 95314bbe0de..a5686ffac01 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c @@ -115,7 +115,62 @@ poly16x4x3_t test_vld1_p16_x3 (poly16_t * a) return vld1_p16_x3 (a); } -/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ -/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ \ No newline at end of file +uint8x8x4_t test_vld1_u8_x4 (uint8_t * a) +{ + return vld1_u8_x4 (a); +} + +uint16x4x4_t test_vld1_u16_x4 (uint16_t * a) +{ + return vld1_u16_x4 (a); +} + +uint32x2x4_t test_vld1_u32_x4 (uint32_t * a) +{ + return vld1_u32_x4 (a); +} + +uint64x1x4_t test_vld1_u64_x4 (uint64_t * a) +{ + return vld1_u64_x4 (a); +} + +int8x8x4_t test_vld1_s8_x4 (int8_t * a) +{ + return vld1_s8_x4 (a); +} + +int16x4x4_t test_vld1_s16_x4 (int16_t * a) +{ + return vld1_s16_x4 (a); +} + +int32x2x4_t test_vld1_s32_x4 (int32_t * a) +{ + return vld1_s32_x4 (a); +} + +int64x1x4_t test_vld1_s64_x4 (int64_t * a) +{ + return vld1_s64_x4 (a); +} + +float32x2x4_t test_vld1_f32_x4 (float32_t * a) +{ + return vld1_f32_x4 (a); +} + +poly8x8x4_t test_vld1_p8_x4 (poly8_t * a) +{ + return vld1_p8_x4 (a); +} + +poly16x4x4_t test_vld1_p16_x4 (poly16_t * a) +{ + return vld1_p16_x4 (a); +} + +/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */ +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */ +/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */ +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 6 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c index c1935da0a4c..7ed17834ccf 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c @@ -15,4 +15,9 @@ bfloat16x4x3_t test_vld1_bf16_x3 (bfloat16_t * a) return vld1_bf16_x3 (a); } -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file +bfloat16x4x4_t test_vld1_bf16_x4 (bfloat16_t * a) +{ + return vld1_bf16_x4 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c index 20363239f5b..82e7211ebbf 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c @@ -15,4 +15,9 @@ float16x4x3_t test_vld1_f16_x3 (float16_t * a) return vld1_f16_x3 (a); } -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ +float16x4x4_t test_vld1_f16_x4 (float16_t * a) +{ + return vld1_f16_x4 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c index 210de511c71..644371b89ea 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c @@ -15,4 +15,9 @@ poly64x1x3_t test_vld1_p64_x3 (poly64_t * a) return vld1_p64_x3 (a); } -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +poly64x1x4_t test_vld1_p64_x4 (poly64_t * a) +{ + return vld1_p64_x4 (a); +} + +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 3 } } */