From patchwork Tue Nov 28 10:34:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Rojek X-Patchwork-Id: 1869229 X-Patchwork-Delegate: seanga2@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=conclusive.pl header.i=@conclusive.pl header.a=rsa-sha256 header.s=google header.b=jpFKPQj9; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Sff4q3WhWz23mg for ; Tue, 28 Nov 2023 21:36:11 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 205E7876BF; Tue, 28 Nov 2023 11:35:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=conclusive.pl Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=conclusive.pl header.i=@conclusive.pl header.b="jpFKPQj9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A3E6F87652; Tue, 28 Nov 2023 11:35:53 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C303786F4F for ; Tue, 28 Nov 2023 11:35:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=conclusive.pl Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=artur@conclusive.pl Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-5488bf9e193so7213665a12.2 for ; Tue, 28 Nov 2023 02:35:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conclusive.pl; s=google; t=1701167751; x=1701772551; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gTgXspvtHrY9wMvp2zonRdToCyTkcUXYYIP919AlYss=; b=jpFKPQj9TUGqZ+e58+XsV/AAFoU5VUgqWblIs2K4fHs1slfdC1I08mMPkFXvuvqsbn AHKWFWQnxTVN6QPp7Mm/vPH+Qb/cRJlHyey4li961rntPc2kmeb/N+5/wcPLHKpq1QmM oJ+5GBBTYnMIuY64ULfCk4irkUyKiV5MvEeqzqknavsO5a4WHUan5lrvGP8wFYySzd6a omc1Qg5EHVLwqV9+jtRoJfp4YxOhV3CNIXYvy0C1oEQNMyhnTq5wBB/imehwMNFGt7/3 Qzw1LJmg0IlYAgw8ncYBIMn4ldF0aHzUjnY5kU+FUg1r3r2mwypzy80vlp+r+471fPHY YxAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701167751; x=1701772551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gTgXspvtHrY9wMvp2zonRdToCyTkcUXYYIP919AlYss=; b=skkF66BjWgBtuiH/xyVmSZL19dZTqzjSPBaVnWELsmrl2rLU/4JWZqoj21Vlgh6V3Z UYBMfN0mNWHZc1s4atwHJ5aESKiWlXxpgn9zB9NnGEtu6NlUiMIcgn4QSusm0AaUwabV PFx6eRb790+JTG/3xIFehEIi4NUdQCLtclfY+O0xBIxiRDIeAyn4MmWdljwEqLHtovWI bORI1R0979SYe5vDkyxtjrD+VVrBHmlUgPNxiPz12tZSMWxjhS6fyyU3kBGhFUO51rQX BXDtfH/ndwbJrjZBeTww6hrGX1Tg7aZfQAfjNbE9zim21WbHKFR8CLU3nuFIdYflykwV ygSQ== X-Gm-Message-State: AOJu0YxQ0cPzJAkO77bSG/OgilGeGM6u68hT1OGdEWqMPdDm7Mu/NH59 f9L+0ISjzCwlaWn73Aj7BcSGew== X-Google-Smtp-Source: AGHT+IFA2cAO95PmTTrJWbaZ5JoaRbOtiNFBg6uLDvuPDa3DjHaYJloQi4V9cht74rL/XlNYzmVHLw== X-Received: by 2002:a17:906:ca55:b0:a04:e6d8:dbc with SMTP id jx21-20020a170906ca5500b00a04e6d80dbcmr9763460ejb.42.1701167751223; Tue, 28 Nov 2023 02:35:51 -0800 (PST) Received: from localhost.localdomain (host-93.179.209.131.static.3s.pl. [93.179.209.131]) by smtp.gmail.com with ESMTPSA id cw16-20020a170907161000b00a169550fccesm77558ejd.111.2023.11.28.02.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 02:35:50 -0800 (PST) From: Artur Rojek To: Peng Fan , "NXP i . MX U-Boot Team" , Simon Glass , Jakub Klama , Tom Rini Cc: Wojciech Kloska , =?utf-8?q?Rados=C5=82aw_Adamcz?= =?utf-8?q?yk?= , u-boot@lists.denx.de, Artur Rojek Subject: [PATCH v3 1/3] armv8: layerscape: Enable ext4 environment storage Date: Tue, 28 Nov 2023 11:34:55 +0100 Message-ID: <20231128103457.45802-2-artur@conclusive.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231128103457.45802-1-artur@conclusive.pl> References: <20231128103457.45802-1-artur@conclusive.pl> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Jakub Klama Some boards keep their environment on MMC storage within an ext4 partition. Signed-off-by: Jakub Klama Signed-off-by: Artur Rojek Reviewed-by: Tom Rini --- v2-v3: no change arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 12d31184ad91..3775cb493732 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -857,6 +857,11 @@ enum env_location arch_env_get_location(enum env_operation op, int prio) break; } +#ifdef CONFIG_ENV_IS_IN_EXT4 + if (env_loc == ENVL_MMC) + return ENVL_EXT4; +#endif + return env_loc; } #endif /* CONFIG_TFABOOT */ From patchwork Tue Nov 28 10:34:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Rojek X-Patchwork-Id: 1869230 X-Patchwork-Delegate: seanga2@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[93.179.209.131]) by smtp.gmail.com with ESMTPSA id cw16-20020a170907161000b00a169550fccesm77558ejd.111.2023.11.28.02.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 02:35:51 -0800 (PST) From: Artur Rojek To: Peng Fan , "NXP i . MX U-Boot Team" , Simon Glass , Jakub Klama , Tom Rini Cc: Wojciech Kloska , =?utf-8?q?Rados=C5=82aw_Adamcz?= =?utf-8?q?yk?= , u-boot@lists.denx.de, Artur Rojek Subject: [PATCH v3 2/3] board: Add support for Conclusive WHLE-LS1046A Date: Tue, 28 Nov 2023 11:34:56 +0100 Message-ID: <20231128103457.45802-3-artur@conclusive.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231128103457.45802-1-artur@conclusive.pl> References: <20231128103457.45802-1-artur@conclusive.pl> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Introduce support for Conclusive WHLE-LS1046A Single Board Computer. Co-developed-by: Jakub Klama Signed-off-by: Jakub Klama Signed-off-by: Artur Rojek --- v3: no change v2: - drop non-DM_ETH case - clean-up defines in configs/whle_ls1046a.h: remove unneeded ones, move others to appropriate files in board directory - move environment variables to whle-ls1046a.env - move away from distro_bootcmd and use BOOTSTD - fix i2c-mux node parent and ext_i2c address in Device Tree - style changes to eth.c - fix CONFIG_MTDPARTS_DEFAULT value in defconfigs arch/arm/Kconfig | 19 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1046a-whle.dts | 208 +++++++++++++++++ board/conclusive/whle-ls1046a/Kconfig | 15 ++ board/conclusive/whle-ls1046a/MAINTAINERS | 9 + board/conclusive/whle-ls1046a/Makefile | 7 + board/conclusive/whle-ls1046a/ddr.c | 21 ++ board/conclusive/whle-ls1046a/eth.c | 65 ++++++ board/conclusive/whle-ls1046a/whle-ls1046a.c | 215 ++++++++++++++++++ .../conclusive/whle-ls1046a/whle-ls1046a.env | 13 ++ configs/whle_ls1046a_emmc_defconfig | 83 +++++++ configs/whle_ls1046a_qspi_defconfig | 84 +++++++ include/configs/whle_ls1046a.h | 47 ++++ 13 files changed, 787 insertions(+) create mode 100644 arch/arm/dts/fsl-ls1046a-whle.dts create mode 100644 board/conclusive/whle-ls1046a/Kconfig create mode 100644 board/conclusive/whle-ls1046a/MAINTAINERS create mode 100644 board/conclusive/whle-ls1046a/Makefile create mode 100644 board/conclusive/whle-ls1046a/ddr.c create mode 100644 board/conclusive/whle-ls1046a/eth.c create mode 100644 board/conclusive/whle-ls1046a/whle-ls1046a.c create mode 100644 board/conclusive/whle-ls1046a/whle-ls1046a.env create mode 100644 configs/whle_ls1046a_emmc_defconfig create mode 100644 configs/whle_ls1046a_qspi_defconfig create mode 100644 include/configs/whle_ls1046a.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c9842..609571e6e421 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1851,6 +1851,24 @@ config TARGET_SL28 help Support for Kontron SMARC-sAL28 board. +config TARGET_WHLE_LS1046A + bool "Support Conclusive WHLE-LS1046A" + select ARCH_LS1046A + select ARM64 + select ARMV8_MULTIENTRY + select ARCH_SUPPORT_TFABOOT + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER + select DM_SPI_FLASH if DM_SPI + imply SCSI + help + Support for Conclusive WHLE-LS1046A platform. + The WHLE-LS1046A is a high-performance Single Board Computer with + extensive connectivity features that supports the QorIQ LS1046A + Layerscape Architecture processor: + https://conclusive.tech/products/whle-ls1-sbc/ + config TARGET_TEN64 bool "Support ten64" select ARCH_LS1088A @@ -2299,6 +2317,7 @@ source "board/cortina/presidio-asic/Kconfig" source "board/broadcom/bcmns/Kconfig" source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" +source "board/conclusive/whle-ls1046a/Kconfig" source "board/eets/pdu001/Kconfig" source "board/emulation/qemu-arm/Kconfig" source "board/freescale/ls2080aqds/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1be08c5fdc2e..8dcbf29df363 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -615,6 +615,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ fsl-ls1046a-frwy.dtb \ + fsl-ls1046a-whle.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ fsl-ls1012a-2g5rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1046a-whle.dts b/arch/arm/dts/fsl-ls1046a-whle.dts new file mode 100644 index 000000000000..1aed3e8c4701 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-whle.dts @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +#include + +/dts-v1/; +#include "fsl-ls1046a.dtsi" + +/ { + model = "Conclusive WHLE-LS1046A"; + compatible = "conclusive,whle-ls1046a", "fsl,ls1046a"; + + chosen { + stdout-path = &duart0; + }; + + aliases { + spi0 = &qspi; + }; +}; + +&soc { + pcie@3400000 { + status = "okay"; + }; +}; + +&qspi { + status = "okay"; + + gd25lq128: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fixed-partitions"; + + partition@0 { + label = "bl2"; + reg = <0 0x100000>; + }; + + partition@100000 { + label = "fip1"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "fip2"; + reg = <0x500000 0x400000>; + }; + + partition@900000 { + label = "uboot-env"; + reg = <0x900000 0x10000>; + }; + + partition@910000 { + label = "fman-firmware"; + reg = <0x910000 0x200000>; + }; + + partition@a10000 { + label = "dtb"; + reg = <0xa10000 0x10000>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + spd@50 { + compatible = "spd"; + reg = <0x50>; + status = "okay"; + }; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + status = "okay"; + }; + + eeprom@57 { + compatible = "24c01"; + reg = <0x57>; + status = "okay"; + }; + + leds@62 { + compatible = "nxp,pca9633"; + reg = <0x62>; + status = "okay"; + }; + + rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + i2c-mux@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9546"; + reg = <0x70>; + status = "okay"; + + pcie0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sfp0_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sfp1_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + ext_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +#include "fsl-ls1046-post.dtsi" + +&fman0 { + ethernet@e4000 { + phy-handle = <&rgmii_phy0>; + phy-connection-type = "rgmii-id"; + status = "okay"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; + }; + + ethernet@e8000 { + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; + }; + + ethernet@ea000 { + phy-handle = <&sgmii_phy3>; + phy-connection-type = "sgmii"; + status = "okay"; + }; + + ethernet@f0000 { /* 10GEC1 */ + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "xgmii"; + status = "okay"; + }; + + ethernet@f2000 { /* 10GEC2 */ + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "xgmii"; + status = "okay"; + }; + + mdio@fc000 { + rgmii_phy0: ethernet-phy@1 { + reg = <0x1>; + }; + + rgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@3 { + reg = <0x3>; + }; + + sgmii_phy3: ethernet-phy@4 { + reg = <0x4>; + }; + }; +}; + +&duart0 { + status = "okay"; +}; diff --git a/board/conclusive/whle-ls1046a/Kconfig b/board/conclusive/whle-ls1046a/Kconfig new file mode 100644 index 000000000000..5778fbd5cd22 --- /dev/null +++ b/board/conclusive/whle-ls1046a/Kconfig @@ -0,0 +1,15 @@ +if TARGET_WHLE_LS1046A + +config SYS_BOARD + default "whle-ls1046a" + +config SYS_VENDOR + default "conclusive" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "whle_ls1046a" + +endif diff --git a/board/conclusive/whle-ls1046a/MAINTAINERS b/board/conclusive/whle-ls1046a/MAINTAINERS new file mode 100644 index 000000000000..1dcf067a06d8 --- /dev/null +++ b/board/conclusive/whle-ls1046a/MAINTAINERS @@ -0,0 +1,9 @@ +WHLE-LS1046A Board +M: Jakub Klama +M: Artur Rojek +S: Maintained +F: board/conclusive/whle-ls1046a +F: include/configs/whle_ls1046a.h +F: configs/whle_ls1046a_emmc_defconfig +F: configs/whle_ls1046a_qspi_defconfig +F: arch/arm/dts/fsl-ls1046a-whle.dts diff --git a/board/conclusive/whle-ls1046a/Makefile b/board/conclusive/whle-ls1046a/Makefile new file mode 100644 index 000000000000..9197ec93a6de --- /dev/null +++ b/board/conclusive/whle-ls1046a/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020-2023 Conclusive Engineering Sp. z o. o. + +obj-y += ddr.o +obj-y += whle-ls1046a.o +obj-$(CONFIG_NET) += eth.o diff --git a/board/conclusive/whle-ls1046a/ddr.c b/board/conclusive/whle-ls1046a/ddr.c new file mode 100644 index 000000000000..cbefc779d55d --- /dev/null +++ b/board/conclusive/whle-ls1046a/ddr.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/conclusive/whle-ls1046a/eth.c b/board/conclusive/whle-ls1046a/eth.c new file mode 100644 index 000000000000..05b83352b0ab --- /dev/null +++ b/board/conclusive/whle-ls1046a/eth.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2020-2023 Conclusive Engineering Sp. z o. o. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define RGMII_PHY1_ADDR 0x01 +#define RGMII_PHY2_ADDR 0x02 +#define SGMII_PHY3_ADDR 0x03 +#define SGMII_PHY4_ADDR 0x04 + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_controller *regs; + struct mii_dev *dev; + u32 srds; + struct ccsr_gur *gur = (struct ccsr_gur *)(CFG_SYS_FSL_GUTS_ADDR); + + srds = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (srds != 0x1133 && srds != 0x3333) + printf("Invalid SerDes protocol 0x%x for WHLE-LS1046A\n", srds); + + regs = (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + dtsec_mdio_info.regs = regs; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + /* RGMII on MAC 3 and 4, SGMII on MAC 5 and 6 */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY3_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY4_ADDR); + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(FM1_DTSEC3, dev); + fm_info_set_mdio(FM1_DTSEC4, dev); + fm_info_set_mdio(FM1_DTSEC5, dev); + fm_info_set_mdio(FM1_DTSEC6, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +#ifdef CONFIG_FMAN_ENET +int fdt_update_ethernet_dt(void *blob) +{ + return 0; +} +#endif diff --git a/board/conclusive/whle-ls1046a/whle-ls1046a.c b/board/conclusive/whle-ls1046a/whle-ls1046a.c new file mode 100644 index 000000000000..6b4bd149cdb2 --- /dev/null +++ b/board/conclusive/whle-ls1046a/whle-ls1046a.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * whle-ls1046a.c - Board init file for Conclusive WHLE-LS1046A board + * Copyright (C) 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BOARD_REV_MASK 0x0f +#define SPI_MCR_REG 0x2100000 + +/* Retimer */ +#define I2C_RETIMER_BUS 0 +#define I2C_RETIMER_ADDR 0x18 + +DECLARE_GLOBAL_DATA_PTR; + +static inline void set_spi_cs_signal_inactive(void) +{ + /* default: all CS signals inactive state is high */ + uint mcr_val; + uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | + DSPI_MCR_CRXF | DSPI_MCR_CTXF; + + mcr_val = in_be32(SPI_MCR_REG); + mcr_val |= DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); + out_be32(SPI_MCR_REG, mcr_cfg_val); + mcr_val = in_be32(SPI_MCR_REG); + mcr_val &= ~DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +static inline uint8_t get_board_version(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + + return in_be32(&gur->gpporcr1) & BOARD_REV_MASK; +} + +static int settings_r(void) +{ + serial_read_from_eeprom(0); + + return 0; +} +EVENT_SPY_SIMPLE(EVT_SETTINGS_R, settings_r); + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) +int checkboard(void) +{ + const char *serial_number = env_get("serial#"); + + printf("Board: WHLE-LS1046A, Rev: %s\n", + get_board_version() == 0x00 ? "0" : "unknown"); + + if (!serial_number) + printf("Warning: unknown serial number.\n"); + else + printf("S/N: %s\n", serial_number); + + return 0; +} +#endif + +static void board_retimer_init_rx(struct udevice *dev, int chnum) +{ + /* Select channel */ + dm_i2c_reg_write(dev, 0xff, chnum); + + /* Initialize receive channel */ + dm_i2c_reg_clrset(dev, 0x00, 0x04, 0x04); + dm_i2c_reg_clrset(dev, 0x0a, 0x0c, 0x0c); + dm_i2c_reg_clrset(dev, 0x2f, 0xf0, 0xc0); + dm_i2c_reg_clrset(dev, 0x31, 0x60, 0x00); + dm_i2c_reg_clrset(dev, 0x03, 0xff, 0x00); + dm_i2c_reg_clrset(dev, 0x3a, 0xff, 0x00); + dm_i2c_reg_clrset(dev, 0x40, 0xff, 0x00); + dm_i2c_reg_clrset(dev, 0x1e, 0x08, 0x08); + dm_i2c_reg_clrset(dev, 0x2d, 0x08, 0x08); + dm_i2c_reg_clrset(dev, 0x2d, 0x07, 0x02); + dm_i2c_reg_clrset(dev, 0x15, 0x47, 0x00); + dm_i2c_reg_clrset(dev, 0x0a, 0x0c, 0x00); +} + +static void board_retimer_init_tx(struct udevice *dev, int chnum) +{ + /* Select channel */ + dm_i2c_reg_write(dev, 0xff, chnum); + + /* Initialize transmit channel */ + dm_i2c_reg_clrset(dev, 0x00, 0x04, 0x04); + dm_i2c_reg_clrset(dev, 0x0a, 0x0c, 0x0c); + dm_i2c_reg_clrset(dev, 0x2f, 0xf0, 0xc0); + dm_i2c_reg_clrset(dev, 0x31, 0x20, 0x20); + dm_i2c_reg_clrset(dev, 0x3a, 0xff, 0x00); + dm_i2c_reg_clrset(dev, 0x1e, 0x08, 0x08); + dm_i2c_reg_clrset(dev, 0x2d, 0x07, 0x00); + dm_i2c_reg_clrset(dev, 0x15, 0x47, 0x00); + dm_i2c_reg_clrset(dev, 0x0a, 0x0c, 0x00); +} + +static void board_retimer_init(void) +{ + struct udevice *dev; + + i2c_get_chip_for_busnum(I2C_RETIMER_BUS, I2C_RETIMER_ADDR, 1, &dev); + board_retimer_init_tx(dev, 0x04); + board_retimer_init_rx(dev, 0x05); + board_retimer_init_tx(dev, 0x06); + board_retimer_init_rx(dev, 0x07); +} + +int board_init(void) +{ +#ifdef CONFIG_NXP_ESBC + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + + board_retimer_init(); + return 0; +} + +int board_setup_core_volt(u32 vdd) +{ + return 0; +} + +static void board_config_mux(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + + /* Configure IRQ01 and IRQ02 lines polarity to negated */ + out_be32(&scfg->intpcr, 0x60000000); + + /* + * IIC3 is used, configure mux to IIC3_SCL/IIC3/SDA + * IIC4 is not used, configure mux to USB3_DRVVBUS/USB3_PWRFAULT + */ + out_be32(&scfg->rcwpmuxcr0, 0x0033); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); + set_spi_cs_signal_inactive(); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + board_config_mux(); + return 0; +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + fdt_fixup_icid(blob); + + return 0; +} diff --git a/board/conclusive/whle-ls1046a/whle-ls1046a.env b/board/conclusive/whle-ls1046a/whle-ls1046a.env new file mode 100644 index 000000000000..fd82a9a6b1d8 --- /dev/null +++ b/board/conclusive/whle-ls1046a/whle-ls1046a.env @@ -0,0 +1,13 @@ +hwconfig=fsl_ddr:bank_intlv=auto +kernel_addr_r=0x81000000 +kernel_size=0x07000000 +kernel_comp_addr_r=0x88000000 +kernel_comp_size=0x04000000 +ramdisk_addr_r=0x90000000 +ramdisk_size=0x08000000 +fdt_addr_r=0x98000000 +pxefile_addr_r=0x99000000 +scriptaddr=0x9a000000 +fdtfile=fsl-ls1046a-whle.dtb +console=ttyS0,115200 +fsl_bootcmd_mcinitcmd_set=y diff --git a/configs/whle_ls1046a_emmc_defconfig b/configs/whle_ls1046a_emmc_defconfig new file mode 100644 index 000000000000..a3104b0023e9 --- /dev/null +++ b/configs/whle_ls1046a_emmc_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=25000000 +CONFIG_TARGET_WHLE_LS1046A=y +CONFIG_TFABOOT=y +CONFIG_TEXT_BASE=0x82000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-whle" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_PCI=y +CONFIG_AHCI=y +CONFIG_MP=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_BOOTCOMMAND=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=10 +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p1 earlycon=uart8250,mmio,0x21c0500" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_CMD_TLV_EEPROM=y +CONFIG_CMD_BOOTMENU=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_EXT4=y +CONFIG_ENV_EXT4_INTERFACE="mmc" +CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1" +CONFIG_ENV_EXT4_FILE="/boot/uboot.env" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="fm1-mac3" +CONFIG_FSL_CAAM=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_EEPROM=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_FIXED=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_NVME_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_SYS_QE_FMAN_FW_IN_MMC=y +CONFIG_DM_SCSI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/whle_ls1046a_qspi_defconfig b/configs/whle_ls1046a_qspi_defconfig new file mode 100644 index 000000000000..7d6a6ba50eaf --- /dev/null +++ b/configs/whle_ls1046a_qspi_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=25000000 +CONFIG_TARGET_WHLE_LS1046A=y +CONFIG_TFABOOT=y +CONFIG_TEXT_BASE=0x82000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x900000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-whle" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_PCI=y +CONFIG_AHCI=y +CONFIG_MP=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_BOOTCOMMAND=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=10 +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p1 earlycon=uart8250,mmio,0x21c0500" +CONFIG_BOOTCOMMAND="sf probe; mtd read dtb $fdt_addr_r; bootflow scan -lb" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_CMD_TLV_EEPROM=y +CONFIG_CMD_BOOTMENU=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="fm1-mac3" +CONFIG_FSL_CAAM=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_EEPROM=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_FIXED=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x910000 +CONFIG_NVME_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y +CONFIG_DM_SCSI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/include/configs/whle_ls1046a.h b/include/configs/whle_ls1046a.h new file mode 100644 index 000000000000..597d1b274940 --- /dev/null +++ b/include/configs/whle_ls1046a.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019-2020 NXP + * Copyright 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +#ifndef __WHLE_LS1046A_H__ +#define __WHLE_LS1046A_H__ + +#include +#include +#include + +#define CFG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* Serial Port */ +#define CFG_SYS_NS16550_CLK (get_serial_clock()) + +/* Miscellaneous configurable options */ +#define HWCONFIG_BUFFER_SIZE 128 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/ + +/* RTC */ +#define RTC +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CFG_SYS_RTC_BUS_NUM 0 + +/* FMan */ +#ifdef CONFIG_FMAN_ENET +#define CFG_SYS_FM_MURAM_SIZE 0x60000 +#define FDT_SEQ_MACADDR_FROM_ENV +#endif + +/* TF-A */ +#define QSPI_NOR_BOOTCOMMAND CONFIG_BOOTCOMMAND +#define QSPI_NAND_BOOTCOMMAND CONFIG_BOOTCOMMAND +#define SD_BOOTCOMMAND CONFIG_BOOTCOMMAND + +#endif /* __WHLE_LS1046A_H__ */ From patchwork Tue Nov 28 10:34:57 2023 Content-Type: text/plain; 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[93.179.209.131]) by smtp.gmail.com with ESMTPSA id cw16-20020a170907161000b00a169550fccesm77558ejd.111.2023.11.28.02.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 02:35:53 -0800 (PST) From: Artur Rojek To: Peng Fan , "NXP i . MX U-Boot Team" , Simon Glass , Jakub Klama , Tom Rini Cc: Wojciech Kloska , =?utf-8?q?Rados=C5=82aw_Adamcz?= =?utf-8?q?yk?= , u-boot@lists.denx.de, Artur Rojek Subject: [PATCH v3 3/3] board: Add support for Conclusive WHLE-LS1088A Date: Tue, 28 Nov 2023 11:34:57 +0100 Message-ID: <20231128103457.45802-4-artur@conclusive.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231128103457.45802-1-artur@conclusive.pl> References: <20231128103457.45802-1-artur@conclusive.pl> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Introduce support for Conclusive WHLE-LS1088A Single Board Computer. Co-developed-by: Jakub Klama Signed-off-by: Jakub Klama Signed-off-by: Artur Rojek --- v3: new patch arch/arm/Kconfig | 19 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1088a-whle-u-boot.dtsi | 8 + arch/arm/dts/fsl-ls1088a-whle.dts | 235 ++++++++++++++ board/conclusive/whle-ls1088a/Kconfig | 29 ++ board/conclusive/whle-ls1088a/MAINTAINERS | 11 + board/conclusive/whle-ls1088a/Makefile | 7 + board/conclusive/whle-ls1088a/ddr.c | 134 ++++++++ board/conclusive/whle-ls1088a/ddr.h | 47 +++ board/conclusive/whle-ls1088a/eth.c | 13 + board/conclusive/whle-ls1088a/whle-ls1088a.c | 301 ++++++++++++++++++ .../conclusive/whle-ls1088a/whle-ls1088a.env | 13 + configs/whle_ls1088a_emmc_defconfig | 84 +++++ configs/whle_ls1088a_qspi_defconfig | 84 +++++ include/configs/whle_ls1088a.h | 92 ++++++ 15 files changed, 1078 insertions(+) create mode 100644 arch/arm/dts/fsl-ls1088a-whle-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-whle.dts create mode 100644 board/conclusive/whle-ls1088a/Kconfig create mode 100644 board/conclusive/whle-ls1088a/MAINTAINERS create mode 100644 board/conclusive/whle-ls1088a/Makefile create mode 100644 board/conclusive/whle-ls1088a/ddr.c create mode 100644 board/conclusive/whle-ls1088a/ddr.h create mode 100644 board/conclusive/whle-ls1088a/eth.c create mode 100644 board/conclusive/whle-ls1088a/whle-ls1088a.c create mode 100644 board/conclusive/whle-ls1088a/whle-ls1088a.env create mode 100644 configs/whle_ls1088a_emmc_defconfig create mode 100644 configs/whle_ls1088a_qspi_defconfig create mode 100644 include/configs/whle_ls1088a.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 609571e6e421..cd53fcaac883 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1869,6 +1869,24 @@ config TARGET_WHLE_LS1046A Layerscape Architecture processor: https://conclusive.tech/products/whle-ls1-sbc/ +config TARGET_WHLE_LS1088A + bool "Support Conclusive WHLE-LS1088A" + select ARCH_LS1088A + select ARM64 + select ARMV8_MULTIENTRY + select ARCH_SUPPORT_TFABOOT + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER + select DM_SPI_FLASH if DM_SPI + imply SCSI + help + Support for Conclusive WHLE-LS1088A platform. + The WHLE-LS1088A is a high-performance Single Board Computer with + extensive connectivity features that supports the QorIQ LS1088A + Layerscape Architecture processor: + https://conclusive.tech/products/whle-ls1-sbc/ + config TARGET_TEN64 bool "Support ten64" select ARCH_LS1088A @@ -2318,6 +2336,7 @@ source "board/broadcom/bcmns/Kconfig" source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/conclusive/whle-ls1046a/Kconfig" +source "board/conclusive/whle-ls1088a/Kconfig" source "board/eets/pdu001/Kconfig" source "board/emulation/qemu-arm/Kconfig" source "board/freescale/ls2080aqds/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8dcbf29df363..b0782b4f29bc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -591,6 +591,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls1088a-qds.dtb \ fsl-ls1088a-qds-21-x.dtb \ fsl-ls1088a-qds-29-x.dtb \ + fsl-ls1088a-whle.dtb \ fsl-ls1028a-rdb.dtb \ fsl-ls1028a-qds-duart.dtb \ fsl-ls1028a-qds-lpuart.dtb \ diff --git a/arch/arm/dts/fsl-ls1088a-whle-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-whle-u-boot.dtsi new file mode 100644 index 000000000000..bbe93a1d6e4f --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-whle-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +#include + +#include "fsl-ls1088a-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1088a-whle.dts b/arch/arm/dts/fsl-ls1088a-whle.dts new file mode 100644 index 000000000000..76ef1c748059 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-whle.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +/dts-v1/; + +#include "fsl-ls1088a.dtsi" + +/ { + model = "Conclusive WHLE-LS1088A"; + compatible = "conclusive,whle-ls1088a", "fsl,ls1088a"; + + chosen { + stdout-path = &duart0; + }; + + aliases { + spi0 = &qspi; + }; +}; + +&dpmac1 { + status = "okay"; + phy-connection-type = "10gbase-r"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "10gbase-r"; +}; + +&dpmac3 { + status = "okay"; + phy-handle = <&sgmii_phy3>; + phy-connection-type = "sgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&rgmii_phy0>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac6 { + status = "disabled"; +}; + +&dpmac7 { + status = "okay"; + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; +}; + +&dpmac8 { + status = "disabled"; +}; + +&dpmac9 { + status = "disabled"; +}; + +&dpmac10 { + status = "disabled"; +}; + +&emdio1 { + status = "okay"; + + rgmii_phy0: ethernet-phy@1 { + reg = <0x1>; + }; + + rgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@3 { + reg = <0x3>; + }; + + sgmii_phy3: ethernet-phy@4 { + reg = <0x4>; + }; +}; + +&i2c0 { + status = "okay"; + + spd@50 { + compatible = "spd"; + reg = <0x50>; + status = "okay"; + }; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + status = "okay"; + }; + + eeprom@57 { + compatible = "24c01"; + reg = <0x57>; + status = "okay"; + }; + + leds@62 { + compatible = "nxp,pca9633"; + reg = <0x62>; + status = "okay"; + }; + + rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + i2c-mux@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9546"; + reg = <0x70>; + status = "okay"; + + pcie0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sfp0_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sfp1_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + ext_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&qspi { + status = "okay"; + + gd25lq128: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fixed-partitions"; + + partition@0 { + label = "bl2"; + reg = <0 0x100000>; + }; + + partition@100000 { + label = "fip1"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "fip2"; + reg = <0x500000 0x400000>; + }; + + partition@900000 { + label = "uboot-env"; + reg = <0x900000 0x10000>; + }; + + partition@910000 { + label = "mc-firmware"; + reg = <0x910000 0x200000>; + }; + + partition@b10000 { + label = "dpc"; + reg = <0xb10000 0x10000>; + }; + + partition@b20000 { + label = "dpl"; + reg = <0xb20000 0x10000>; + }; + + partition@b30000 { + label = "dtb"; + reg = <0xb30000 0x10000>; + }; + }; + }; +}; + +&esdhc { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; diff --git a/board/conclusive/whle-ls1088a/Kconfig b/board/conclusive/whle-ls1088a/Kconfig new file mode 100644 index 000000000000..3111ccc84e0c --- /dev/null +++ b/board/conclusive/whle-ls1088a/Kconfig @@ -0,0 +1,29 @@ +if TARGET_WHLE_LS1088A + +config SYS_BOARD + default "whle-ls1088a" + +config SYS_VENDOR + default "conclusive" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "whle_ls1088a" + +if FSL_LS_PPA +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP + default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND + +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA Firmware HDR Addr" + default 0x20680000 if SYS_LS_PPA_FW_IN_XIP + default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND +endif +endif + +endif diff --git a/board/conclusive/whle-ls1088a/MAINTAINERS b/board/conclusive/whle-ls1088a/MAINTAINERS new file mode 100644 index 000000000000..49a3c5616969 --- /dev/null +++ b/board/conclusive/whle-ls1088a/MAINTAINERS @@ -0,0 +1,11 @@ +WHLE-LS1088A Board +M: Jakub Klama +M: Artur Rojek +S: Maintained +F: board/conclusive/whle-ls1088a +F: include/configs/whle-ls1088a.h +F: configs/whle_ls1088a_emmc_defconfig +F: configs/whle_ls1088a_qspi_defconfig +F: arch/arm/dts/fsl-ls1088a-whle.dts +F: arch/arm/dts/fsl-ls1088a-whle-u-boot.dtsi + diff --git a/board/conclusive/whle-ls1088a/Makefile b/board/conclusive/whle-ls1088a/Makefile new file mode 100644 index 000000000000..9c37d961c433 --- /dev/null +++ b/board/conclusive/whle-ls1088a/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020-2023 Conclusive Engineering Sp. z o. o. + +obj-y += whle-ls1088a.o +obj-y += eth.o +obj-y += ddr.o diff --git a/board/conclusive/whle-ls1088a/ddr.c b/board/conclusive/whle-ls1088a/ddr.c new file mode 100644 index 000000000000..be0f9669177c --- /dev/null +++ b/board/conclusive/whle-ls1088a/ddr.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 NXP + * Copyright (C) 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) +{ + int vdd; + + vdd = get_core_volt_from_fuse(); + if (vdd < 0) + return; + + if (vdd == 900) { + popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN; + debug("VID: configure DDR to support 900 mV\n"); + } +} +#endif + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * frequency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (!pbsp_highest) + panic("DIMM is not supported by this board"); + + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + popts->half_strength_driver_enable = 0; + + /* Write leveling override */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* Enable DDR hashing */ + popts->addr_hash = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + fsl_ddr_setup_0v9_volt(popts); +#endif + + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; +} + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else +int fsl_initdram(void) +{ + puts("Initializing DDR....using SPD\n"); + +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + gd->ram_size = fsl_ddr_sdram_size(); +#else + gd->ram_size = fsl_ddr_sdram(); +#endif + return 0; +} +#endif /* CONFIG_TFABOOT */ diff --git a/board/conclusive/whle-ls1088a/ddr.h b/board/conclusive/whle-ls1088a/ddr.h new file mode 100644 index 000000000000..462c5cfe6b06 --- /dev/null +++ b/board/conclusive/whle-ls1088a/ddr.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __LS1088A_DDR_H__ +#define __LS1088A_DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ +#if defined(CONFIG_TARGET_LS1088ARDB) + {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,}, + {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,}, + {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,}, + {} +#elif defined(CONFIG_TARGET_LS1088AQDS) + {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,}, + {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,}, + {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,}, + {} + +#endif +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/conclusive/whle-ls1088a/eth.c b/board/conclusive/whle-ls1088a/eth.c new file mode 100644 index 000000000000..fb6f9c1a813f --- /dev/null +++ b/board/conclusive/whle-ls1088a/eth.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +#include + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ + mc_env_boot(); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/conclusive/whle-ls1088a/whle-ls1088a.c b/board/conclusive/whle-ls1088a/whle-ls1088a.c new file mode 100644 index 000000000000..dab367f85145 --- /dev/null +++ b/board/conclusive/whle-ls1088a/whle-ls1088a.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * whle-ls1088a.c - Board init file for Conclusive WHLE-LS1088A board + * Copyright (C) 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BOARD_REV_MASK 0x0f + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + fsl_lsch3_early_init_f(); + return 0; +} + +static inline uint8_t get_board_version(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + + return in_be32(&gur->gpporcr1) & BOARD_REV_MASK; +} + +static int settings_r(void) +{ + serial_read_from_eeprom(0); + + return 0; +} +EVENT_SPY_SIMPLE(EVT_SETTINGS_R, settings_r); + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) +int checkboard(void) +{ + const char *serial_number = env_get("serial#"); + + printf("Board: WHLE-LS1088A, Rev: %s\n", + get_board_version() == 0x00 ? "0" : "unknown"); + + if (!serial_number) + printf("Warning: unknown serial number.\n"); + else + printf("S/N: %s\n", serial_number); + + return 0; +} +#endif + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + return 0; +} +#endif + +#if !defined(CONFIG_SPL_BUILD) +int board_init(void) +{ +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) + pci_init(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR: "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +} + +#ifdef CONFIG_FSL_MC_ENET +void board_quiesce_devices(void) +{ + fsl_mc_ldpaa_exit(gd->bd); +} + +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/fsl-mc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); + + if (offset < 0) { + printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) + fdt_status_okay(fdt, offset); + else + fdt_status_fail(fdt, offset); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +void fsl_fdt_fixup_flash(void *fdt) +{ + int offset; +#ifdef CONFIG_TFABOOT + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 val; +#endif + +/* + * IFC-NOR and QSPI are muxed on SoC. + * So disable IFC node in dts if QSPI is enabled or + * disable QSPI node in dts in case QSPI is not enabled. + */ + +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); + bool disable_ifc = false; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + disable_ifc = false; + break; + case BOOT_SOURCE_QSPI_NOR: + disable_ifc = true; + break; + default: + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & 0x3)) + disable_ifc = true; + break; + } + + if (disable_ifc) { + offset = fdt_path_offset(fdt, "/soc/ifc/nor"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/ifc/nor"); + } else { + offset = fdt_path_offset(fdt, "/soc/quadspi"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/quadspi"); + } + +#else +#ifdef CONFIG_FSL_QSPI + offset = fdt_path_offset(fdt, "/soc/ifc/nor"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/ifc/nor"); +#else + offset = fdt_path_offset(fdt, "/soc/quadspi"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/quadspi"); +#endif +#endif + if (offset < 0) + return; + + fdt_status_disabled(fdt, offset); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u16 total_memory_banks, mc_memory_bank = 0; + u64 *base, *size, mc_memory_base = 0, mc_memory_size = 0; + int i; + + ft_cpu_setup(blob, bd); + + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + + /* fixup DT for the two GPP DDR banks */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); + + fdt_fsl_mc_fixup_iommu_map_entry(blob); + + fsl_fdt_fixup_flash(blob); + +#ifdef CONFIG_FSL_MC_ENET + fdt_fixup_board_enet(blob); +#endif + + fdt_fixup_icid(blob); + + return 0; +} +#endif +#endif /* !defined(CONFIG_SPL_BUILD) */ + +#ifdef CONFIG_TFABOOT +#ifdef CONFIG_MTD_NOR_FLASH +int is_flash_available(void) +{ + char *env_hwconfig = env_get("hwconfig"); + enum boot_src src = get_boot_src(); + int is_nor_flash_available = 1; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + is_nor_flash_available = 1; + break; + case BOOT_SOURCE_QSPI_NOR: + is_nor_flash_available = 0; + break; + /* + * In Case of SD boot,if qspi is defined in env_hwconfig + * disable nor flash probe. + */ + default: + if (hwconfig_f("qspi", env_hwconfig)) + is_nor_flash_available = 0; + break; + } + return is_nor_flash_available; +} +#endif + +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +void *env_sf_get_env_addr(void) +{ + return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif +#endif diff --git a/board/conclusive/whle-ls1088a/whle-ls1088a.env b/board/conclusive/whle-ls1088a/whle-ls1088a.env new file mode 100644 index 000000000000..f48d4800f3a0 --- /dev/null +++ b/board/conclusive/whle-ls1088a/whle-ls1088a.env @@ -0,0 +1,13 @@ +hwconfig=fsl_ddr:bank_intlv=auto +kernel_addr_r=0x81000000 +kernel_size=0x07000000 +kernel_comp_addr_r=0x88000000 +kernel_comp_size=0x04000000 +ramdisk_addr_r=0x90000000 +ramdisk_size=0x08000000 +fdt_addr_r=0x98000000 +pxefile_addr_r=0x99000000 +scriptaddr=0x9a000000 +fdtfile=fsl-ls1088a-whle.dtb +console=ttyS0,115200 +mcmemsize=0x70000000 diff --git a/configs/whle_ls1088a_emmc_defconfig b/configs/whle_ls1088a_emmc_defconfig new file mode 100644 index 000000000000..a7b2744b8639 --- /dev/null +++ b/configs/whle_ls1088a_emmc_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_TARGET_WHLE_LS1088A=y +CONFIG_TFABOOT=y +CONFIG_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_LEN=0x202000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-whle" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_PCI=y +CONFIG_AHCI=y +CONFIG_REMAKE_ELF=y +CONFIG_MP=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_BOOTCOMMAND=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=10 +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p1 earlycon=uart8250,mmio,0x21c0500" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_RESET_PHY_R=y +CONFIG_CMD_TLV_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_EXT4=y +CONFIG_ENV_EXT4_INTERFACE="mmc" +CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1" +CONFIG_ENV_EXT4_FILE="/boot/uboot.env" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="DPMAC4@rgmii-id" +CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_EEPROM=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y +CONFIG_DM_MDIO_MUX=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_MII=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_NVME_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/whle_ls1088a_qspi_defconfig b/configs/whle_ls1088a_qspi_defconfig new file mode 100644 index 000000000000..cfde387a4068 --- /dev/null +++ b/configs/whle_ls1088a_qspi_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_TARGET_WHLE_LS1088A=y +CONFIG_TFABOOT=y +CONFIG_TEXT_BASE=0x82000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x900000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-whle" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_PCI=y +CONFIG_AHCI=y +CONFIG_REMAKE_ELF=y +CONFIG_MP=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_BOOTCOMMAND=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=10 +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p1 earlycon=uart8250,mmio,0x21c0500" +CONFIG_BOOTCOMMAND="sf probe; mtd read dtb $fdt_addr_r; bootflow scan -lb" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_RESET_PHY_R=y +CONFIG_CMD_TLV_EEPROM=y +CONFIG_CMD_BOOTMENU=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="DPMAC4@rgmii-id" +CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_EEPROM=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y +CONFIG_DM_MDIO_MUX=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/include/configs/whle_ls1088a.h b/include/configs/whle_ls1088a.h new file mode 100644 index 000000000000..260643b4447d --- /dev/null +++ b/include/configs/whle_ls1088a.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020-2023 Conclusive Engineering Sp. z o. o. + */ + +#ifndef __WHLE_LS1088A_H__ +#define __WHLE_LS1088A_H__ + +#include +#include +#include + +/* Link Definitions */ +#define CFG_SYS_FSL_QSPI_BASE 0x20000000 + +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_addr + +#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ +#define SPD_EEPROM_ADDRESS 0x50 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define PWM_CHANNEL0 0x0 + +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +/* Serial Port */ +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + +#define HWCONFIG_BUFFER_SIZE 128 + +/* RTC configuration */ +#ifndef SPL_NO_RTC +#define RTC +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#endif + +/* TF-A */ +#define QSPI_NOR_BOOTCOMMAND CONFIG_BOOTCOMMAND +#define QSPI_NAND_BOOTCOMMAND CONFIG_BOOTCOMMAND +#define SD_BOOTCOMMAND CONFIG_BOOTCOMMAND + +/* + * Carve out a DDR region which will not be used by u-boot/Linux + * + * It will be used by MC and Debug Server. The MC region must be + * 512MB aligned, so the min size to hide is 512MB. + */ + +#ifdef CONFIG_FSL_MC_ENET +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#endif + +/* MC firmware */ +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) + +#define RESERVED_MC_INIT_CMD \ + "fsl_mc start mc 0x83000000 0x84000000 && " \ + "fsl_mc lazyapply DPL 0x85000000\0" + +#define QSPI_MC_INIT_CMD \ + "sf probe; " \ + "mtd read mc-firmware 0x83000000; " \ + "mtd read dpc 0x84000000; " \ + "mtd read dpl 0x85000000; " \ + "fsl_mc start mc 0x83000000 0x84000000 && " \ + "fsl_mc lazyapply DPL 0x85000000\0" + +#define SD_MC_INIT_CMD \ + "mmcinfo;" \ + "mmc read 0x83000000 0x5000 0x2000 && " \ + "mmc read 0x84000000 0x7000 0x100 && " \ + "mmc read 0x85000000 0x6800 0x100 && " \ + "fsl_mc start mc 0x83000000 0x84000000 && " \ + "fsl_mc lazyapply DPL 0x85000000\0" + +#include + +#endif /* __WHLE_LS1088A_H__ */