From patchwork Mon Nov 27 17:08:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=hq6fvtv1; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBsb2Wm0z23m6 for ; Tue, 28 Nov 2023 04:09:55 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f5y-0007Q6-VR; Mon, 27 Nov 2023 12:08:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f5x-0007PX-63 for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:29 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f5v-0004cW-DA for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:28 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40b31232bf0so36333965e9.1 for ; Mon, 27 Nov 2023 09:08:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104906; x=1701709706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EExjjsQKHG4G/S0rA+HN9RE1Zx7xegOtzNg+8uLL5Ts=; b=hq6fvtv1SK0VBy7Fusz3pDg5T3lp1xjf6jBXHXnue4YQvZkFP5AYLhlDrts8SHV75M mBAArYibyVZUUkkkdX2U8qaM3zQuOCf08hmrvCaboenyY9u6RtMCJBdpugeWRaUKQmog 2FGg4gi9Y9UwWRa22oJ5rjrT98F/nxABa5v7te/TaLQEInPKaunvrmCIioLqdRHM3f5o v7/NOTUqkAuYOmw9BGGp6TvxO1J5zZ9XHfulfy3IOlRd7kdZyObsW8Gw97ViS4pNPktq JyaDm5ojbkh/SJXSGDUnYfcJ8qawBCCxUJHo8qnQgtnuEfoVOiIb1cQKgN8tYz/y+ctV udbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104906; x=1701709706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EExjjsQKHG4G/S0rA+HN9RE1Zx7xegOtzNg+8uLL5Ts=; b=gIS4frkWrqGOG2HYWPtqMbBLXx9aJ0uNOCNuCHsFDzwPDdRfUWMchwPnVT+yD52Pap Tj3U52PGigy3zb2yknE/gpBdGuo4VxdRq3rfZOMy+kJIzuPTs0mVFBBUnCIzM8ZTvPdO F+tFb78Wfc4YJpuzenVChMbW5Oy3S74Uq1NRBUKm0vmIw/IsKA7NjDP5jGJ7858BdHxa uOWwsxJcDgh3jLLyU0bj+Bt4n6BtxxVTTC6Sc02a2ywolvjg1yisQ9kv84p1WQcAezWq cux6nogDXhVAJ4EIKBMQs3F0CTQj1tcT7bmN+tBWPGYiol1k7EPjPcz2cA6xs8YL/3lv s2Uw== X-Gm-Message-State: AOJu0YwfjRavi+1M1LMQb72ZY7KGLJDVfQmIGvSUkMvcdJpzr3nuS4Ns SW9V3UcwCd8GE+MRJQjy1tjEsd+RNucyOaS9Adw= X-Google-Smtp-Source: AGHT+IGrkzCb6cqK4LFhDn7anN1mQBj3I2Twky5WOJXBLkRQPJOCodKD1DPWbr/D2kvyBN8HLwIuFQ== X-Received: by 2002:a05:600c:35d3:b0:40b:3d8a:ed34 with SMTP id r19-20020a05600c35d300b0040b3d8aed34mr7516386wmq.13.1701104905978; Mon, 27 Nov 2023 09:08:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/13] target/arm: Set IL bit for pauth, SVE access, BTI trap syndromes Date: Mon, 27 Nov 2023 17:08:11 +0000 Message-Id: <20231127170823.589863-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The syndrome register value always has an IL field at bit 25, which is 0 for a trap on a 16 bit instruction, and 1 for a trap on a 32 bit instruction (or for exceptions which aren't traps on a known instruction, like PC alignment faults). This means that our syn_*() functions should always either take an is_16bit argument to determine whether to set the IL bit, or else unconditionally set it. We missed setting the IL bit for the syndrome for three kinds of trap: * an SVE access exception * a pointer authentication check failure * a BTI (branch target identification) check failure All of these traps are AArch64 only, and so the instruction causing the trap is always 64 bit. This means we can unconditionally set the IL bit in the syn_*() function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20231120150121.3458408-1-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell --- target/arm/syndrome.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 5d34755508d..95454b5b3bb 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -216,7 +216,7 @@ static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) static inline uint32_t syn_sve_access_trap(void) { - return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; + return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; } /* @@ -242,12 +242,12 @@ static inline uint32_t syn_pacfail(bool data, int keynumber) static inline uint32_t syn_pactrap(void) { - return EC_PACTRAP << ARM_EL_EC_SHIFT; + return (EC_PACTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; } static inline uint32_t syn_btitrap(int btype) { - return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | btype; } static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) From patchwork Mon Nov 27 17:08:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868897 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=FWPtGN+p; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBwT0pLjz1yS6 for ; Tue, 28 Nov 2023 04:12:25 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f6A-0007UG-8H; Mon, 27 Nov 2023 12:08:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f5z-0007QH-2n for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:31 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f5v-0004cZ-On for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:30 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40b2ddab817so31258545e9.3 for ; Mon, 27 Nov 2023 09:08:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104906; x=1701709706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uLt/J0Ekf4tgAJYBqplW3Dr2IyBfScT1SQCm++J6lI4=; b=FWPtGN+pb4zP0LpUcu8m9G2ih80Y30110LIvXt1ywNq2v8M50KIIyXrfh6megmc8hg 7qanZfa8GhC08CVD5f3H7Vh6l8WlfbRLxyxBc2HZSQ0Qcu1kbF+KLjLfP6NB/4e1+bFS xEV3qA5S6lSEbo98cRb6qgFez6kBVudI7W83bGl8BAV35yEGAnkTt+QKFhRLKOjz8DlY bxfSvyLkzkTKPI/WiCui7vSXCU2x1an8Y2+o+XPzZPue2G3VpR+8yNO9iXXCAer8IwTV ccYPaxM8b3tAjrIVPoD0+Fs48+36gJGBmu9tn7tI5F9bZcltRGn7dn2kA7sczWRyrsaw /9uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104906; x=1701709706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uLt/J0Ekf4tgAJYBqplW3Dr2IyBfScT1SQCm++J6lI4=; b=XUJW1V0E0pJSbk+cOKbH6rnhQc757eNmnEo3hHAp5M9Jk8os74gqPYjWarTSG2lFdc T+y7iwsGAiAJzEW8RUYWRVQZmRCuQBjflk2NCHPsE63beW2nRuh41g3w8hh1rKjt1cHY RXUcPTzDXQi0XTq69uhfdHAYx4tdbogCs5NqpscAGnBe2JCNSNdAaJxabr6mogvuVyRV c+G4r923IwkDqNJm9ptTdilE92R5YmhXQATkoTyi1xd7i6TubiceJb/Km1nBBLb0dDbJ AVeFdjhr2GJ16jx+d1LIG6PAFxXtMMJ0rSOlP7VeUBdbSsl4mKTpdj8MMLJcO1whVdvS JN1Q== X-Gm-Message-State: AOJu0YxxI0a1jGfnzpsSBgmNK4/uRZ4mOu/ZxQr9y9A+zOsmMlgbn+ZN ZYBPE7h6HeoUX9jdfHijRF3BP3ySYH1ADUPzVBs= X-Google-Smtp-Source: AGHT+IHcgrmjIEXdC5J2hQ3icXSPQEWbEWIR1hli3JpXcwoXiq0pqKfGHUTun0s4NmCQtPCFXLbXgA== X-Received: by 2002:a05:600c:3ca0:b0:40a:48af:4820 with SMTP id bg32-20020a05600c3ca000b0040a48af4820mr5690786wmb.30.1701104906387; Mon, 27 Nov 2023 09:08:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/13] target/arm: Handle overflow in calculation of next timer tick Date: Mon, 27 Nov 2023 17:08:12 +0000 Message-Id: <20231127170823.589863-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In commit edac4d8a168 back in 2015 when we added support for the virtual timer offset CNTVOFF_EL2, we didn't correctly update the timer-recalculation code that figures out when the timer interrupt is next going to change state. We got it wrong in two ways: * for the 0->1 transition, we didn't notice that gt->cval + offset can overflow a uint64_t * for the 1->0 transition, we didn't notice that the transition might now happen before the count rolls over, if offset > count In the former case, we end up trying to set the next interrupt for a time in the past, which results in QEMU hanging as the timer fires continuously. In the latter case, we would fail to update the interrupt status when we are supposed to. Fix the calculations in both cases. The test case is Alex Bennée's from the bug report, and tests the 0->1 transition overflow case. Fixes: edac4d8a168 ("target-arm: Add CNTVOFF_EL2") Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/60 Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20231120173506.3729884-1-peter.maydell@linaro.org Reviewed-by: Peter Maydell --- target/arm/helper.c | 25 ++++++++++-- tests/tcg/aarch64/system/vtimer.c | 48 +++++++++++++++++++++++ tests/tcg/aarch64/Makefile.softmmu-target | 7 +++- 3 files changed, 75 insertions(+), 5 deletions(-) create mode 100644 tests/tcg/aarch64/system/vtimer.c diff --git a/target/arm/helper.c b/target/arm/helper.c index ff1970981ee..2746d3fdac8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2646,11 +2646,28 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) gt->ctl = deposit32(gt->ctl, 2, 1, istatus); if (istatus) { - /* Next transition is when count rolls back over to zero */ - nexttick = UINT64_MAX; + /* + * Next transition is when (count - offset) rolls back over to 0. + * If offset > count then this is when count == offset; + * if offset <= count then this is when count == offset + 2^64 + * For the latter case we set nexttick to an "as far in future + * as possible" value and let the code below handle it. + */ + if (offset > count) { + nexttick = offset; + } else { + nexttick = UINT64_MAX; + } } else { - /* Next transition is when we hit cval */ - nexttick = gt->cval + offset; + /* + * Next transition is when (count - offset) == cval, i.e. + * when count == (cval + offset). + * If that would overflow, then again we set up the next interrupt + * for "as far in the future as possible" for the code below. + */ + if (uadd64_overflow(gt->cval, offset, &nexttick)) { + nexttick = UINT64_MAX; + } } /* * Note that the desired next expiry time might be beyond the diff --git a/tests/tcg/aarch64/system/vtimer.c b/tests/tcg/aarch64/system/vtimer.c new file mode 100644 index 00000000000..42f2f7796c7 --- /dev/null +++ b/tests/tcg/aarch64/system/vtimer.c @@ -0,0 +1,48 @@ +/* + * Simple Virtual Timer Test + * + * Copyright (c) 2020 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +/* grabbed from Linux */ +#define __stringify_1(x...) #x +#define __stringify(x...) __stringify_1(x) + +#define read_sysreg(r) ({ \ + uint64_t __val; \ + asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ + __val; \ +}) + +#define write_sysreg(r, v) do { \ + uint64_t __val = (uint64_t)(v); \ + asm volatile("msr " __stringify(r) ", %x0" \ + : : "rZ" (__val)); \ +} while (0) + +int main(void) +{ + int i; + + ml_printf("VTimer Test\n"); + + write_sysreg(cntvoff_el2, 1); + write_sysreg(cntv_cval_el0, -1); + write_sysreg(cntv_ctl_el0, 1); + + ml_printf("cntvoff_el2=%lx\n", read_sysreg(cntvoff_el2)); + ml_printf("cntv_cval_el0=%lx\n", read_sysreg(cntv_cval_el0)); + ml_printf("cntv_ctl_el0=%lx\n", read_sysreg(cntv_ctl_el0)); + + /* Now read cval a few times */ + for (i = 0; i < 10; i++) { + ml_printf("%d: cntv_cval_el0=%lx\n", i, read_sysreg(cntv_cval_el0)); + } + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index 77c5018e02a..4b03ef602ea 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -45,7 +45,8 @@ TESTS+=memory-sve # Running QEMU_BASE_MACHINE=-M virt -cpu max -display none -QEMU_OPTS+=$(QEMU_BASE_MACHINE) -semihosting-config enable=on,target=native,chardev=output -kernel +QEMU_BASE_ARGS=-semihosting-config enable=on,target=native,chardev=output +QEMU_OPTS+=$(QEMU_BASE_MACHINE) $(QEMU_BASE_ARGS) -kernel # console test is manual only QEMU_SEMIHOST=-serial none -chardev stdio,mux=on,id=stdio0 -semihosting-config enable=on,chardev=stdio0 -mon chardev=stdio0,mode=readline @@ -56,6 +57,10 @@ run-semiconsole: semiconsole run-plugin-semiconsole-with-%: semiconsole $(call skip-test, $<, "MANUAL ONLY") +# vtimer test needs EL2 +QEMU_EL2_MACHINE=-machine virt,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 4 +run-vtimer: QEMU_OPTS=$(QEMU_EL2_MACHINE) $(QEMU_BASE_ARGS) -kernel + # Simple Record/Replay Test .PHONY: memory-record run-memory-record: memory-record memory From patchwork Mon Nov 27 17:08:13 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/13] hw/net/can/xlnx-zynqmp: Avoid underflow while popping TX FIFOs Date: Mon, 27 Nov 2023 17:08:13 +0000 Message-Id: <20231127170823.589863-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé Per https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format Message Format The same message format is used for RXFIFO, TXFIFO, and TXHPB. Each message includes four words (16 bytes). Software must read and write all four words regardless of the actual number of data bytes and valid fields in the message. There is no mention in this reference manual about what the hardware does when not all four words are written. To fix the reported underflow behavior when DATA2 register is written, I choose to fill the data with the previous content of the ID / DLC / DATA1 registers, which is how I expect hardware would do. Note there is no hardware flag raised under such condition. Reported-by: Qiang Liu Reviewed-by: Francisco Iglesias Reviewed-by: Vikram Garhwal Signed-off-by: Philippe Mathieu-Daudé Message-id: 20231124183325.95392-2-philmd@linaro.org Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1425 Reviewed-by: Francisco Iglesias Reviewed-by: Vikram Garhwal Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/net/can/xlnx-zynqmp-can.c | 50 +++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index e93e6c5e194..1f1c686479c 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -434,6 +434,52 @@ static bool tx_ready_check(XlnxZynqMPCANState *s) return true; } +static void read_tx_frame(XlnxZynqMPCANState *s, Fifo32 *fifo, uint32_t *data) +{ + unsigned used = fifo32_num_used(fifo); + bool is_txhpb = fifo == &s->txhpb_fifo; + + assert(used > 0); + used %= CAN_FRAME_SIZE; + + /* + * Frame Message Format + * + * Each frame includes four words (16 bytes). Software must read and write + * all four words regardless of the actual number of data bytes and valid + * fields in the message. + * If software misbehave (not writing all four words), we use the previous + * registers content to initialize each missing word. + * + * If used is 1 then ID, DLC and DATA1 are missing. + * if used is 2 then ID and DLC are missing. + * if used is 3 then only ID is missing. + */ + if (used > 0) { + data[0] = s->regs[is_txhpb ? R_TXHPB_ID : R_TXFIFO_ID]; + } else { + data[0] = fifo32_pop(fifo); + } + if (used == 1 || used == 2) { + data[1] = s->regs[is_txhpb ? R_TXHPB_DLC : R_TXFIFO_DLC]; + } else { + data[1] = fifo32_pop(fifo); + } + if (used == 1) { + data[2] = s->regs[is_txhpb ? R_TXHPB_DATA1 : R_TXFIFO_DATA1]; + } else { + data[2] = fifo32_pop(fifo); + } + /* DATA2 triggered the transfer thus is always available */ + data[3] = fifo32_pop(fifo); + + if (used) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Incomplete CAN frame (only %u/%u slots used)\n", + TYPE_XLNX_ZYNQMP_CAN, used, CAN_FRAME_SIZE); + } +} + static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) { qemu_can_frame frame; @@ -451,9 +497,7 @@ static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) } while (!fifo32_is_empty(fifo)) { - for (i = 0; i < CAN_FRAME_SIZE; i++) { - data[i] = fifo32_pop(fifo); - } + read_tx_frame(s, fifo, data); if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { /* From patchwork Mon Nov 27 17:08:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868880 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=JbaZBEVw; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBsV6VSxz23m6 for ; Tue, 28 Nov 2023 04:09:50 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f65-0007TA-Hf; Mon, 27 Nov 2023 12:08:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f60-0007Qq-Pz for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:33 -0500 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f5y-0004cl-Uf for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:32 -0500 Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-50aabfa1b75so6351785e87.3 for ; Mon, 27 Nov 2023 09:08:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104908; x=1701709708; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bsA0OtH+nvL+ZJuEfjGQayseVaIvl0J9HnDPUu7e/SA=; b=JbaZBEVwPVwcAfyL3Wwpi8+zvf5jzbn4wWOPe3pIRoI57URoEGKfzMoM4LzvfYuIK1 Lqq87gVDbFDt+VEj2ULdxGgMY9kwOvRkoNNHz0QTHNZA5Rxg+YFhq0exAdJiSHFpIeaW Lp1u+ZrxK+xnJQPoHBMXtJ2dPwMeSoS1GLNvrNh9BmyBm1Mlz41D35QMerMdio2lhGTk 7GK8vXAqguKlGIoJrT5BmlIuI3ilH5Ilt3UNDIrB+HrXvz9jEVT34jzcjsHL7P4gnLyl 7MusMcrRdKyTusALGr97YzOl0E0mqSN6MQag14Z55bvHb6R9VtK17+OEGK9piNosezfE ZZKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104908; x=1701709708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bsA0OtH+nvL+ZJuEfjGQayseVaIvl0J9HnDPUu7e/SA=; b=Kfx2yRXkMLmDgAtK/1oRmyKu/6CsbEGgePjb89r9fcfxZhjK47xOTFUjZcF9J+yBp9 IDlhIEXkpkONWjMYDyLUAahwa5a73+DSHT8C5pcoiu9ID+1AdhQ4XSyH5FYygVdMjz91 jIDVwWxKzTJksIfmdJlafF/6eS3lcOgEKjA6v9S2JbVy5VC5yx172LoaKIl8aektA9Bg kwdl1YIHsjZcBAvwC1HG+xBjk4T2CHyvMul63KX3UgdiPYlaH0qmP/b7PMT/7B7WThTM YtecLvXZ016DncsKEB8x91fh2Q1tQz/6kaEIT7qM4iiafxpNAgNsZdMyJVlVgrP6ic23 NtXw== X-Gm-Message-State: AOJu0YxRayeeKKd+C0MOdgTwjUCb0mFXreo9TA0iPCYzC/5FILoj/6H5 lOTd/oPC72Ux++K2OpWXTxQ5Oc6P4gQt7rxDwXQ= X-Google-Smtp-Source: AGHT+IG57jo7iLObOVs4nv/pJMk8FN4rg7HQoVcdhy1wt+3TOspm0ClkfL69vMJYj5VkcyRL8KBzhg== X-Received: by 2002:a2e:a7d3:0:b0:2c9:a088:aa19 with SMTP id x19-20020a2ea7d3000000b002c9a088aa19mr3924661ljp.34.1701104907335; Mon, 27 Nov 2023 09:08:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/13] hw/net/can/xlnx-zynqmp: Avoid underflow while popping RX FIFO Date: Mon, 27 Nov 2023 17:08:14 +0000 Message-Id: <20231127170823.589863-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé Per https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format Message Format The same message format is used for RXFIFO, TXFIFO, and TXHPB. Each message includes four words (16 bytes). Software must read and write all four words regardless of the actual number of data bytes and valid fields in the message. There is no mention in this reference manual about what the hardware does when not all four words are read. To fix the reported underflow behavior, I choose to fill the 4 frame data registers when the first register (ID) is accessed, which is how I expect hardware would do. Reported-by: Qiang Liu Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Vikram Garhwal Message-id: 20231124183325.95392-3-philmd@linaro.org Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1427 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Vikram Garhwal Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/net/can/xlnx-zynqmp-can.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index 1f1c686479c..f60e480c3ab 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -778,14 +778,18 @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame) } } -static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val) +static uint64_t can_rxfifo_post_read_id(RegisterInfo *reg, uint64_t val) { XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); + unsigned used = fifo32_num_used(&s->rx_fifo); - if (!fifo32_is_empty(&s->rx_fifo)) { - val = fifo32_pop(&s->rx_fifo); - } else { + if (used < CAN_FRAME_SIZE) { ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1); + } else { + val = s->regs[R_RXFIFO_ID] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DLC] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DATA1] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DATA2] = fifo32_pop(&s->rx_fifo); } can_update_irq(s); @@ -946,14 +950,11 @@ static const RegisterAccessInfo can_regs_info[] = { .post_write = can_tx_post_write, },{ .name = "RXFIFO_ID", .addr = A_RXFIFO_ID, .ro = 0xffffffff, - .post_read = can_rxfifo_pre_read, + .post_read = can_rxfifo_post_read_id, },{ .name = "RXFIFO_DLC", .addr = A_RXFIFO_DLC, .rsvd = 0xfff0000, - .post_read = can_rxfifo_pre_read, },{ .name = "RXFIFO_DATA1", .addr = A_RXFIFO_DATA1, - .post_read = can_rxfifo_pre_read, },{ .name = "RXFIFO_DATA2", .addr = A_RXFIFO_DATA2, - .post_read = can_rxfifo_pre_read, },{ .name = "AFR", .addr = A_AFR, .rsvd = 0xfffffff0, .post_write = can_filter_enable_post_write, From patchwork Mon Nov 27 17:08:15 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/13] hw/virtio: Add VirtioPCIDeviceTypeInfo::instance_finalize field Date: Mon, 27 Nov 2023 17:08:15 +0000 Message-Id: <20231127170823.589863-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé The VirtioPCIDeviceTypeInfo structure, added in commit a4ee4c8baa ("virtio: Helper for registering virtio device types") got extended in commit 8ea90ee690 ("virtio: add class_size") with the @class_size field. Do similarly with the @instance_finalize field. Signed-off-by: Philippe Mathieu-Daudé Message-id: 20231121174051.63038-2-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/virtio/virtio-pci.h | 1 + hw/virtio/virtio-pci.c | 1 + 2 files changed, 2 insertions(+) diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 5a3f182f998..59d88018c16 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -246,6 +246,7 @@ typedef struct VirtioPCIDeviceTypeInfo { size_t instance_size; size_t class_size; void (*instance_init)(Object *obj); + void (*instance_finalize)(Object *obj); void (*class_init)(ObjectClass *klass, void *data); InterfaceInfo *interfaces; } VirtioPCIDeviceTypeInfo; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 205dbf24fb1..e4338795423 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2391,6 +2391,7 @@ void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t) .parent = t->parent ? t->parent : TYPE_VIRTIO_PCI, .instance_size = t->instance_size, .instance_init = t->instance_init, + .instance_finalize = t->instance_finalize, .class_size = t->class_size, .abstract = true, .interfaces = t->interfaces, From patchwork Mon Nov 27 17:08:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868894 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=tHpm/FIb; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBvt0L9xz1yS6 for ; Tue, 28 Nov 2023 04:11:54 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f63-0007SX-Bv; Mon, 27 Nov 2023 12:08:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f60-0007Qp-KS for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:33 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f5y-0004d8-Us for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:32 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40b4734b975so7801185e9.2 for ; Mon, 27 Nov 2023 09:08:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104909; x=1701709709; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qtgG7nMoh/J0Wuwlj0UEmo0xDREAKAgqHzHLy2baaAs=; b=tHpm/FIbMSk76asN/NPxAIqbBY2sTRA/+K4/ECCf4J23jaswiYsw4rTu69Sb1D+Kpn gsW5s8f7GpWOCyW+2Fcp9t22nj8rGRMSQnK7UkF2vPNNqu6UnIBOH+yqKUKHIFSHZpLY KaUdaomqc1rfU24ZBgePb1+RzXZUGq4huSem6Idq144a5ww/TNDxVrUzY5HkS/q2viGQ YdJrhdyIthl1cyoKSGDLrTC/pxhfRIbvDGplFk6+qDjlWytxZJttCAkKQBzMH8NrqLvh sYLyMJJCQFELiXC33RkzHJcsTAMDyAIk8JrEuB0C4hPw4N/DUUQfCoWiseGwpQXlMUFh 2vxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104909; x=1701709709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qtgG7nMoh/J0Wuwlj0UEmo0xDREAKAgqHzHLy2baaAs=; b=cDuJERAMQFVRvVOu5PfySP7OLROYmX3ZPbb+subUysyz7csAEJh/UBJXYVYo1Ep7XV m3p8FpyUZ6r9jdgSm+5BYzpNDj/iE1gIxKTggTOyt8YDputg8wqPWhYdgxMyC59Pmxi0 zoAc0+dKoWi+P5Gv0OlteSv5nJi/V4isjSCc/cJK6ikensZkcjICnbO7kzPKRYXnFPoC x211iRgnCRyefWxSifql8vupXMB4RKR7sRZI3D1a9g8dOIGVfSrGLHRcUZTtfML7JMgb Qgms6WyLvsdLIihrPYUcbhUbVyRYZTnAfTWN3sA8Zx4hHPYtbv0A/nfPefPUeXuLabOJ pwGw== X-Gm-Message-State: AOJu0Yw94UBbIsXEL+n0hX52vfXUEr7hRnRgI+zcmbFvAkUJITT/xLBb kqTN5pxEclbLzeO3Ma0jhNG30mgctUr4bcyckec= X-Google-Smtp-Source: AGHT+IFI95OCuo/NzHfu++Hwvcqtwnv7kWHHKLyJZoSdqe0rmFlF80OSPswbui0qYqzRs1hByj2xLQ== X-Received: by 2002:a05:600c:19ca:b0:40b:367a:806 with SMTP id u10-20020a05600c19ca00b0040b367a0806mr8757538wmq.20.1701104909282; Mon, 27 Nov 2023 09:08:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/13] hw/virtio: Free VirtIOIOMMUPCI::vdev.reserved_regions[] on finalize() Date: Mon, 27 Nov 2023 17:08:16 +0000 Message-Id: <20231127170823.589863-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé Commit 0be6bfac62 ("qdev: Implement variable length array properties") added the DEFINE_PROP_ARRAY() macro with the following comment: * It is the responsibility of the device deinit code to free the * @_arrayfield memory. Commit 8077b8e549 added: DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI, vdev.nb_reserved_regions, vdev.reserved_regions, qdev_prop_reserved_region, ReservedRegion), but forgot to free the 'vdev.reserved_regions' array. Do it in the instance_finalize() handler. Cc: qemu-stable@nongnu.org Fixes: 8077b8e549 ("virtio-iommu-pci: Add array of Interval properties") # v5.1.0+ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Eric Auger Message-id: 20231121174051.63038-3-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/virtio/virtio-iommu-pci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c index 9459fbf6edf..cbdfe4c591c 100644 --- a/hw/virtio/virtio-iommu-pci.c +++ b/hw/virtio/virtio-iommu-pci.c @@ -95,10 +95,18 @@ static void virtio_iommu_pci_instance_init(Object *obj) TYPE_VIRTIO_IOMMU); } +static void virtio_iommu_pci_instance_finalize(Object *obj) +{ + VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(obj); + + g_free(dev->vdev.prop_resv_regions); +} + static const VirtioPCIDeviceTypeInfo virtio_iommu_pci_info = { .generic_name = TYPE_VIRTIO_IOMMU_PCI, .instance_size = sizeof(VirtIOIOMMUPCI), .instance_init = virtio_iommu_pci_instance_init, + .instance_finalize = virtio_iommu_pci_instance_finalize, .class_init = virtio_iommu_pci_class_init, }; From patchwork Mon Nov 27 17:08:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868885 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ZUBOqEcg; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBsm3FY2z23m6 for ; Tue, 28 Nov 2023 04:10:04 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f68-0007Tx-Iv; Mon, 27 Nov 2023 12:08:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f62-0007Rp-Rm for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:34 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f5z-0004dH-JH for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:33 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-40b4a8db314so155445e9.3 for ; Mon, 27 Nov 2023 09:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104910; x=1701709710; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=z25o5HgpS769sk9FWaELdrm182ytGgUoPKT3/jaRyEU=; b=ZUBOqEcgtMjks5jLUb0ovvKTTXJQiIdSpspkVlepP2SMxSua04ytRYArzHCk+f0XjL DpOuEWVTyPfFJL4o282mA2iaBQEfxw0cy4bqd5s8v6yC8l7AFWtXQGsWo2asJGceuhkK Fa/xyK1YnayrWDZOaQ8vcX/DI0SnHlmdJN1yeCnxjaJOHrPNk87HoAC2g4Q2R+bkEszm JFQbMVyHXM2m11NtsBIAG+ai6WMjBD9ed7hATA7SGjso03ph6+our+pMP+0oHQn8C3Xp qWNvSR8evwKLi2vxOQcKjsEWSLlgBr3x4T9BPk8GEu3FPsokxe5gu4fosm4lV+QkRWk+ n5tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104910; x=1701709710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z25o5HgpS769sk9FWaELdrm182ytGgUoPKT3/jaRyEU=; b=nbvwGfNK50HyRE4dpkxDwO5rh01L8JR5cZhnlqgSMjB+9xHx/sFQVX5jzK0WN/QAGA JfDLlMrTHEF8JKb3575zHirKXerq6T7fvrw4fbAEJBQIsoRIA19kmEvUFSGoYweXXdaJ qcOQOM7b95TTb2Hvn/PNX5KmKrJxWTkeasuQ4lpkg0TmacQT3Zb7whDsjTnR+0wGl0W8 EpuCqjvRDBwTshowE5wGOfl9yS5QAkn7nZ7vqlMfC3QnkTFZ5O7NXx9+bW9vnYp3yzQX ku1o22KhF3chwc2obP8AKy1Tow9IQqRMyQxsluWnX9ZOyTKVOG+642Qhkou8msXk5k3r Y8FQ== X-Gm-Message-State: AOJu0YyrRIgDLGsWt10c6dVGZsPhZymmteXPTbGyCeIZquRSGrSeMV8G Sdvm2BzbJSdXsvKbBhYTVDkIeR7EqJUV9r5rTT8= X-Google-Smtp-Source: AGHT+IGuHifjooqi6K+dZu14L9z0TaDUyYIvYXdWTYrTdss6jC5rPP2/EKCkQV3ILVKTkJ2XWe4CaA== X-Received: by 2002:a05:600c:4ed0:b0:40b:2b86:c886 with SMTP id g16-20020a05600c4ed000b0040b2b86c886mr5335928wmq.31.1701104909856; Mon, 27 Nov 2023 09:08:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/13] hw/misc/mps2-scc: Free MPS2SCC::oscclk[] array on finalize() Date: Mon, 27 Nov 2023 17:08:17 +0000 Message-Id: <20231127170823.589863-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé Commit 0be6bfac62 ("qdev: Implement variable length array properties") added the DEFINE_PROP_ARRAY() macro with the following comment: * It is the responsibility of the device deinit code to free the * @_arrayfield memory. Commit 4fb013afcc added: DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset, qdev_prop_uint32, uint32_t), but forgot to free the 'oscclk_reset' array. Do it in the instance_finalize() handler. Cc: qemu-stable@nongnu.org Fixes: 4fb013afcc ("hw/misc/mps2-scc: Support configurable number of OSCCLK values") # v6.0.0+ Signed-off-by: Philippe Mathieu-Daudé Message-id: 20231121174051.63038-4-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/mps2-scc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index b3b42a792cd..fe5034db140 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -329,6 +329,13 @@ static void mps2_scc_realize(DeviceState *dev, Error **errp) s->oscclk = g_new0(uint32_t, s->num_oscclk); } +static void mps2_scc_finalize(Object *obj) +{ + MPS2SCC *s = MPS2_SCC(obj); + + g_free(s->oscclk_reset); +} + static const VMStateDescription mps2_scc_vmstate = { .name = "mps2-scc", .version_id = 3, @@ -385,6 +392,7 @@ static const TypeInfo mps2_scc_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(MPS2SCC), .instance_init = mps2_scc_init, + .instance_finalize = mps2_scc_finalize, .class_init = mps2_scc_class_init, }; From patchwork Mon Nov 27 17:08:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868888 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=AtfBv7jq; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBtM4Hvfz1yS6 for ; Tue, 28 Nov 2023 04:10:35 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f6B-0007UW-96; Mon, 27 Nov 2023 12:08:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f62-0007Ro-R7 for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:34 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f5z-0004dM-JL for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:33 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-40b4744d603so7695495e9.2 for ; Mon, 27 Nov 2023 09:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104910; x=1701709710; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+2uI5wNmH21FhUP7Rp19KQf2tC2ID75lHpAU974IEJI=; b=AtfBv7jqq4qRnRVCPjqzs7KQ/sj0tM6xMueJTMWjApWbO3HpVvp8tYhUmAFyxLVTiN Gav5Of/qOidOTJ39JedLMNJfUSzZFx1SH8IFig2dJaBLL2L0Dz0G9TochBE3ml4gsDHR U1hVLsnnY5ux2qFVDce6WlVOjqM2+WPreqgumVXi2sbdHcp8fNfcGtms8dyw/shpYZaa Vv5na606WWtr6Qk7shDxZNYJ3wIxyTm1vGdTj1HDrO2fu0BBxhFagJm7TriYZR1VGTsD SLYVVFTPZan+kvh8nR9D0DCccATpeOEoCHccSTuJm+7QEJlrhViL2K0ZAf9H2cwnG97/ iBWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104910; x=1701709710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+2uI5wNmH21FhUP7Rp19KQf2tC2ID75lHpAU974IEJI=; b=edKELDlBHh+6DAHkGMojGGXA3nwgcH+JlmGTgk+d9gOa/v/NFH/r/VgiWCqE5h9wR0 q6m3B77runfTrJftGLZBXzE3FAKIEL5JkapABFjASCYdVITVA7yg8APm0kvSAbcZr5Sk V3dNrLbc+C+4KGQ06G390+S3zaUC1pW8rGZ88Aa10wCu3NFK9i8s4serLDGeM76ta5IC tYhduweW1CTNpbGSYFz5vOfMStEFBFPYAMWGbXNxBl7LbDd0FXRzp3PxBvNA09UOhKnY GRKSCBVG3CaAvJj8wgUXqr9YhwdRVBto6o0d+iXs8k9nMAJoy0X8CHjkjTf514GbJ3d1 tFVw== X-Gm-Message-State: AOJu0Ywz/OIr77S29AfgkZv/yQM5jnoXk6O6VYp/6dtCLHDC4toCT8ul m2EqogLo2W7MHk9OeGiaqY9v8DpAOpzYN06L2Vk= X-Google-Smtp-Source: AGHT+IFib3sAWbW3EY9wIWkCdeDuxGzhtZVy6NqjbxaO+bm8oTjqcjaZlmsqP3RodjV5IetviPlLUQ== X-Received: by 2002:a05:600c:1f8c:b0:40b:2baa:6a0d with SMTP id je12-20020a05600c1f8c00b0040b2baa6a0dmr4811964wmb.1.1701104910300; Mon, 27 Nov 2023 09:08:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/13] hw/nvram/xlnx-efuse: Free XlnxEFuse::ro_bits[] array on finalize() Date: Mon, 27 Nov 2023 17:08:18 +0000 Message-Id: <20231127170823.589863-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé Commit 0be6bfac62 ("qdev: Implement variable length array properties") added the DEFINE_PROP_ARRAY() macro with the following comment: * It is the responsibility of the device deinit code to free the * @_arrayfield memory. Commit 68fbcc344e added: DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits, qdev_prop_uint32, uint32_t), but forgot to free the 'ro_bits' array. Do it in the instance_finalize handler. Cc: qemu-stable@nongnu.org Fixes: 68fbcc344e ("hw/nvram: Introduce Xilinx eFuse QOM") # v6.2.0+ Signed-off-by: Philippe Mathieu-Daudé Message-id: 20231121174051.63038-5-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/nvram/xlnx-efuse.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c index 655c40b8d1e..f7b849f7de4 100644 --- a/hw/nvram/xlnx-efuse.c +++ b/hw/nvram/xlnx-efuse.c @@ -224,6 +224,13 @@ static void efuse_realize(DeviceState *dev, Error **errp) } } +static void efuse_finalize(Object *obj) +{ + XlnxEFuse *s = XLNX_EFUSE(obj); + + g_free(s->ro_bits); +} + static void efuse_prop_set_drive(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -280,6 +287,7 @@ static const TypeInfo efuse_info = { .name = TYPE_XLNX_EFUSE, .parent = TYPE_DEVICE, .instance_size = sizeof(XlnxEFuse), + .instance_finalize = efuse_finalize, .class_init = efuse_class_init, }; From patchwork Mon Nov 27 17:08:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868878 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=kf87bU9m; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBsD2fbMz1ySP for ; Tue, 28 Nov 2023 04:09:34 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f65-0007TN-Sn; Mon, 27 Nov 2023 12:08:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f62-0007Rq-Rn for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:34 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f60-0004dY-53 for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:33 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40b2ddab817so31259025e9.3 for ; Mon, 27 Nov 2023 09:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104910; x=1701709710; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8Li9u/apX2z/hqU6tBl3/yWCNm5priiBHrKq1erqDx8=; b=kf87bU9mvZgbYN2EfFtERGWyuazWVtB8zn5oSJZ1DteR+fYzbIakHkeD6JNHglvgTk RQdZoJWzEhdmUakaCYPhQsZdJrrViTV1Wm+/TkykLGGsT8EHUEUJVbSf6B0RmuwOFP1L 91eC6iF7FP0J/pmTJd1GWoLfoeg95e1Fzass752K1tOJ6cZ+1JkUtIIAV7hHn6DRvHVw GbtbqJybgNPniRAhPGWMj2gUDm/RnaPut/U8FqFxMS2lFQ+Y1cIVxFQ0IvPcr/R62UFK 2ElsjyFFhNxk9OKy3Dj6NEKGec9fzCgLUMDOWL5SV67qVHJ1E6CFqbaV4MmlQTNWh/sG 5hww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104910; x=1701709710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Li9u/apX2z/hqU6tBl3/yWCNm5priiBHrKq1erqDx8=; b=OMgwnu6dSIhhelCEj0UeZ7rssIXSdk3PZhCgxZmJ/bJ7ieKD/S3COpDOh+TY4e7K5T jV9XBc+qAptsbnLtGIJi0fHjCM2OkGNIKk4+2cV2sXhI1vNk5PpkMaQdm34bygkGEK5f F7Ri56M1awAqI+uDUL3ijo+OW4JYk01F3Ix3VhvLinHHExmrpntkhGbI17FNJLQWra0y +J4xMVfCea36XxVlxv9j03iiREPf5sIlcHc5FM3MAUWHEntrn6e1IlYqa/HE8pwRxOLA c++4t1OcgRJWn9PQnBVXw38gYoqIVQarxT4QptXGhf9yy5GnwF5dz9NybManys1QmxR0 B1bg== X-Gm-Message-State: AOJu0Yxdzy1RNzJ2b5DzjCWsz18mYtS4cZrMn6I3xndJ5/vetfMSsnp3 YH1yru4ug1epNp1byZT2y+wClbYsoGaaVCP6TRA= X-Google-Smtp-Source: AGHT+IHidsQlkcjdo/msC76Qscrt63c2ufhA+Ni8HzenWAHzajm1R6IbjsqIATUbcXvieKEUneRPSg== X-Received: by 2002:a05:600c:4749:b0:40b:35aa:bfdd with SMTP id w9-20020a05600c474900b0040b35aabfddmr5570219wmo.27.1701104910703; Mon, 27 Nov 2023 09:08:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/13] hw/nvram/xlnx-efuse-ctrl: Free XlnxVersalEFuseCtrl[] "pg0-lock" array Date: Mon, 27 Nov 2023 17:08:19 +0000 Message-Id: <20231127170823.589863-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé Commit 0be6bfac62 ("qdev: Implement variable length array properties") added the DEFINE_PROP_ARRAY() macro with the following comment: * It is the responsibility of the device deinit code to free the * @_arrayfield memory. Commit 9e4aa1fafe added: DEFINE_PROP_ARRAY("pg0-lock", XlnxVersalEFuseCtrl, extra_pg0_lock_n16, extra_pg0_lock_spec, qdev_prop_uint16, uint16_t), but forgot to free the 'extra_pg0_lock_spec' array. Do it in the instance_finalize() handler. Cc: qemu-stable@nongnu.org Fixes: 9e4aa1fafe ("hw/nvram: Xilinx Versal eFuse device") # v6.2.0+ Signed-off-by: Philippe Mathieu-Daudé Message-id: 20231121174051.63038-6-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/nvram/xlnx-versal-efuse-ctrl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c index beb5661c35f..2480af35e1b 100644 --- a/hw/nvram/xlnx-versal-efuse-ctrl.c +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c @@ -726,6 +726,13 @@ static void efuse_ctrl_init(Object *obj) sysbus_init_irq(sbd, &s->irq_efuse_imr); } +static void efuse_ctrl_finalize(Object *obj) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); + + g_free(s->extra_pg0_lock_spec); +} + static const VMStateDescription vmstate_efuse_ctrl = { .name = TYPE_XLNX_VERSAL_EFUSE_CTRL, .version_id = 1, @@ -764,6 +771,7 @@ static const TypeInfo efuse_ctrl_info = { .instance_size = sizeof(XlnxVersalEFuseCtrl), .class_init = efuse_ctrl_class_init, .instance_init = efuse_ctrl_init, + .instance_finalize = efuse_ctrl_finalize, }; static void efuse_ctrl_register_types(void) From patchwork Mon Nov 27 17:08:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868896 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=rhMUlqoE; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBvz58KJz1yS6 for ; Tue, 28 Nov 2023 04:11:59 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f6D-0007WM-Ql; Mon, 27 Nov 2023 12:08:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f63-0007Sb-JT for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:35 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f61-0004dj-9Z for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:34 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40b427507b7so12741075e9.2 for ; Mon, 27 Nov 2023 09:08:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104911; x=1701709711; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VSnQX/38IwFzIkR+hMTwUicJZArqSWcbr4ZMRYvD5BY=; b=rhMUlqoEdFFGmU1/to256yLyud9WNgJ7p6ROHKvXALTWU2laNm9oMASpYjSXZMZKyg 2o/GMmwjdhVoJOOU5+ILTQULb2jRXTa2dqd3/s3YBJZ/JmrssoNyNE2avRZBKvRCW6JE tcIxO5NPB3CB24gnzadA2v9JckcWbBTa068lYqZCEk0BaSH7VN3F8RIpQ97OU+59PK+K rqaH58IOogSZctUv25yvs8u8X3Yy2CMCXFZN7JJSatXNdZab7i8Ny4WqHMxaglfatsYN W1YS088jx15UN0H9LaAE0mI7DVi2PVCMVnjtQjfkwYM95Kiez2LFXiAn/JdZ6v+mte71 DVEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104911; x=1701709711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VSnQX/38IwFzIkR+hMTwUicJZArqSWcbr4ZMRYvD5BY=; b=CX48ypNMHG0bsKCds01VGNXQFJTJRuSAq/0Wunja3k25uBAsULwKwolF8RMuG6td2G LrMMditP1IH39Zxgwjt/CjC9iaOoyJ7AumrQmQXHllY/3aSF3irhH+GUQVuO4lGDCj1v lRJFr+7VIQhPc4oAwcQk6BbdSHaCfFStOR59XsAEI+ewOWu+FyQbCJ0F1vEoiIdwBI7G OLlaMrXBzhz09vg+AYgCB6bNviUF+pMxq882GTxVQrpEIP43Elmgup3Nw7ZRWpJdWm6W HD3sC1CnK8zNsBx/3bYt9eb+jnOCwE2YmhGhW4Q+CUWNy6i+nyCr92ymOSCFlCafiCey TaWg== X-Gm-Message-State: AOJu0YwfD3SNWmGz4DGaRAgIOF+3z5tbXkxZmXJhh4rj8bD0/ntQjPBK PGWSS99Qg/jLm+5ifuOSxCptGwQ+FCaP51ypL08= X-Google-Smtp-Source: AGHT+IEwxhzwsyGSVN7pY2EVQuoIAKsonm2kqCrh/byTAyeszfkdF85ds6vTdQPR8j+Bxx4MlhpceQ== X-Received: by 2002:a05:600c:4ed0:b0:409:5bd2:aa00 with SMTP id g16-20020a05600c4ed000b004095bd2aa00mr10374989wmq.41.1701104911131; Mon, 27 Nov 2023 09:08:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/13] hw/input/stellaris_gamepad: Free StellarisGamepad::keycodes[] array Date: Mon, 27 Nov 2023 17:08:20 +0000 Message-Id: <20231127170823.589863-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé Commit 0be6bfac62 ("qdev: Implement variable length array properties") added the DEFINE_PROP_ARRAY() macro with the following comment: * It is the responsibility of the device deinit code to free the * @_arrayfield memory. Commit a75f336b97 added: DEFINE_PROP_ARRAY("keycodes", StellarisGamepad, num_buttons, keycodes, qdev_prop_uint32, uint32_t), but forgot to free the 'keycodes' array. Do it in the instance_finalize handler. Fixes: a75f336b97 ("hw/input/stellaris_input: Convert to qdev") Signed-off-by: Philippe Mathieu-Daudé Message-id: 20231121174051.63038-7-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/input/stellaris_gamepad.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/input/stellaris_gamepad.c b/hw/input/stellaris_gamepad.c index 06a0c0ce839..9dfa620e29a 100644 --- a/hw/input/stellaris_gamepad.c +++ b/hw/input/stellaris_gamepad.c @@ -63,6 +63,13 @@ static void stellaris_gamepad_realize(DeviceState *dev, Error **errp) qemu_input_handler_register(dev, &stellaris_gamepad_handler); } +static void stellaris_gamepad_finalize(Object *obj) +{ + StellarisGamepad *s = STELLARIS_GAMEPAD(obj); + + g_free(s->keycodes); +} + static void stellaris_gamepad_reset_enter(Object *obj, ResetType type) { StellarisGamepad *s = STELLARIS_GAMEPAD(obj); @@ -92,6 +99,7 @@ static const TypeInfo stellaris_gamepad_info[] = { .name = TYPE_STELLARIS_GAMEPAD, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(StellarisGamepad), + .instance_finalize = stellaris_gamepad_finalize, .class_init = stellaris_gamepad_class_init, }, }; From patchwork Mon Nov 27 17:08:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=XKUXt+cZ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBvv1RhQz1yS6 for ; Tue, 28 Nov 2023 04:11:55 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r7f6D-0007V6-3o; Mon, 27 Nov 2023 12:08:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r7f63-0007Sc-JV for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:36 -0500 Received: from mail-lj1-x235.google.com ([2a00:1450:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r7f61-0004do-A6 for qemu-devel@nongnu.org; Mon, 27 Nov 2023 12:08:34 -0500 Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2c87adce180so54661761fa.0 for ; Mon, 27 Nov 2023 09:08:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104911; x=1701709711; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=r7VN+FUHi4irf+Hlji9rNkb2Vpl4dSI7XsEUkLnRwXY=; b=XKUXt+cZ/EJEc9urUIHlZpL77MT4eP3bdcJxV1go8RlzlQ5EzqREGn3eE+ehjtIL3o RLaEtHmQK+pmpVBdtQaTtXfOqYbptdmnn5DFvuPSN0sW1FszXXa01cO4C2qA1EQWs/Kn g57R1PVDT6/ydrmZg0ah2CSulXebhn0k8psMJ8vfaKvgNRAG8hEpJ0LgR3N3IkpokaFJ TQJ5Q1R9QWetgN3OIAiY2qwPOZRlIVodo2QvStTMUwHLq3Szo8mK1f4XLRX6CGEKPra5 WWa0cLOw3DouQK+vPulMhlOqYtaoi+ngCrgh9l04G91/NfoAZr5gwAdwTlOwaKtC0Bhj TOrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104911; x=1701709711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7VN+FUHi4irf+Hlji9rNkb2Vpl4dSI7XsEUkLnRwXY=; b=dhi49IksCCmlvQP6VPrPJ6o6HmVpiAMOl5eNTimiz5zwM7iO/upx+qy0/+AjB1ioBd 9f8+fYWWAZFCMdikByhrtA+IWyyrUVrX29nUff3Ku4b44qODyqFwWOTQ6NlDKMwMX7/H KrCpK+R4MsihfRY0f2gH8CYFM83loj9rllvdSyF6VqAV+9ZRsYb6t1oNYPplcCaFutCA Nd8PFT7yQb6mU5wfMZ2457NvCkP8WeN5RVRFnGLQJOEMwE0Mjp9Al2P/uzG7VV5atxwT 10mWS2mAjN7ZnPT//U1UviFCWT25+hFrQ282PQ9sZIFeFC7pcJzL2oAhG6mraPdCm5tl 62fA== X-Gm-Message-State: AOJu0YwFL0U3Bmyd0wF3KCIUbeNV54Z9BFo1bpSzUTYhMcSYDWc8NsvR RdzwibeAA0AqX9UiacJ81YoP+YYieXL5DvVbhfY= X-Google-Smtp-Source: AGHT+IFuj6WVWGl6AUS/UQbvq6SRqgXnU7dR7oz2kGroewS9TL/DH82Djm8sUbpbPMIYUxYHUQlXwg== X-Received: by 2002:a05:651c:48b:b0:2c9:9737:28ab with SMTP id s11-20020a05651c048b00b002c9973728abmr5175016ljc.2.1701104911601; Mon, 27 Nov 2023 09:08:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/13] hw/ssi/xilinx_spips: fix an out of bound access Date: Mon, 27 Nov 2023 17:08:21 +0000 Message-Id: <20231127170823.589863-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Frederic Konrad The spips, qspips, and zynqmp-qspips share the same realize function (xilinx_spips_realize) and initialize their io memory region with different mmio_ops passed through the class. The size of the memory region is set to the largest area (0x200 bytes for zynqmp-qspips) thus it is possible to write out of s->regs[addr] in xilinx_spips_write for spips and qspips. This fixes that wrong behavior. Reviewed-by: Luc Michel Signed-off-by: Frederic Konrad Reviewed-by: Francisco Iglesias Message-id: 20231124143505.1493184-2-fkonrad@amd.com Signed-off-by: Peter Maydell --- include/hw/ssi/xilinx_spips.h | 3 +++ hw/ssi/xilinx_spips.c | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 1386d5ac8fe..7a754bf67a2 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -33,7 +33,9 @@ typedef struct XilinxSPIPS XilinxSPIPS; +/* For SPIPS, QSPIPS. */ #define XLNX_SPIPS_R_MAX (0x100 / 4) +/* For ZYNQMP_QSPIPS. */ #define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) /* Bite off 4k chunks at a time */ @@ -125,6 +127,7 @@ struct XilinxSPIPSClass { SysBusDeviceClass parent_class; const MemoryRegionOps *reg_ops; + uint64_t reg_size; uint32_t rx_fifo_size; uint32_t tx_fifo_size; diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a3955c6c50c..0bdfad7e2e5 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -973,6 +973,8 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr, (unsigned)value); addr >>= 2; + assert(addr < XLNX_SPIPS_R_MAX); + switch (addr) { case R_CONFIG: mask = ~(R_CONFIG_RSVD | MAN_START_COM); @@ -1299,7 +1301,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) } memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, - "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); + "spi", xsc->reg_size); sysbus_init_mmio(sbd, &s->iomem); s->irqline = -1; @@ -1435,6 +1437,7 @@ static void xilinx_qspips_class_init(ObjectClass *klass, void * data) dc->realize = xilinx_qspips_realize; xsc->reg_ops = &qspips_ops; + xsc->reg_size = XLNX_SPIPS_R_MAX * 4; xsc->rx_fifo_size = RXFF_A_Q; xsc->tx_fifo_size = TXFF_A_Q; } @@ -1450,6 +1453,7 @@ static void xilinx_spips_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_xilinx_spips; xsc->reg_ops = &spips_ops; + xsc->reg_size = XLNX_SPIPS_R_MAX * 4; xsc->rx_fifo_size = RXFF_A; xsc->tx_fifo_size = TXFF_A; } @@ -1464,6 +1468,7 @@ static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) dc->vmsd = &vmstate_xlnx_zynqmp_qspips; device_class_set_props(dc, xilinx_zynqmp_qspips_properties); xsc->reg_ops = &xlnx_zynqmp_qspips_ops; + xsc->reg_size = XLNX_ZYNQMP_SPIPS_R_MAX * 4; xsc->rx_fifo_size = RXFF_A_Q; xsc->tx_fifo_size = TXFF_A_Q; } From patchwork Mon Nov 27 17:08:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1868881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=mI0KGuxt; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SfBsV4pkKz1ySP for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/13] hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models Date: Mon, 27 Nov 2023 17:08:22 +0000 Message-Id: <20231127170823.589863-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Frederic Konrad It seems that the url changed a bit, and it triggers an error. Fix the URLs so the documentation can be reached again. Signed-off-by: Frederic Konrad Reviewed-by: Francisco Iglesias Message-id: 20231124143505.1493184-3-fkonrad@amd.com Signed-off-by: Peter Maydell --- include/hw/misc/xlnx-versal-cframe-reg.h | 2 +- include/hw/misc/xlnx-versal-cfu.h | 2 +- include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 2 +- include/hw/ssi/xlnx-versal-ospi.h | 2 +- hw/dma/xlnx_csu_dma.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/misc/xlnx-versal-cframe-reg.h b/include/hw/misc/xlnx-versal-cframe-reg.h index a14fbd7fe45..0091505246f 100644 --- a/include/hw/misc/xlnx-versal-cframe-reg.h +++ b/include/hw/misc/xlnx-versal-cframe-reg.h @@ -12,7 +12,7 @@ * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf * * [2] Versal ACAP Register Reference, - * https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html + * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFRAME_REG-Module */ #ifndef HW_MISC_XLNX_VERSAL_CFRAME_REG_H #define HW_MISC_XLNX_VERSAL_CFRAME_REG_H diff --git a/include/hw/misc/xlnx-versal-cfu.h b/include/hw/misc/xlnx-versal-cfu.h index 86fb8410538..be62bab8c8c 100644 --- a/include/hw/misc/xlnx-versal-cfu.h +++ b/include/hw/misc/xlnx-versal-cfu.h @@ -12,7 +12,7 @@ * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf * * [2] Versal ACAP Register Reference, - * https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html + * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFU_CSR-Module */ #ifndef HW_MISC_XLNX_VERSAL_CFU_APB_H #define HW_MISC_XLNX_VERSAL_CFU_APB_H diff --git a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h index f7d24c93c41..0c4a4fd66d9 100644 --- a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h +++ b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h @@ -34,7 +34,7 @@ * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf * * [2] Versal ACAP Register Reference, - * https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___pmc_iop_slcr.html + * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PMC_IOP_SLCR-Module * * QEMU interface: * + sysbus MMIO region 0: MemoryRegion for the device's registers diff --git a/include/hw/ssi/xlnx-versal-ospi.h b/include/hw/ssi/xlnx-versal-ospi.h index 5d131d351d2..4ac975aa2fd 100644 --- a/include/hw/ssi/xlnx-versal-ospi.h +++ b/include/hw/ssi/xlnx-versal-ospi.h @@ -34,7 +34,7 @@ * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf * * [2] Versal ACAP Register Reference, - * https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___ospi.html + * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/OSPI-Module * * * QEMU interface: diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index e89089821a3..531013f35aa 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -33,7 +33,7 @@ /* * Ref: UG1087 (v1.7) February 8, 2019 - * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html + * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers * CSUDMA Module section */ REG32(ADDR, 0x0) From patchwork Mon Nov 27 17:08:23 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/13] hw/dma/xlnx_csu_dma: don't throw guest errors when stopping the SRC DMA Date: Mon, 27 Nov 2023 17:08:23 +0000 Message-Id: <20231127170823.589863-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Frederic Konrad UG1087 states for the source channel that: if SIZE is programmed to 0, and the DMA is started, the interrupts DONE and MEM_DONE will be asserted. This implies that it is allowed for the guest to stop the source DMA by writing a size of 0 to the SIZE register, so remove the LOG_GUEST_ERROR in that case. While at it remove the comment marking the SIZE register as write-only. See: https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/CSUDMA_SRC_SIZE-CSUDMA-Register Signed-off-by: Frederic Konrad Reviewed-by: Francisco Iglesias Message-id: 20231124143505.1493184-4-fkonrad@amd.com Signed-off-by: Peter Maydell --- hw/dma/xlnx_csu_dma.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 531013f35aa..bc1505aade7 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -39,7 +39,7 @@ REG32(ADDR, 0x0) FIELD(ADDR, ADDR, 2, 30) /* wo */ REG32(SIZE, 0x4) - FIELD(SIZE, SIZE, 2, 27) /* wo */ + FIELD(SIZE, SIZE, 2, 27) FIELD(SIZE, LAST_WORD, 0, 1) /* rw, only exists in SRC */ REG32(STATUS, 0x8) FIELD(STATUS, DONE_CNT, 13, 3) /* wtc */ @@ -335,10 +335,14 @@ static uint64_t addr_pre_write(RegisterInfo *reg, uint64_t val) static uint64_t size_pre_write(RegisterInfo *reg, uint64_t val) { XlnxCSUDMA *s = XLNX_CSU_DMA(reg->opaque); + uint64_t size = val & R_SIZE_SIZE_MASK; if (s->regs[R_SIZE] != 0) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Starting DMA while already running.\n", __func__); + if (size || s->is_dst) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Starting DMA while already running.\n", + __func__); + } } if (!s->is_dst) { @@ -346,7 +350,7 @@ static uint64_t size_pre_write(RegisterInfo *reg, uint64_t val) } /* Size is word aligned */ - return val & R_SIZE_SIZE_MASK; + return size; } static uint64_t size_post_read(RegisterInfo *reg, uint64_t val)