From patchwork Thu Nov 9 07:18:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Randolph X-Patchwork-Id: 1861864 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SQtcD5Zrvz1yRF for ; Thu, 9 Nov 2023 18:19:08 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1F64A870A8; Thu, 9 Nov 2023 08:18:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 3735D86F6F; Thu, 9 Nov 2023 08:18:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00,RDNS_DYNAMIC, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AD68086FF6 for ; Thu, 9 Nov 2023 08:18:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=randolph@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3A97IWlc031813; Thu, 9 Nov 2023 15:18:32 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 9 Nov 2023 15:18:31 +0800 From: Randolph To: CC: , , , , Randolph , CL Wang Subject: [PATCH 1/2] drivers: watchdog: add andes atcwdt200 support Date: Thu, 9 Nov 2023 15:18:23 +0800 Message-ID: <20231109071824.850865-1-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.173] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3A97IWlc031813 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang Signed-off-by: Randolph --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/atcwdt200_wdt.c | 219 +++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+) create mode 100644 drivers/watchdog/atcwdt200_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 07fc4940e9..6b0f77dd3f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -130,6 +130,12 @@ config WDT_AT91 Select this to enable Microchip watchdog timer, which can be found on some AT91 devices. +config WDT_ATCWDT200 + bool "Andes watchdog timer support" + depends on WDT + help + Select this to enable Andes ATCWDT200 watchdog timer + config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || BCM6856 || \ diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index eef786f5e7..1750ebbb1f 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o +obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c new file mode 100644 index 0000000000..dc34013473 --- /dev/null +++ b/drivers/watchdog/atcwdt200_wdt.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation. + * + */ + +#include +#include +#include +#include +#include + +#define NODE_NOT_FOUND 0xFFFFFFFF + +#define WDT_WP_MAGIC 0x5aa5 +#define WDT_RESTART_MAGIC 0xcafe + +/* Control Register */ +#define REG_WDT_ID 0x00 +#define REG_WDT_CFG 0x10 +#define REG_WDT_RS 0x14 +#define REG_WDT_WE 0x18 +#define REG_WDT_STA 0x1C + +#define RST_TIME_OFF 8 +#define RST_TIME_MSK (0x7 << RST_TIME_OFF) +#define RST_CLK_128 (0 << RST_TIME_OFF) +#define RST_CLK_256 (1 << RST_TIME_OFF) +#define RST_CLK_512 (2 << RST_TIME_OFF) +#define RST_CLK_1024 (3 << RST_TIME_OFF) +#define INT_TIME_OFF 4 +#define INT_TIME_MSK (0xf << INT_TIME_OFF) +#define INT_CLK_2_6 (0 << INT_TIME_OFF) /* clk period*2^6 */ +#define INT_CLK_2_8 (1 << INT_TIME_OFF) /* clk period*2^8 */ +#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */ +#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */ +#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */ +#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */ +#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */ +#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */ +#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */ +#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */ +#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */ +#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */ +#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */ +#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */ +#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */ +#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */ +#define INT_CLK_MIN 0x0 +#define INT_CLK_MAX_16B 0x7 +#define INT_CLK_MAX_32B 0xF +#define RST_EN BIT(3) +#define INT_EN BIT(2) +#define CLK_PCLK BIT(1) +#define WDT_EN BIT(0) +#define INT_EXPIRED BIT(0) + +#define INT_TIME_ARRAY 16 +#define RST_TIME_ARRAY 8 + +struct wdt_priv { + void __iomem *base; + u32 wdt_clk_src; + u32 clk_freq; + u8 max_clk; +}; + +static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type) +{ + u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15, 17, 19, 21, 23, 25, 27, 29, 31}; + u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14}; + u8 *pdiv; + + if (type == RST_TIME_ARRAY) + pdiv = div_rst; + else + pdiv = div_int; + + if (index >= type) + index = type - 1; + + return pdiv[index]; +} + +static u8 atwdt_search_msb(u64 freq_ms, u8 type) +{ + u64 result; + u64 freq_sec; + u8 index; + + freq_sec = freq_ms / 1000; + for (index = 0; index < type; index++) { + result = freq_sec >> atcwdt_get_2_power_of_n(index, type); + + if (result <= 1) + break; + } + + return index; +} + +static int atcwdt_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct wdt_priv *priv = dev_get_priv(dev); + u64 rst_max_count; + u32 rst_max_time_ms; + u64 rst_time_ms; + u64 int_time_ms; + u8 rst_time; + u8 int_time; + + rst_max_count = 1 << atcwdt_get_2_power_of_n(RST_TIME_ARRAY, RST_TIME_ARRAY); + rst_max_time_ms = (rst_max_count * 1000) / priv->clk_freq; + + if (timeout > rst_max_time_ms) { + int_time_ms = timeout - rst_max_time_ms; + rst_time_ms = rst_max_time_ms; + } else { + int_time_ms = 0; + rst_time_ms = timeout; + } + + rst_time = atwdt_search_msb(rst_time_ms * priv->clk_freq, RST_TIME_ARRAY); + + if (int_time_ms) { + int_time = atwdt_search_msb(int_time_ms * priv->clk_freq, INT_TIME_ARRAY); + if (int_time > priv->max_clk) + int_time = priv->max_clk; + } else { + int_time = 0; + } + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(((rst_time << RST_TIME_OFF) & RST_TIME_MSK) | ((int_time << INT_TIME_OFF) & + INT_TIME_MSK) | INT_EN | RST_EN | priv->wdt_clk_src | WDT_EN, + priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_stop(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(0, priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_restart(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(WDT_RESTART_MAGIC, priv->base + REG_WDT_RS); + setbits_le32(priv->base + REG_WDT_STA, INT_EXPIRED); + + return 0; +} + +static int atcwdt_wdt_expire_now(struct udevice *dev, ulong flags) +{ + atcwdt_wdt_start(dev, 0, 0); + hang(); + + return 0; +} + +static int atcwdt_wdt_probe(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + int timer_16bit; + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EFAULT; + + priv->wdt_clk_src = dev_read_u32_default(dev, "clock-source", NODE_NOT_FOUND); + if (priv->wdt_clk_src == NODE_NOT_FOUND || priv->wdt_clk_src > 1) + priv->wdt_clk_src = CLK_PCLK; + + timer_16bit = dev_read_u32_default(dev, "16bit_timer", NODE_NOT_FOUND); + if (timer_16bit == 1 || timer_16bit == NODE_NOT_FOUND) + priv->max_clk = INT_CLK_MAX_16B; + else + priv->max_clk = INT_CLK_MAX_32B; + + priv->clk_freq = dev_read_u32_default(dev, "clock-frequency", NODE_NOT_FOUND); + if (priv->clk_freq == NODE_NOT_FOUND) { + printf("atcwdt200: Please provide a valid \"clock-frequency\" in DTB\n"); + return -EINVAL; + } + + atcwdt_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops atcwdt_wdt_ops = { + .start = atcwdt_wdt_start, + .reset = atcwdt_wdt_restart, + .stop = atcwdt_wdt_stop, + .expire_now = atcwdt_wdt_expire_now, +}; + +static const struct udevice_id atcwdt_wdt_ids[] = { + {.compatible = "andestech,atcwdt200"}, + {} +}; + +U_BOOT_DRIVER(atcwdt) = { + .name = "atc_wdt", + .id = UCLASS_WDT, + .probe = atcwdt_wdt_probe, + .of_match = atcwdt_wdt_ids, + .ops = &atcwdt_wdt_ops, + .priv_auto = sizeof(struct wdt_priv), +}; From patchwork Thu Nov 9 07:18:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Randolph X-Patchwork-Id: 1861863 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SQtc76nLKz1yRF for ; Thu, 9 Nov 2023 18:19:01 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A260186F6F; Thu, 9 Nov 2023 08:18:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2089387090; Thu, 9 Nov 2023 08:18:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00,RDNS_DYNAMIC, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 09F9086F6F for ; Thu, 9 Nov 2023 08:18:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=randolph@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3A97Ibx9032043; Thu, 9 Nov 2023 15:18:37 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 9 Nov 2023 15:18:33 +0800 From: Randolph To: CC: , , , , Randolph , CL Wang Subject: [PATCH 2/2] configs: andes: add watchdog support fot andes ae350 Date: Thu, 9 Nov 2023 15:18:24 +0800 Message-ID: <20231109071824.850865-2-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231109071824.850865-1-randolph@andestech.com> References: <20231109071824.850865-1-randolph@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.173] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3A97Ibx9032043 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph --- configs/ae350_rv32_defconfig | 4 ++++ configs/ae350_rv32_spl_defconfig | 4 ++++ configs/ae350_rv32_spl_xip_defconfig | 4 ++++ configs/ae350_rv32_xip_defconfig | 4 ++++ configs/ae350_rv64_defconfig | 4 ++++ configs/ae350_rv64_spl_defconfig | 4 ++++ configs/ae350_rv64_spl_xip_defconfig | 4 ++++ configs/ae350_rv64_xip_defconfig | 4 ++++ 8 files changed, 32 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06cd972a0d..a32672f8ed 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f469d5bb2b..e09f878329 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 9672a19c23..850e67a0d9 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b90200a97e..8745ac4c07 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a4b9ad6162..4aa0b1a29d 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 834a0fbbdd..1a3c294b16 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index b52b8d78d7..f8db0a1a85 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index cc5e751c9b..70119f154a 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file