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Date: Wed, 1 Nov 2023 18:08:22 +0800 Message-Id: <20231101100822.2126091-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} Ready push to trunk. gcc/ChangeLog: * config/i386/mmx.md (cmlav4hf4): New expander. (cmla_conjv4hf4): Ditto. (cmulv4hf3): Ditto. (cmul_conjv4hf3): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/part-vect-complexhf.c: New test. --- gcc/config/i386/mmx.md | 86 +++++++++++++++++++ .../gcc.target/i386/part-vect-complexhf.c | 40 +++++++++ 2 files changed, 126 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-complexhf.c diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 2b97bb8fa98..ba81ff72551 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -2622,6 +2622,92 @@ (define_expand "vec_fmsubaddv4hf4" DONE; }) +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Parallel half-precision floating point complex type operations +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_expand "cmlav4hf4" + [(match_operand:V4HF 0 "register_operand") + (match_operand:V4HF 1 "vector_operand") + (match_operand:V4HF 2 "vector_operand") + (match_operand:V4HF 3 "vector_operand")] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + rtx op3 = gen_reg_rtx (V8HFmode); + rtx op2 = gen_reg_rtx (V8HFmode); + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_movq_v4hf_to_sse (op3, operands[3])); + emit_insn (gen_movq_v4hf_to_sse (op2, operands[2])); + emit_insn (gen_movq_v4hf_to_sse (op1, operands[1])); + + emit_insn (gen_cmlav8hf4 (op0, op1, op2, op3)); + + emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode)); + DONE; +}) + +(define_expand "cmla_conjv4hf4" + [(match_operand:V4HF 0 "register_operand") + (match_operand:V4HF 1 "vector_operand") + (match_operand:V4HF 2 "vector_operand") + (match_operand:V4HF 3 "vector_operand")] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + rtx op3 = gen_reg_rtx (V8HFmode); + rtx op2 = gen_reg_rtx (V8HFmode); + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_movq_v4hf_to_sse (op3, operands[3])); + emit_insn (gen_movq_v4hf_to_sse (op2, operands[2])); + emit_insn (gen_movq_v4hf_to_sse (op1, operands[1])); + + emit_insn (gen_cmla_conjv8hf4 (op0, op1, op2, op3)); + + emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode)); + DONE; +}) + +(define_expand "cmulv4hf3" + [(match_operand:V4HF 0 "register_operand") + (match_operand:V4HF 1 "vector_operand") + (match_operand:V4HF 2 "vector_operand")] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + rtx op2 = gen_reg_rtx (V8HFmode); + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_movq_v4hf_to_sse (op2, operands[2])); + emit_insn (gen_movq_v4hf_to_sse (op1, operands[1])); + + emit_insn (gen_cmulv8hf3 (op0, op1, op2)); + emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode)); + DONE; +}) + +(define_expand "cmul_conjv4hf3" + [(match_operand:V4HF 0 "register_operand") + (match_operand:V4HF 1 "vector_operand") + (match_operand:V4HF 2 "vector_operand")] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + rtx op2 = gen_reg_rtx (V8HFmode); + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_movq_v4hf_to_sse (op2, operands[2])); + emit_insn (gen_movq_v4hf_to_sse (op1, operands[1])); + + emit_insn (gen_cmul_conjv8hf3 (op0, op1, op2)); + emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode)); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel half-precision floating point conversion operations diff --git a/gcc/testsuite/gcc.target/i386/part-vect-complexhf.c b/gcc/testsuite/gcc.target/i386/part-vect-complexhf.c new file mode 100644 index 00000000000..b9f4ba2f4cf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/part-vect-complexhf.c @@ -0,0 +1,40 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O1 -ftree-vectorize -ffast-math -mavx512fp16 -mavx512vl" } */ +/* { dg-final { scan-assembler-times "vfmaddcph\[ \\t\]" 1 } } */ +/* { dg-final { scan-assembler-not "vfmadd\[123]*ph\[ \\t\]"} } */ +/* { dg-final { scan-assembler-not "vfmadd\[123]*sh\[ \\t\]"} } */ +/* { dg-final { scan-assembler-times "vfcmaddcph\[ \\t\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfcmulcph\[ \\t\]" 1 } } */ + +#include +#define TYPE _Float16 +#define N 2 + +void fma0 (_Complex TYPE *a, _Complex TYPE *b, + _Complex TYPE * __restrict c) +{ + for (int i = 0; i < N; i++) + c[i] += a[i] * b[i]; +} + +void fmaconj (_Complex TYPE a[restrict N], _Complex TYPE b[restrict N], + _Complex TYPE c[restrict N]) +{ + for (int i = 0; i < N; i++) + c[i] += a[i] * ~b[i]; +} + +void fmul (_Complex TYPE a[restrict N], _Complex TYPE b[restrict N], + _Complex TYPE c[restrict N]) +{ + for (int i = 0; i < N; i++) + c[i] = a[i] * b[i]; +} + +void fmulconj (_Complex TYPE a[restrict N], _Complex TYPE b[restrict N], + _Complex TYPE c[restrict N]) +{ + for (int i = 0; i < N; i++) + c[i] = a[i] * ~b[i]; +}