From patchwork Tue Sep 19 02:48:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 815260 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rere.qmqm.pl header.i=@rere.qmqm.pl header.b="X22x4VZu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xx6kR44Txz9rxm for ; Tue, 19 Sep 2017 12:48:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750921AbdISCsO (ORCPT ); Mon, 18 Sep 2017 22:48:14 -0400 Received: from 78-11-180-123.static.ip.netia.com.pl ([78.11.180.123]:47410 "EHLO rere.qmqm.pl" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750789AbdISCsN (ORCPT ); Mon, 18 Sep 2017 22:48:13 -0400 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 3xx6kM0YGsz4N; Tue, 19 Sep 2017 04:48:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1505789291; bh=DIuZh5qAhtpG4E3kzg4Mk96OHvaODk4uDPp29BKcS0E=; h=Date:From:Subject:To:Cc:From; b=X22x4VZu/b4YbVA4FWTbJKc1ntfOZ00qs1oSPNqiSYkRQ6fc572QSzrLxOsD4EPgr E+8mZecbwE9V8kiqy9J5eSboJNIVBK8r8+kamJF/FQDqC0+koOf9rqijYUscXQ2ds6 hw0TVzoDLAUCdfoxGTOUcZe0AFM+lvGmYCSZ0yEjIqeyZv+iiTcwaVdH/TEEq4kdaa sMwkI3Pax8zuwJttoS7USmelIcEl++sQBToMCWjD4NJClWZlqPltJu2lFNeYVQnx2F 1no4SUnmWaBWhWhZvrmdBflgaH+hLXhg/g9ol8CmXGABaZac51KiEWJu2Wt/Q7kgPi bGGu2XmVgWRqQ== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.99.2 at rere Date: Tue, 19 Sep 2017 04:48:10 +0200 Message-Id: From: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Subject: [PATCH] clk: tegra30: fix cclk_lp divisor register MIME-Version: 1.0 To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org According to comments in code and common sense, cclk_lp uses its own divisor, not cclk_g's. Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30") Signed-off-by: Michał Mirosław Acked-By: Peter De Schrijver --- drivers/clk/tegra/clk-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 8f5a3e7c3bf9..95b7df4a8abd 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -964,7 +964,7 @@ static void __init tegra30_super_clk_init(void) * U71 divider of cclk_lp. */ clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", - clk_base + SUPER_CCLKG_DIVIDER, 0, + clk_base + SUPER_CCLKLP_DIVIDER, 0, TEGRA_DIVIDER_INT, 16, 8, 1, NULL); clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);