From patchwork Sun Oct 8 02:27:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1844843 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ardngZCG; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S35gQ4pN2z1yqP for ; Sun, 8 Oct 2023 13:28:17 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E18E3385735E for ; Sun, 8 Oct 2023 02:28:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 1E8CE3858D32 for ; Sun, 8 Oct 2023 02:27:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1E8CE3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696732053; x=1728268053; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=CRXcBhhHAWe3nIBgSyMxsPso8S8lf4Jixh/ikI1h+B0=; b=ardngZCGs1ffnUHw4vR1cTi0rH3bOZ70EonChwLutYa7GV25m3dsH1pM tDj7P+PFQvpVjYP2Zat/28uKi2uncpWEL0OHyZjq+2j2UY89eoB6y1owd z7+9XOuA0l1Lgyw355Cp8/x8D/iVvtesPfMRlLquPzds8DcI11/3GuIjG OWk9QlnX9Cs6USML2R7urrzmpHbnOnZgYZRZCc915URVXdXPqTUcKwg3e 7Phe39Geht+VEeinmagZ3wkTAcnreNY/4rj/BcQmJ9YlrIW/GZLM5ttUt HAXVhg4tIymzyj+QGIite5ccg0Ido1Jho3zLCkuLWEU3G/7ztbaIUgrrQ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10856"; a="364262493" X-IronPort-AV: E=Sophos;i="6.03,207,1694761200"; d="scan'208";a="364262493" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2023 19:27:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10856"; a="876427626" X-IronPort-AV: E=Sophos;i="6.03,207,1694761200"; d="scan'208";a="876427626" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 07 Oct 2023 19:27:28 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id DE26110056F9; Sun, 8 Oct 2023 10:27:27 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH 1/2] [x86] Support smin/smax for V2HF/V4HF Date: Sun, 8 Oct 2023 10:27:26 +0800 Message-Id: <20231008022727.2896829-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Ready push to trunk. gcc/ChangeLog: * config/i386/mmx.md (VHF_32_64): New mode iterator. (3): New define_expand, merged from .. (v4hf3): .. this and (v2hf3): .. this. (movd_v2hf_to_sse_reg): New define_expand, splitted from .. (movd_v2hf_to_sse): .. this. (3): New define_expand. gcc/testsuite/ChangeLog: * gcc.target/i386/part-vect-vminmaxph-1.c: New test. * gcc.target/i386/avx512fp16-64-32-vecop-1.c: Scan-assembler only for { target { ! ia32 } }. --- gcc/config/i386/mmx.md | 74 +++++++++++-------- .../i386/avx512fp16-64-32-vecop-1.c | 8 +- .../gcc.target/i386/part-vect-vminmaxph-1.c | 36 +++++++++ 3 files changed, 83 insertions(+), 35 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-vminmaxph-1.c diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index ef578222945..77f1db265ab 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1936,25 +1936,7 @@ (define_expand "lroundv2sfv2si2" ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "v4hf3" - [(set (match_operand:V4HF 0 "register_operand") - (plusminusmult:V4HF - (match_operand:V4HF 1 "nonimmediate_operand") - (match_operand:V4HF 2 "nonimmediate_operand")))] - "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" -{ - rtx op2 = gen_reg_rtx (V8HFmode); - rtx op1 = gen_reg_rtx (V8HFmode); - rtx op0 = gen_reg_rtx (V8HFmode); - - emit_insn (gen_movq_v4hf_to_sse (op2, operands[2])); - emit_insn (gen_movq_v4hf_to_sse (op1, operands[1])); - - emit_insn (gen_v8hf3 (op0, op1, op2)); - - emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode)); - DONE; -}) +(define_mode_iterator VHF_32_64 [V2HF (V4HF "TARGET_MMX_WITH_SSE")]) (define_expand "divv4hf3" [(set (match_operand:V4HF 0 "register_operand") @@ -1976,39 +1958,50 @@ (define_expand "divv4hf3" DONE; }) +(define_mode_attr mov_to_sse_suffix [(V2HF "d") (V4HF "q")]) (define_expand "movd_v2hf_to_sse" [(set (match_operand:V8HF 0 "register_operand") (vec_merge:V8HF (vec_duplicate:V8HF (match_operand:V2HF 1 "nonimmediate_operand")) - (match_operand:V8HF 2 "reg_or_0_operand") + (match_dup 2) (const_int 3)))] "TARGET_SSE" { - if (!flag_trapping_math && operands[2] == CONST0_RTX (V8HFmode)) + if (!flag_trapping_math) { rtx op1 = force_reg (V2HFmode, operands[1]); emit_move_insn (operands[0], lowpart_subreg (V8HFmode, op1, V2HFmode)); DONE; } + operands[2] = CONST0_RTX (V8HFmode); }) -(define_expand "v2hf3" - [(set (match_operand:V2HF 0 "register_operand") - (plusminusmult:V2HF - (match_operand:V2HF 1 "nonimmediate_operand") - (match_operand:V2HF 2 "nonimmediate_operand")))] +(define_expand "movd_v2hf_to_sse_reg" + [(set (match_operand:V8HF 0 "register_operand") + (vec_merge:V8HF + (vec_duplicate:V8HF + (match_operand:V2HF 1 "nonimmediate_operand")) + (match_operand:V8HF 2 "register_operand") + (const_int 3)))] + "TARGET_SSE") + +(define_expand "3" + [(set (match_operand:VHF_32_64 0 "register_operand") + (plusminusmult:VHF_32_64 + (match_operand:VHF_32_64 1 "nonimmediate_operand") + (match_operand:VHF_32_64 2 "nonimmediate_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" { rtx op2 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode); rtx op0 = gen_reg_rtx (V8HFmode); - emit_insn (gen_movd_v2hf_to_sse (op2, operands[2], CONST0_RTX (V8HFmode))); - emit_insn (gen_movd_v2hf_to_sse (op1, operands[1], CONST0_RTX (V8HFmode))); + emit_insn (gen_mov__to_sse (op2, operands[2])); + emit_insn (gen_mov__to_sse (op1, operands[1])); emit_insn (gen_v8hf3 (op0, op1, op2)); - emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode)); + emit_move_insn (operands[0], lowpart_subreg (mode, op0, V8HFmode)); DONE; }) @@ -2023,15 +2016,34 @@ (define_expand "divv2hf3" rtx op1 = gen_reg_rtx (V8HFmode); rtx op0 = gen_reg_rtx (V8HFmode); - emit_insn (gen_movd_v2hf_to_sse (op2, operands[2], + emit_insn (gen_movd_v2hf_to_sse_reg (op2, operands[2], force_reg (V8HFmode, CONST1_RTX (V8HFmode)))); - emit_insn (gen_movd_v2hf_to_sse (op1, operands[1], CONST0_RTX (V8HFmode))); + emit_insn (gen_movd_v2hf_to_sse (op1, operands[1])); emit_insn (gen_divv8hf3 (op0, op1, op2)); emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode)); DONE; }) +(define_expand "3" + [(set (match_operand:VHF_32_64 0 "register_operand") + (smaxmin:VHF_32_64 + (match_operand:VHF_32_64 1 "nonimmediate_operand") + (match_operand:VHF_32_64 2 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" +{ + rtx op2 = gen_reg_rtx (V8HFmode); + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_mov__to_sse (op2, operands[2])); + emit_insn (gen_mov__to_sse (op1, operands[1])); + + emit_insn (gen_v8hf3 (op0, op1, op2)); + + emit_move_insn (operands[0], lowpart_subreg (mode, op0, V8HFmode)); + DONE; +}) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-64-32-vecop-1.c b/gcc/testsuite/gcc.target/i386/avx512fp16-64-32-vecop-1.c index 754e909d77b..de883545d6d 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fp16-64-32-vecop-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-64-32-vecop-1.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mavx512fp16 -mavx512vl" } */ -/* { dg-final { scan-assembler-times "vaddph" 2 } } */ -/* { dg-final { scan-assembler-times "vsubph" 2 } } */ -/* { dg-final { scan-assembler-times "vmulph" 2 } } */ -/* { dg-final { scan-assembler-times "vdivph" 2 } } */ +/* { dg-final { scan-assembler-times "vaddph" 2 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "vsubph" 2 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "vmulph" 2 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "vdivph" 2 { target { ! ia32 } } } } */ #define DO_PRAGMA(X) _Pragma(#X) diff --git a/gcc/testsuite/gcc.target/i386/part-vect-vminmaxph-1.c b/gcc/testsuite/gcc.target/i386/part-vect-vminmaxph-1.c new file mode 100644 index 00000000000..a0c98441de0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/part-vect-vminmaxph-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -Ofast" } */ +/* { dg-final { scan-assembler-times {(?n)vmaxph[ \t].*%xmm[0-9]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vminph[ \t].*%xmm[0-9]} 2 } } */ + +void +foo16_max (_Float16* a, _Float16* b, _Float16* __restrict c) +{ + c[0] = __builtin_fmaxf16 (a[0], b[0]); + c[1] = __builtin_fmaxf16 (a[1], b[1]); +} + +void +foo32_max(_Float16* a, _Float16* b, _Float16* __restrict c) +{ + c[0] = __builtin_fmaxf16 (a[0], b[0]); + c[1] = __builtin_fmaxf16 (a[1], b[1]); + c[2] = __builtin_fmaxf16 (a[2], b[2]); + c[3] = __builtin_fmaxf16 (a[3], b[3]); +} + +void +foo16_min (_Float16* a, _Float16* b, _Float16* __restrict c) +{ + c[0] = __builtin_fminf16 (a[0], b[0]); + c[1] = __builtin_fminf16 (a[1], b[1]); +} + +void +foo32_min(_Float16* a, _Float16* b, _Float16* __restrict c) +{ + c[0] = __builtin_fminf16 (a[0], b[0]); + c[1] = __builtin_fminf16 (a[1], b[1]); + c[2] = __builtin_fminf16 (a[2], b[2]); + c[3] = __builtin_fminf16 (a[3], b[3]); +} From patchwork Sun Oct 8 02:27:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1844844 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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d="scan'208";a="364262495" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2023 19:27:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10856"; a="876427625" X-IronPort-AV: E=Sophos;i="6.03,207,1694761200"; d="scan'208";a="876427625" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 07 Oct 2023 19:27:28 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id E08CB100571A; Sun, 8 Oct 2023 10:27:27 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH 2/2] Support signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V2HF/V4HF. Date: Sun, 8 Oct 2023 10:27:27 +0800 Message-Id: <20231008022727.2896829-2-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231008022727.2896829-1-hongtao.liu@intel.com> References: <20231008022727.2896829-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Ready push to trunk. gcc/ChangeLog: * config/i386/i386.cc (ix86_build_const_vector): Handle V2HF and V4HFmode. (ix86_build_signbit_mask): Ditto. * config/i386/mmx.md (mmxintvecmode): Ditto. (2): New define_expand. (*mmx_): New define_insn_and_split. (*mmx_nabs2): Ditto. (*mmx_andnot3): New define_insn. (3): Ditto. (copysign3): New define_expand. (xorsign3): Ditto. (signbit2): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/part-vect-absneghf.c: New test. * gcc.target/i386/part-vect-copysignhf.c: New test. * gcc.target/i386/part-vect-xorsignhf.c: New test. --- gcc/config/i386/i386.cc | 4 + gcc/config/i386/mmx.md | 114 +++++++++++++++++- .../gcc.target/i386/part-vect-absneghf.c | 91 ++++++++++++++ .../gcc.target/i386/part-vect-copysignhf.c | 60 +++++++++ .../gcc.target/i386/part-vect-vminmaxph-1.c | 4 +- .../gcc.target/i386/part-vect-xorsignhf.c | 60 +++++++++ 6 files changed, 330 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-absneghf.c create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-copysignhf.c create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-xorsignhf.c diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 9557bffd092..46326d3c82e 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -15752,6 +15752,8 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value) case E_V2DImode: gcc_assert (vect); /* FALLTHRU */ + case E_V2HFmode: + case E_V4HFmode: case E_V8HFmode: case E_V16HFmode: case E_V32HFmode: @@ -15793,6 +15795,8 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert) switch (mode) { + case E_V2HFmode: + case E_V4HFmode: case E_V8HFmode: case E_V16HFmode: case E_V32HFmode: diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 77f1db265ab..c68a3d6fe43 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -99,7 +99,8 @@ (define_mode_attr mmxdoublemode ;; Mapping of vector float modes to an integer mode of the same size (define_mode_attr mmxintvecmode - [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")]) + [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI") + (V4HF "V4HF") (V2HF "V2HI")]) (define_mode_attr mmxintvecmodelower [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")]) @@ -2045,6 +2046,117 @@ (define_expand "3" DONE; }) +(define_expand "2" + [(set (match_operand:VHF_32_64 0 "register_operand") + (absneg:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand")))] + "TARGET_SSE" + "ix86_expand_fp_absneg_operator (, mode, operands); DONE;") + +(define_insn_and_split "*mmx_" + [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x,x") + (absneg:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand" "0,x,x"))) + (use (match_operand:VHF_32_64 2 "register_operand" "x,0,x"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) + (: (match_dup 1) (match_dup 2)))] +{ + if (!TARGET_AVX && operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); +} + [(set_attr "isa" "noavx,noavx,avx")]) + +(define_insn_and_split "*mmx_nabs2" + [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x,x") + (neg:VHF_32_64 + (abs:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand" "0,x,x")))) + (use (match_operand:VHF_32_64 2 "register_operand" "x,0,x"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) + (ior: (match_dup 1) (match_dup 2)))]) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Parallel half-precision floating point logical operations +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn "*mmx_andnot3" + [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x") + (and:VHF_32_64 + (not:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand" "0,x")) + (match_operand:VHF_32_64 2 "register_operand" "x,x")))] + "TARGET_SSE" + "@ + andnps\t{%2, %0|%0, %2} + vandnps\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") + (set_attr "prefix" "orig,vex") + (set_attr "mode" "V4SF")]) + +(define_insn "3" + [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x") + (any_logic:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand" "%0,x") + (match_operand:VHF_32_64 2 "register_operand" " x,x")))] + "TARGET_SSE" + "@ + ps\t{%2, %0|%0, %2} + vps\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog,sselog") + (set_attr "prefix" "orig,vex") + (set_attr "mode" "V4SF")]) + +(define_expand "copysign3" + [(set (match_dup 4) + (and:VHF_32_64 + (not:VHF_32_64 (match_dup 3)) + (match_operand:VHF_32_64 1 "register_operand"))) + (set (match_dup 5) + (and:VHF_32_64 (match_dup 3) + (match_operand:VHF_32_64 2 "register_operand"))) + (set (match_operand:VHF_32_64 0 "register_operand") + (ior:VHF_32_64 (match_dup 4) (match_dup 5)))] + "TARGET_SSE" +{ + operands[3] = ix86_build_signbit_mask (mode, true, false); + + operands[4] = gen_reg_rtx (mode); + operands[5] = gen_reg_rtx (mode); +}) + +(define_expand "xorsign3" + [(set (match_dup 4) + (and:VHF_32_64 (match_dup 3) + (match_operand:VHF_32_64 2 "register_operand"))) + (set (match_operand:VHF_32_64 0 "register_operand") + (xor:VHF_32_64 (match_dup 4) + (match_operand:VHF_32_64 1 "register_operand")))] + "TARGET_SSE" +{ + operands[3] = ix86_build_signbit_mask (mode, true, false); + + operands[4] = gen_reg_rtx (mode); +}) + +(define_expand "signbit2" + [(set (match_operand: 0 "register_operand") + (lshiftrt: + (subreg: + (match_operand:VHF_32_64 1 "register_operand") 0) + (match_dup 2)))] + "TARGET_SSE2" + "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (mode)-1);") + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral arithmetic diff --git a/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c b/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c new file mode 100644 index 00000000000..48aed14d604 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c @@ -0,0 +1,91 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-slp-details -fdump-tree-optimized" } */ + +extern void abort (); + +static void do_test (void); + +#define DO_TEST do_test +#define AVX512FP16 +#include "avx512-check.h" + +#define N 16 +_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f, + -12.5f, -15.6f, -18.7f, -21.8f, + 24.9f, 27.1f, 30.2f, 33.3f, + 36.4f, 39.5f, 42.6f, 45.7f}; +_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f, + -9.0f, 1.0f, -2.0f, 3.0f, + -4.0f, -5.0f, 6.0f, 7.0f, + -8.0f, -9.0f, 10.0f, 11.0f}; +_Float16 r[N]; + +void +__attribute__((noipa,noinline,optimize("O2"))) +abs_32 (void) +{ + r[0] = __builtin_fabsf16 (b[0]); + r[1] = __builtin_fabsf16 (b[1]); +} + +void +__attribute__((noipa,noinline,optimize("O2"))) +abs_64 (void) +{ + r[0] = __builtin_fabsf16 (b[0]); + r[1] = __builtin_fabsf16 (b[1]); + r[2] = __builtin_fabsf16 (b[2]); + r[3] = __builtin_fabsf16 (b[3]); +} + +void +__attribute__((noipa,noinline,optimize("O2"))) +neg_32 (void) +{ + r[0] = -b[0]; + r[1] = -b[1]; +} + +void +__attribute__((noipa,noinline,optimize("O2"))) +neg_64 (void) +{ + r[0] = -b[0]; + r[1] = -b[1]; + r[2] = -b[2]; + r[3] = -b[3]; +} + +static void +__attribute__ ((noinline, noclone)) +do_test (void) +{ + abs_32 (); + /* check results: */ + for (int i = 0; i != 2; i++) + if (r[i] != __builtin_fabsf16 (b[i])) + abort (); + + abs_64 (); + /* check results: */ + for (int i = 0; i != 4; i++) + if (r[i] != __builtin_fabsf16 (b[i])) + abort (); + + neg_32 (); + /* check results: */ + for (int i = 0; i != 2; i++) + if (r[i] != -b[i]) + abort (); + + neg_64 (); + /* check results: */ + for (int i = 0; i != 4; i++) + if (r[i] != -b[i]) + abort (); +} + +/* { dg-final { scan-tree-dump-times "vectorized using 8 byte vectors" 2 "slp2" } } */ +/* { dg-final { scan-tree-dump-times "vectorized using 4 byte vectors" 2 "slp2" } } */ +/* { dg-final { scan-tree-dump-times {(?n)ABS_EXPR