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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id 11-20020a05600c020b00b003fe2b081661sm3408261wmi.30.2023.09.30.06.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 06:41:18 -0700 (PDT) From: Bryan O'Donoghue To: andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jonathan@marek.ca, quic_tdas@quicinc.com, vladimir.zapolskiy@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bryan.odonoghue@linaro.org Subject: [PATCH v2 1/5] dt-bindings: clock: qcom,camcc-common.yaml: Add a common file for camcc Date: Sat, 30 Sep 2023 14:41:10 +0100 Message-Id: <20230930134114.1816590-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230930134114.1816590-1-bryan.odonoghue@linaro.org> References: <20230930134114.1816590-1-bryan.odonoghue@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Various of the camcc bindings are repeated serially. Aggregate the common defintions into one place declaring common required in one place also. Signed-off-by: Bryan O'Donoghue --- .../bindings/clock/qcom,camcc-common.yaml | 44 +++++++++++++++++++ .../bindings/clock/qcom,camcc-sm8250.yaml | 32 ++------------ .../bindings/clock/qcom,sc7180-camcc.yaml | 23 ++-------- .../bindings/clock/qcom,sc7280-camcc.yaml | 23 ++-------- .../bindings/clock/qcom,sdm845-camcc.yaml | 23 ++-------- .../bindings/clock/qcom,sm6350-camcc.yaml | 13 ++---- .../bindings/clock/qcom,sm8450-camcc.yaml | 33 ++------------ 7 files changed, 67 insertions(+), 124 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,camcc-common.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc-common.yaml b/Documentation/devicetree/bindings/clock/qcom,camcc-common.yaml new file mode 100644 index 000000000000..ce0140985fe7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,camcc-common.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,camcc-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller common properties + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: true + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + power-domains: + maxItems: 1 + description: + A phandle and PM domain specifier for the MMCX power domain. + + required-opps: + maxItems: 1 + description: + OPP node describing required MMCX performance point. + +required: + - compatible + - clocks + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml index 426335a2841c..e31b20076643 100644 --- a/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml @@ -15,6 +15,9 @@ description: | See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h +allOf: + - $ref: qcom,camcc-common.yaml# + properties: compatible: const: qcom,sm8250-camcc @@ -33,37 +36,10 @@ properties: - const: bi_tcxo_ao - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - power-domains: - items: - - description: MMCX power domain - - reg: - maxItems: 1 - - required-opps: - maxItems: 1 - description: - OPP node describing required MMCX performance point. - required: - - compatible - - reg - - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml index 2dfc2a4f1918..40cef12d67e0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml @@ -15,6 +15,9 @@ description: | See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h +allOf: + - $ref: qcom,camcc-common.yaml# + properties: compatible: const: qcom,sc7180-camcc @@ -31,28 +34,10 @@ properties: - const: iface - const: xo - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - - compatible - - reg - - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml index 01feef1cab0a..057f93b4971b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml @@ -15,6 +15,9 @@ description: | See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h +allOf: + - $ref: qcom,camcc-common.yaml# + properties: compatible: const: qcom,sc7280-camcc @@ -31,28 +34,10 @@ properties: - const: bi_tcxo_ao - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - - compatible - - reg - - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml index 91d1f7918037..553fae55bc66 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml @@ -15,6 +15,9 @@ description: | See also:: include/dt-bindings/clock/qcom,camcc-sm845.h +allOf: + - $ref: qcom,camcc-common.yaml# + properties: compatible: const: qcom,sdm845-camcc @@ -27,28 +30,10 @@ properties: items: - const: bi_tcxo - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - - compatible - - reg - - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml index fd6658cb793d..5a004396659b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml @@ -15,6 +15,9 @@ description: | See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h +allOf: + - $ref: qcom,camcc-common.yaml# + properties: compatible: const: qcom,sm6350-camcc @@ -23,16 +26,6 @@ properties: items: - description: Board XO source - reg: - maxItems: 1 - -required: - - compatible - - clocks - -allOf: - - $ref: qcom,gcc.yaml# - unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index dc3c18e4ead7..5db7bd8424d8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -17,6 +17,9 @@ description: | include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h +allOf: + - $ref: qcom,camcc-common.yaml# + properties: compatible: enum: @@ -30,39 +33,11 @@ properties: - description: Board active XO source - description: Sleep clock source - power-domains: - maxItems: 1 - description: - A phandle and PM domain specifier for the MMCX power domain. - - required-opps: - maxItems: 1 - description: - A phandle to an OPP node describing required MMCX performance point. - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - - compatible - - reg - - clocks - power-domains - required-opps - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | From patchwork Sat Sep 30 13:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 1841592 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=qm3DR/EK; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:40f1:3f00::1; helo=sy.mirrors.kernel.org; envelope-from=devicetree+bounces-4796-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org [IPv6:2604:1380:40f1:3f00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RySzr4RbXz1ypb for ; Sat, 30 Sep 2023 23:41:28 +1000 (AEST) Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sy.mirrors.kernel.org (Postfix) with ESMTP id 5C5EDB20A66 for ; Sat, 30 Sep 2023 13:41:27 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EF45A12B81; Sat, 30 Sep 2023 13:41:25 +0000 (UTC) X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 322B211727 for ; Sat, 30 Sep 2023 13:41:24 +0000 (UTC) Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0836EFA for ; Sat, 30 Sep 2023 06:41:22 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4054496bde3so132982955e9.1 for ; Sat, 30 Sep 2023 06:41:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696081280; x=1696686080; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rjipoyU4KPDX/dyi7xPGlEZeRzfxRz0JAyHv25EP1WM=; b=qm3DR/EKywPSVZlYSWwCaxkuQfJzJIkDeG88evtTzkjPI4zceDNBykGkBYkPY/S9Wq 4UFNP3DChVT7MQ1wGJ0tVdDcZR0DuJ94aLS6oMoTSbwt1Wb/9Aa+xBoL7Iv8VQceFZ/h ofImezpZXRy8ecv2ovKL8H7kjkVaqwYtwkJoSWga7sYmvd3EHqyX9KGgRwNaK4BtD3wJ slhbeWSFQuBHKKvr0hq9+PEAvvMOtrujRZZ64FpVV+c/x/jV09gnvS7c7RCn7mpcCayv viJd/fcmv9QShdqSsls68SXkhbLKMheuU2Lir5CnKiWm5drMoKvPpigHBkMk7rLwnarn EzLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696081280; x=1696686080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rjipoyU4KPDX/dyi7xPGlEZeRzfxRz0JAyHv25EP1WM=; b=LycFwas5EwXce0ok1pF84wC7t0LyLdy+fmDlPRW8QEYbTO4jUn0jZDPkIPFByXtspP Ob30vuTxHItNf4A3aiarT6SueQwyDKdJgEw/xqkzRZp5I4hWGedhuv+gLAtJPn/Jv12q 91R2Ykjum3l5MtoNFyHA4aQePcsp5dv0U7Rl7QIQarCxOAyBORdm/CkrcLemHvFb/SRI RcJmDsiD/kpwIpdzfv2ld6mcUJXcHwHg/41whM83BTZcjR7Nu52+Eh1sFZ3l/2ijUyCk Lk+EZswxHuWgQCp87ERrmDRwQjZswed6Jq6B3CmnRuzK5Pc7DwbToXfgsoWZrh9D+hbR xqVw== X-Gm-Message-State: AOJu0YwLYKlgmRVOBltYXAmhSabyT2HAsFUj98/pyDzvQ/Snf82IK0kj PQxw+VFJPdubh1oFC4PwyiEub9pacDgzlUuziOEOZg== X-Google-Smtp-Source: AGHT+IE7E0TbrNQMPPUrmKZ+rRGVXAyIx+xyx6Q1NaNcKAqz2fZJGpO6+oqAFOhV+nrQ5hivTzIjmA== X-Received: by 2002:a05:600c:c8:b0:405:514d:eb0e with SMTP id u8-20020a05600c00c800b00405514deb0emr7292565wmm.19.1696081280469; Sat, 30 Sep 2023 06:41:20 -0700 (PDT) Received: from x13s-linux.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id 11-20020a05600c020b00b003fe2b081661sm3408261wmi.30.2023.09.30.06.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 06:41:20 -0700 (PDT) From: Bryan O'Donoghue To: andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jonathan@marek.ca, quic_tdas@quicinc.com, vladimir.zapolskiy@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bryan.odonoghue@linaro.org Subject: [PATCH v2 2/5] dt-bindings: clock: Add SM8550 CAMCC yaml Date: Sat, 30 Sep 2023 14:41:11 +0100 Message-Id: <20230930134114.1816590-3-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230930134114.1816590-1-bryan.odonoghue@linaro.org> References: <20230930134114.1816590-1-bryan.odonoghue@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net The SM8550 should have its own yaml description file, not be listed as a compatible string of the SM8450 CAMCC driver since SM8450 and SM8550 have separate CAMCC drivers. Signed-off-by: Bryan O'Donoghue --- .../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-- .../bindings/clock/qcom,sm8550-camcc.yaml | 56 +++++++++++++++++++ 2 files changed, 58 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-camcc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 5db7bd8424d8..9d16acc53312 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -13,18 +13,14 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM8450. - See also:: - include/dt-bindings/clock/qcom,sm8450-camcc.h - include/dt-bindings/clock/qcom,sm8550-camcc.h + See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h allOf: - $ref: qcom,camcc-common.yaml# properties: compatible: - enum: - - qcom,sm8450-camcc - - qcom,sm8550-camcc + const: qcom,sm8450-camcc clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-camcc.yaml new file mode 100644 index 000000000000..93534632c0a2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-camcc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM8550 + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SM8550. + + See also:: include/dt-bindings/clock/qcom,sm8550-camcc.h + +allOf: + - $ref: qcom,camcc-common.yaml# + +properties: + compatible: + const: qcom,sm8550-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + +required: + - power-domains + - required-opps + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ade0000 { + compatible = "qcom,sm8550-camcc"; + reg = <0xade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... 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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id 11-20020a05600c020b00b003fe2b081661sm3408261wmi.30.2023.09.30.06.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 06:41:21 -0700 (PDT) From: Bryan O'Donoghue To: andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jonathan@marek.ca, quic_tdas@quicinc.com, vladimir.zapolskiy@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bryan.odonoghue@linaro.org Subject: [PATCH v2 3/5] dt-bindings: clock: Add SC8280XP CAMCC Date: Sat, 30 Sep 2023 14:41:12 +0100 Message-Id: <20230930134114.1816590-4-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230930134114.1816590-1-bryan.odonoghue@linaro.org> References: <20230930134114.1816590-1-bryan.odonoghue@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add device tree bindings for the camera clock controller on Qualcomm SC8280XP platform. Signed-off-by: Bryan O'Donoghue --- .../bindings/clock/qcom,sc8280xp-camcc.yaml | 57 ++++++ .../dt-bindings/clock/qcom,sc8280xp-camcc.h | 179 ++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-camcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sc8280xp-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-camcc.yaml new file mode 100644 index 000000000000..12017d209b8b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-camcc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SC8280XP + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,sc8280xp-camcc.h + +allOf: + - $ref: qcom,camcc-common.yaml# + +properties: + compatible: + - const: qcom,sc8280xp-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + +required: + - power-domains + - required-opps + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ade0000 { + compatible = "qcom,sc8280xp-camcc"; + reg = <0xade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sc8280xp-camcc.h b/include/dt-bindings/clock/qcom,sc8280xp-camcc.h new file mode 100644 index 000000000000..867fbd146ee4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8280xp-camcc.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC8280XP_H + +/* CAM_CC clocks */ +#define CAM_CC_PLL0 0 +#define CAM_CC_PLL0_OUT_EVEN 1 +#define CAM_CC_PLL0_OUT_ODD 2 +#define CAM_CC_PLL1 3 +#define CAM_CC_PLL1_OUT_EVEN 4 +#define CAM_CC_PLL2 5 +#define CAM_CC_PLL3 6 +#define CAM_CC_PLL3_OUT_EVEN 7 +#define CAM_CC_PLL4 8 +#define CAM_CC_PLL4_OUT_EVEN 9 +#define CAM_CC_PLL5 10 +#define CAM_CC_PLL5_OUT_EVEN 11 +#define CAM_CC_PLL6 12 +#define CAM_CC_PLL6_OUT_EVEN 13 +#define CAM_CC_PLL7 14 +#define CAM_CC_PLL7_OUT_EVEN 15 +#define CAM_CC_PLL7_OUT_ODD 16 +#define CAM_CC_BPS_AHB_CLK 17 +#define CAM_CC_BPS_AREG_CLK 18 +#define CAM_CC_BPS_AXI_CLK 19 +#define CAM_CC_BPS_CLK 20 +#define CAM_CC_BPS_CLK_SRC 21 +#define CAM_CC_CAMNOC_AXI_CLK 22 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 23 +#define CAM_CC_CAMNOC_DCD_XO_CLK 24 +#define CAM_CC_CCI_0_CLK 25 +#define CAM_CC_CCI_0_CLK_SRC 26 +#define CAM_CC_CCI_1_CLK 27 +#define CAM_CC_CCI_1_CLK_SRC 28 +#define CAM_CC_CCI_2_CLK 29 +#define CAM_CC_CCI_2_CLK_SRC 30 +#define CAM_CC_CCI_3_CLK 31 +#define CAM_CC_CCI_3_CLK_SRC 32 +#define CAM_CC_CORE_AHB_CLK 33 +#define CAM_CC_CPAS_AHB_CLK 34 +#define CAM_CC_CPHY_RX_CLK_SRC 35 +#define CAM_CC_CSI0PHYTIMER_CLK 36 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI1PHYTIMER_CLK 38 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI2PHYTIMER_CLK 40 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSI3PHYTIMER_CLK 42 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 43 +#define CAM_CC_CSIPHY0_CLK 44 +#define CAM_CC_CSIPHY1_CLK 45 +#define CAM_CC_CSIPHY2_CLK 46 +#define CAM_CC_CSIPHY3_CLK 47 +#define CAM_CC_FAST_AHB_CLK_SRC 48 +#define CAM_CC_GDSC_CLK 49 +#define CAM_CC_ICP_AHB_CLK 50 +#define CAM_CC_ICP_CLK 51 +#define CAM_CC_ICP_CLK_SRC 52 +#define CAM_CC_IFE_0_AXI_CLK 53 +#define CAM_CC_IFE_0_CLK 54 +#define CAM_CC_IFE_0_CLK_SRC 55 +#define CAM_CC_IFE_0_CPHY_RX_CLK 56 +#define CAM_CC_IFE_0_CSID_CLK 57 +#define CAM_CC_IFE_0_CSID_CLK_SRC 58 +#define CAM_CC_IFE_0_DSP_CLK 59 +#define CAM_CC_IFE_1_AXI_CLK 60 +#define CAM_CC_IFE_1_CLK 61 +#define CAM_CC_IFE_1_CLK_SRC 62 +#define CAM_CC_IFE_1_CPHY_RX_CLK 63 +#define CAM_CC_IFE_1_CSID_CLK 64 +#define CAM_CC_IFE_1_CSID_CLK_SRC 65 +#define CAM_CC_IFE_1_DSP_CLK 66 +#define CAM_CC_IFE_2_AXI_CLK 67 +#define CAM_CC_IFE_2_CLK 68 +#define CAM_CC_IFE_2_CLK_SRC 69 +#define CAM_CC_IFE_2_CPHY_RX_CLK 70 +#define CAM_CC_IFE_2_CSID_CLK 71 +#define CAM_CC_IFE_2_CSID_CLK_SRC 72 +#define CAM_CC_IFE_2_DSP_CLK 73 +#define CAM_CC_IFE_3_AXI_CLK 74 +#define CAM_CC_IFE_3_CLK 75 +#define CAM_CC_IFE_3_CLK_SRC 76 +#define CAM_CC_IFE_3_CPHY_RX_CLK 77 +#define CAM_CC_IFE_3_CSID_CLK 78 +#define CAM_CC_IFE_3_CSID_CLK_SRC 79 +#define CAM_CC_IFE_3_DSP_CLK 80 +#define CAM_CC_IFE_LITE_0_CLK 81 +#define CAM_CC_IFE_LITE_0_CLK_SRC 82 +#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 83 +#define CAM_CC_IFE_LITE_0_CSID_CLK 84 +#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 85 +#define CAM_CC_IFE_LITE_1_CLK 86 +#define CAM_CC_IFE_LITE_1_CLK_SRC 87 +#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 88 +#define CAM_CC_IFE_LITE_1_CSID_CLK 89 +#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 90 +#define CAM_CC_IFE_LITE_2_CLK 91 +#define CAM_CC_IFE_LITE_2_CLK_SRC 92 +#define CAM_CC_IFE_LITE_2_CPHY_RX_CLK 93 +#define CAM_CC_IFE_LITE_2_CSID_CLK 94 +#define CAM_CC_IFE_LITE_2_CSID_CLK_SRC 95 +#define CAM_CC_IFE_LITE_3_CLK 96 +#define CAM_CC_IFE_LITE_3_CLK_SRC 97 +#define CAM_CC_IFE_LITE_3_CPHY_RX_CLK 98 +#define CAM_CC_IFE_LITE_3_CSID_CLK 99 +#define CAM_CC_IFE_LITE_3_CSID_CLK_SRC 100 +#define CAM_CC_IPE_0_AHB_CLK 101 +#define CAM_CC_IPE_0_AREG_CLK 102 +#define CAM_CC_IPE_0_AXI_CLK 103 +#define CAM_CC_IPE_0_CLK 104 +#define CAM_CC_IPE_0_CLK_SRC 105 +#define CAM_CC_IPE_1_AHB_CLK 106 +#define CAM_CC_IPE_1_AREG_CLK 107 +#define CAM_CC_IPE_1_AXI_CLK 108 +#define CAM_CC_IPE_1_CLK 109 +#define CAM_CC_JPEG_CLK 110 +#define CAM_CC_JPEG_CLK_SRC 111 +#define CAM_CC_LRME_CLK 112 +#define CAM_CC_LRME_CLK_SRC 113 +#define CAM_CC_MCLK0_CLK 114 +#define CAM_CC_MCLK0_CLK_SRC 115 +#define CAM_CC_MCLK1_CLK 116 +#define CAM_CC_MCLK1_CLK_SRC 117 +#define CAM_CC_MCLK2_CLK 118 +#define CAM_CC_MCLK2_CLK_SRC 119 +#define CAM_CC_MCLK3_CLK 120 +#define CAM_CC_MCLK3_CLK_SRC 121 +#define CAM_CC_MCLK4_CLK 122 +#define CAM_CC_MCLK4_CLK_SRC 123 +#define CAM_CC_MCLK5_CLK 124 +#define CAM_CC_MCLK5_CLK_SRC 125 +#define CAM_CC_MCLK6_CLK 126 +#define CAM_CC_MCLK6_CLK_SRC 127 +#define CAM_CC_MCLK7_CLK 128 +#define CAM_CC_MCLK7_CLK_SRC 129 +#define CAM_CC_SLEEP_CLK 130 +#define CAM_CC_SLEEP_CLK_SRC 131 +#define CAM_CC_SLOW_AHB_CLK_SRC 132 +#define CAM_CC_XO_CLK_SRC 133 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_CAMNOC_BCR 1 +#define CAM_CC_CCI_BCR 2 +#define CAM_CC_CPAS_BCR 3 +#define CAM_CC_CSI0PHY_BCR 4 +#define CAM_CC_CSI1PHY_BCR 5 +#define CAM_CC_CSI2PHY_BCR 6 +#define CAM_CC_CSI3PHY_BCR 7 +#define CAM_CC_ICP_BCR 8 +#define CAM_CC_IFE_0_BCR 9 +#define CAM_CC_IFE_1_BCR 10 +#define CAM_CC_IFE_2_BCR 11 +#define CAM_CC_IFE_3_BCR 12 +#define CAM_CC_IFE_LITE_0_BCR 13 +#define CAM_CC_IFE_LITE_1_BCR 14 +#define CAM_CC_IFE_LITE_2_BCR 15 +#define CAM_CC_IFE_LITE_3_BCR 16 +#define CAM_CC_IPE_0_BCR 17 +#define CAM_CC_IPE_1_BCR 18 +#define CAM_CC_JPEG_BCR 19 +#define CAM_CC_LRME_BCR 20 + +/* CAM_CC GDSCRs */ +#define BPS_GDSC 0 +#define IFE_0_GDSC 1 +#define IFE_1_GDSC 2 +#define IFE_2_GDSC 3 +#define IFE_3_GDSC 4 +#define IPE_0_GDSC 5 +#define IPE_1_GDSC 6 +#define TITAN_TOP_GDSC 7 + +#endif