From patchwork Wed Sep 27 03:07:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Xu X-Patchwork-Id: 1839993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RwM4P2kP8z1ypJ for ; Wed, 27 Sep 2023 13:08:04 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EE9493852766 for ; Wed, 27 Sep 2023 03:08:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by sourceware.org (Postfix) with ESMTP id CE6B63858C74 for ; Wed, 27 Sep 2023 03:07:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CE6B63858C74 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgDXdcV+nBNlxiVNAA--.10796S4; Wed, 27 Sep 2023 11:07:42 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, xuli Subject: [PATCH] RISC-V: Bugfix for RTL check[PR111533] Date: Wed, 27 Sep 2023 03:07:41 +0000 Message-Id: <20230927030741.26669-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: EwgMCgDXdcV+nBNlxiVNAA--.10796S4 X-Coremail-Antispam: 1UD129KBjvJXoWxZFyDJF1UZw1xZry5Gr1xZrb_yoW5Zr43pa yDKr4ayFWrCFn3Ww47tFW5Jr1rJwn3Krn0krZ5Ary7Aa1DZrWq9Fs8t3Wavr45WFs5Wrsr Cw1akrWj93WUCa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkF14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4U JVW0owA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK 82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGw C20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48J MIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMI IF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E 87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUdHUDUUUUU= X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: xuli Consider the flowing situation: BB5: local_dem(RVV Insn 1, AVL(reg zero)) RVV Insn 1: vmv.s.x, AVL (const_int 1) RVV Insn 2: vredsum.vs, AVL(reg zero) vmv.s.x has vl operand, the following code will get avl (cosnt_int) from RVV Insn 1. rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); If use REGNO for const_int, the compiler will crash: during RTL pass: vsetvl res_debug.c: In function '__dn_count_labels': res_debug.c:1050:1: internal compiler error: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934 1050 | } | ^ 0x8fb169 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*) ../.././gcc/gcc/rtl.cc:770 0x1399818 rhs_regno(rtx_def const*) ../.././gcc/gcc/rtl.h:1934 0x1399818 anticipatable_occurrence_p ../.././gcc/gcc/config/riscv/riscv-vsetvl.cc:348 So in this case avl should be obtained from dem. Another issue is caused by the following code: HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; during RTL pass: expand ../../.././gcc/libgfortran/generated/matmul_c4.c: In function 'matmul_c4': ../../.././gcc/libgfortran/generated/matmul_c4.c:2906:39: internal compiler error: RTL check: expected code 'const_int', have 'const_poly_int' in expand_const_vector, at config/riscv/riscv-v.cc:1149 The builder.elt (i) can be either const_int or const_poly_int. PR target/111533 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Fix bug. * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug. --- gcc/config/riscv/riscv-v.cc | 6 ++++-- gcc/config/riscv/riscv-vsetvl.cc | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 5f738634219..fb3c55b4705 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1147,8 +1147,10 @@ expand_const_vector (rtx target, rtx src) for (unsigned int i = 0; i < v.npatterns (); ++i) { /* Calculate the diff between the target sequence and - vid sequence. */ - HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; + vid sequence. The elt (i) can be either const_int or + const_poly_int. */ + HOST_WIDE_INT diff = rtx_to_poly_int64 (builder.elt (i)).to_constant () - i; + v.quick_push (gen_int_mode (diff, v.inner_mode ())); } /* Step 2: Generate result = VID + diff. */ diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 7af33e7ea6f..27000434341 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -308,7 +308,10 @@ anticipatable_occurrence_p (const bb_info *bb, const vector_insn_info dem) { /* rs1 (avl) are not modified in the basic block prior to the VSETVL. */ rtx avl - = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); + = (has_vl_op (insn->rtl ()) && REG_P (get_vl (insn->rtl ()))) + ? get_vl (insn->rtl ()) + : dem.get_avl (); + if (dem.dirty_p ()) { gcc_assert (!vsetvl_insn_p (insn->rtl ()));