From patchwork Thu Apr 5 06:53:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 895286 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40Gtpb4lZzz9s0y for ; Thu, 5 Apr 2018 16:53:59 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MLvQ8aRJ"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40Gtpb2xBbzF1l6 for ; Thu, 5 Apr 2018 16:53:59 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MLvQ8aRJ"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MLvQ8aRJ"; dkim-atps=neutral Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40GtpB72sxzDrnp for ; Thu, 5 Apr 2018 16:53:38 +1000 (AEST) Received: by mail-pl0-x241.google.com with SMTP id 59-v6so15157381plc.13 for ; Wed, 04 Apr 2018 23:53:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=8N/+84WJAC+KG0PJYlQQIfE6UVLLagiNKHuRXnPT3kI=; b=MLvQ8aRJqPTxkD74VMviNfvEbDgOSfZQqRtP3NmxHj6unq9iGd9Y2pOAcuyC6jx3Rj Tt0N17Lpj1T7kXofCcLh967OU7ipNsmzielKLlxDIZVTPt1OZ54nnT9HeTBd1/0fhAWb 9qiWKL17TuycEmlMzKoQymD5oHHF/88xWyak1fvpnFwo2CAfcjHYzZW7Ur6fJoqTU2Ph XEUhxWrIXEyTltg7DR4K1EdvI+TdJAxtu3BqnIUIIjyKa+I9H0X9eEMTS0P5SYMklHQv 1hvFIr2SPfh3QpJ6DOV419kHu9BCWFp6FI72SgLrlQ9Z7gpC1eXfu0CYCo6m8aMw17Yp +3eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=8N/+84WJAC+KG0PJYlQQIfE6UVLLagiNKHuRXnPT3kI=; b=fWtndSxh8L7ai+zYognitZgTIjMFOwy5USW7VqtMqFPVtLbmQOQsD4IGt/L/xabEhr hsOeDPYZxiPHIQh6jrBk1Z92YpljvA1Bz6oXhGy3z72InETRPCT48Y92V3lDe90aWg7J UL83WSmun1T66I5h+Q8BppdbmpU8UbDyOpd2spMI5KgvJQ4C9dM4SvXmpgwKcnppucV+ oTjPU+iQi0tvhTUufOO5q08OzRtObZEnCd0aItjo4VHxjT9Sgf/okMQZ0KJfqRzj1TyP Ea0yzjYK9D0I3zcqgnX7RKYfDgsRAA5bVeF0SSOyyP41bWWVkRTTtdUUSOeIuugE0aqX mOXQ== X-Gm-Message-State: AElRT7Fil6xUBxJwG2Q4ORvguhP6qxw2KfqQa5lNZg8waec6YtNdBEVm vFMLPTY5lMKsIljksrreFlDDgQ== X-Google-Smtp-Source: AIpwx4/uYc8y07dxgS8AQfqKk52rHqop+XFXsnIWiHivWQMR8NVqvZPTN8L40CJJWytPuJmwa5bCHg== X-Received: by 10.99.120.3 with SMTP id t3mr13832381pgc.56.1522911215623; Wed, 04 Apr 2018 23:53:35 -0700 (PDT) Received: from flat-canetoad.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id j11sm12608871pgs.13.2018.04.04.23.53.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Apr 2018 23:53:34 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 5 Apr 2018 16:53:20 +1000 Message-Id: <20180405065322.3647-1-oohall@gmail.com> X-Mailer: git-send-email 2.9.5 Subject: [Skiboot] [PATCH 1/3] core/pci: Set slot power limit when supported X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The PCIe slot capability can be implemented in a root or switch downstream port to set the maximum power a card is allowed to draw from the system. This patch adds support for setting the power limit when the platform has defined one. Signed-off-by: Oliver O'Halloran --- core/pci-slot.c | 1 + core/pci.c | 40 ++++++++++++++++++++++++++++++++++++++++ include/pci-slot.h | 1 + 3 files changed, 42 insertions(+) diff --git a/core/pci-slot.c b/core/pci-slot.c index 8bddc147e9d2..71d2769e710b 100644 --- a/core/pci-slot.c +++ b/core/pci-slot.c @@ -133,6 +133,7 @@ void pci_slot_add_dt_properties(struct pci_slot *slot, dt_add_property_cells(np, "ibm,slot-card-desc", slot->card_desc); dt_add_property_cells(np, "ibm,slot-card-mech", slot->card_mech); dt_add_property_cells(np, "ibm,slot-wired-lanes", slot->wired_lanes); + dt_add_property_cells(np, "ibm,power-limit", slot->power_limit); if (slot->ops.add_properties) slot->ops.add_properties(slot, np); diff --git a/core/pci.c b/core/pci.c index 3fc4854a3ed8..6d627a1e4db0 100644 --- a/core/pci.c +++ b/core/pci.c @@ -713,6 +713,43 @@ void pci_remove_bus(struct phb *phb, struct list_head *list) } } +static void pci_set_power_limit(struct pci_device *pd) +{ + uint32_t offset, val; + uint16_t caps; + + offset = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false); + if (!offset) { + PCIERR(pd->phb, pd->bdfn, "Legacy dev?\n"); + return; /* legacy dev */ + } + + pci_cfg_read16(pd->phb, pd->bdfn, + offset + PCICAP_EXP_CAPABILITY_REG, &caps); + if (!(caps & PCICAP_EXP_CAP_SLOT)) { + PCIERR(pd->phb, pd->bdfn, "slot cap missing?\n"); + return; /* bridge has no slot capabilities */ + } + + if (!pd->slot || !pd->slot->power_limit) { + PCIERR(pd->phb, pd->bdfn, "slot information missing!!!\n"); + return; + } + + pci_cfg_read32(pd->phb, pd->bdfn, offset + PCICAP_EXP_SLOTCAP, &val); + + val = SETFIELD(PCICAP_EXP_SLOTCAP_SPLSC, val, 0); /* 1W scale */ + val = SETFIELD(PCICAP_EXP_SLOTCAP_SPLVA, val, pd->slot->power_limit); + + pci_cfg_write32(pd->phb, pd->bdfn, offset + PCICAP_EXP_SLOTCAP, val); + + /* update the cached copy in the slot */ + pd->slot->slot_cap = val; + + PCIERR(pd->phb, pd->bdfn, "Slot power limit set to %dW\n", + pd->slot->power_limit); +} + /* Perform a recursive scan of the bus at bus_number populating * the list passed as an argument. This also performs the bus * numbering, so it returns the largest bus number that was @@ -847,6 +884,9 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus, /* Clear up bridge resources */ pci_cleanup_bridge(phb, pd); + /* set a slot power limit (if we have one) */ + pci_set_power_limit(pd); + /* Configure the bridge. This will enable power to the slot * if it's currently disabled, lift reset, etc... * diff --git a/include/pci-slot.h b/include/pci-slot.h index bb66d7c7f888..cd757535a470 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -169,6 +169,7 @@ struct pci_slot { uint8_t card_desc; uint8_t card_mech; uint8_t wired_lanes; + uint8_t power_limit; /* * PCI slot is driven by state machine with polling function. From patchwork Thu Apr 5 06:53:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 895287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40Gtpl2spdz9s0y for ; Thu, 5 Apr 2018 16:54:07 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NWuwbTLX"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40Gtpl1CQRzF1vy for ; Thu, 5 Apr 2018 16:54:07 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NWuwbTLX"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NWuwbTLX"; dkim-atps=neutral Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40GtpD0dyszDrnp for ; Thu, 5 Apr 2018 16:53:39 +1000 (AEST) Received: by mail-pl0-x241.google.com with SMTP id b6-v6so15873045pla.11 for ; Wed, 04 Apr 2018 23:53:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8jB4jY2AsnwRP5KkhnvhRMGHLq4o750IPag3gilUFyA=; b=NWuwbTLXAAoj0ZvRXlrDsJJyRzns0Ov/q4jHC7FQT93vVuUsJxa2O+eZz9SbkEw9dC ZXAzqbe7ZNdapcGKUtaiWlZ1avY1dfECMGbSmSTSz8t06Xu9GDR3sHnpDwtZinTERcUu 0fbtUwL122oFmGASUDyW7F/Lqf/imJ5ejgbfC4WrwRYH+znaEb2anG0Ii+o9MfTOocw8 ifu5z1B3w3biWadxXkJQ//G9JoevR1dfxmYfh+PzhYj7J6eSJQD/RHEp1RLDl4YOUzPG EBsS+9lSwTbSSzmCDWeiZ/pZvy5f38JgLVdhg/O3H1X4DrK8V5x6fvdnzEzPKYrF70K8 34Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8jB4jY2AsnwRP5KkhnvhRMGHLq4o750IPag3gilUFyA=; b=CpZyMWpVN/C4sVSU8J3J8Xu1Pa5JckWsOr4pO9J7x7LKRKq/bZRDrMr1xdDFpU2trk A3KCocRnW7/1M2iewIVHZh+0AF9NPsU0AbAxLAhk2J3aJmTNvPVQ65Px2O/Zuju1n+Op giK3589Dg+pWJILR/uvQbq2SbjcswPR6Ly9tcR2nw34Vf0SYCedogN54gt5PmrokSybb xgSn7YUmmdGND8tcfDw/EuaJBD40Ie8R251x5+vEtJF45B4Qgt9oNbzFd688Vlvoh6A2 brozlx4hby+I4OQQL8W6ngBGzI4R0hEj3WSY3jEzlah0RtIYuOXF6U/hJAvPF0o0+FT+ kV5Q== X-Gm-Message-State: AElRT7GBHuSkLct4+wFMICg4Ms9XGk5z6MIY3EFSmej0BjBZ3UyYS2gp oX9gzrjlzvLNOqw9+c/4/s9pgA== X-Google-Smtp-Source: AIpwx4/SdGzgVUdBMAGIoHidxxdLDdZz6ZX86xMm2z02xumtmVGVsC+QQJJ3qNL0ZolNHkYeLAht6A== X-Received: by 10.167.131.201 with SMTP id j9mr16273241pfn.214.1522911218250; Wed, 04 Apr 2018 23:53:38 -0700 (PDT) Received: from flat-canetoad.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id j11sm12608871pgs.13.2018.04.04.23.53.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Apr 2018 23:53:37 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 5 Apr 2018 16:53:21 +1000 Message-Id: <20180405065322.3647-2-oohall@gmail.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180405065322.3647-1-oohall@gmail.com> References: <20180405065322.3647-1-oohall@gmail.com> Subject: [Skiboot] [PATCH 2/3] phb4: Enable the PCIe slotcap on pluggable slots X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Enables reporting of slot status information, etc in the config space of the root complex. Currently this is only used to set the slot power limit in our generic PCI code, but we might use it for other things later on. Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 20 ++++++++++++++++++++ include/phb4-regs.h | 1 + 2 files changed, 21 insertions(+) diff --git a/hw/phb4.c b/hw/phb4.c index 06d2050f829b..c72f93330699 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -624,6 +624,8 @@ static int64_t phb4_get_reserved_pe_number(struct phb *phb) static void phb4_root_port_init(struct phb *phb, struct pci_device *dev, int ecap, int aercap) { + struct phb4 *p = phb_to_phb4(phb); + struct pci_slot *slot = dev->slot; uint16_t bdfn = dev->bdfn; uint16_t val16; uint32_t val32; @@ -639,6 +641,24 @@ static void phb4_root_port_init(struct phb *phb, struct pci_device *dev, // FIXME: check recommended init values for phb4 + /* + * Enable the bridge slot capability in the root port's config + * space. This should probably be done *before* we start + * scanning config space, but we need a pci_device struct to + * exist before we do a slot lookup so *faaaaaaaaaaaaaart* + */ + if (slot && slot->pluggable && slot->power_limit) { + uint64_t val; + + val = in_be64(p->regs + PHB_PCIE_SCR); + val |= PHB_PCIE_SCR_SLOT_CAP; + out_be64(p->regs + PHB_PCIE_SCR, val); + + /* update the cached slotcap */ + pci_cfg_read32(phb, bdfn, ecap + PCICAP_EXP_SLOTCAP, + &slot->slot_cap); + } + /* Enable SERR and parity checking */ pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); val16 |= (PCI_CFG_CMD_SERR_EN | PCI_CFG_CMD_PERR_RESP | diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 16a1a7405720..3f87ddcdcac8 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -267,6 +267,7 @@ // FIXME add more here #define PHB_PCIE_SCR 0x1A00 +#define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32,35) From patchwork Thu Apr 5 06:53:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 895288 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40Gtq15yMMz9s0y for ; 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Wed, 04 Apr 2018 23:53:40 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 5 Apr 2018 16:53:22 +1000 Message-Id: <20180405065322.3647-3-oohall@gmail.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180405065322.3647-1-oohall@gmail.com> References: <20180405065322.3647-1-oohall@gmail.com> Subject: [Skiboot] [PATCH 3/3] slots: Add power limit support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add support for sourcing power limit information from either the DT slot heirachy or the slot table. Signed-off-by: Oliver O'Halloran --- platforms/astbmc/astbmc.h | 1 + platforms/astbmc/slots.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/platforms/astbmc/astbmc.h b/platforms/astbmc/astbmc.h index feaca1d011d4..36ebe45dbb71 100644 --- a/platforms/astbmc/astbmc.h +++ b/platforms/astbmc/astbmc.h @@ -39,6 +39,7 @@ struct slot_table_entry { uint32_t location; const char *name; const struct slot_table_entry *children; + uint8_t power_limit; }; /* diff --git a/platforms/astbmc/slots.c b/platforms/astbmc/slots.c index 19b82fdd8c61..5c0effd1689c 100644 --- a/platforms/astbmc/slots.c +++ b/platforms/astbmc/slots.c @@ -121,6 +121,7 @@ void slot_table_get_slot_info(struct phb *phb, struct pci_device *pd) slot->pluggable = !!(ent->etype == st_pluggable_slot); slot->ops.add_properties = slot_table_add_properties; + slot->power_limit = ent->power_limit; slot->data = (void *)ent; } @@ -141,6 +142,7 @@ void dt_slot_get_slot_info(struct phb *phb, struct pci_device *pd) struct dt_node *slot_np; struct pci_slot *slot; const char *name = NULL; + uint32_t power_limit = 0; bool pluggable = false; if (!pd || pd->slot) @@ -150,6 +152,8 @@ void dt_slot_get_slot_info(struct phb *phb, struct pci_device *pd) if (slot_np) { pluggable = dt_has_node_property(slot_np, "ibm,pluggable", NULL); + power_limit = dt_prop_get_u32_def(slot_np, + "ibm,power-limit", 0); name = dt_prop_get_def(slot_np, "ibm,slot-label", NULL); } @@ -169,6 +173,7 @@ void dt_slot_get_slot_info(struct phb *phb, struct pci_device *pd) slot->ops.add_properties = dt_slot_add_properties; slot->pluggable = pluggable; + slot->power_limit = power_limit; slot->data = (void *)slot_np; }