From patchwork Thu Sep 14 11:33:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1834162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=JwDDobdG; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RmZx00CZ7z1yhd for ; Thu, 14 Sep 2023 21:34:44 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qgkb9-0000kI-Rz; Thu, 14 Sep 2023 07:33:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qgkb5-0000h0-8k for qemu-devel@nongnu.org; Thu, 14 Sep 2023 07:33:23 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qgkb1-000829-Bd for qemu-devel@nongnu.org; Thu, 14 Sep 2023 07:33:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694691198; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kbuF+g1FjxuOcbVTKhy2Mky4MOIcfRtu8c/CwwAuRwE=; b=JwDDobdGUCi3XEKGHOg6dLPsee9yQEdTKCXvKqdbrIs9pIM3nzqQs+7AyVizimZy4kaEyu DItOTV7E46NcgSxJXBzyi8HDxtO8m7P3JICwa8EQJm/Mg61GpHIBccui/xwcdR5nUKfcuS I7gR+7Wsjb3pKXjph9YLR6xnah0qr2g= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-167-HrkBKEnqO4m4Sqk56xTlIg-1; Thu, 14 Sep 2023 07:33:16 -0400 X-MC-Unique: HrkBKEnqO4m4Sqk56xTlIg-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id F3A1A802E5A; Thu, 14 Sep 2023 11:33:14 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.193.62]) by smtp.corp.redhat.com (Postfix) with ESMTP id E97711054FC0; Thu, 14 Sep 2023 11:33:13 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Ilya Leoshkevich Subject: [risu PATCH v3 1/7] Pass siginfo_t->si_addr to the reginfo_init() function Date: Thu, 14 Sep 2023 13:33:05 +0200 Message-ID: <20230914113311.379537-2-thuth@redhat.com> In-Reply-To: <20230914113311.379537-1-thuth@redhat.com> References: <20230914113311.379537-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On s390x, we need the si_addr from the siginfo_t to get to the address of the illegal instruction (the PSW address in the ucontext_t is already pointing to the next instruction there). So let's prepare for that situation and pass the si_addr to the reginfo_init() function everywhere. Signed-off-by: Thomas Huth --- risu.c | 12 ++++++------ risu.h | 2 +- risu_reginfo_aarch64.c | 2 +- risu_reginfo_arm.c | 2 +- risu_reginfo_i386.c | 2 +- risu_reginfo_loongarch64.c | 2 +- risu_reginfo_m68k.c | 2 +- risu_reginfo_ppc64.c | 2 +- 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/risu.c b/risu.c index 714074e..36fc82a 100644 --- a/risu.c +++ b/risu.c @@ -106,14 +106,14 @@ static void respond(RisuResult r) } } -static RisuResult send_register_info(void *uc) +static RisuResult send_register_info(void *uc, void *siaddr) { uint64_t paramreg; RisuResult res; RisuOp op; void *extra; - reginfo_init(&ri[MASTER], uc); + reginfo_init(&ri[MASTER], uc, siaddr); op = get_risuop(&ri[MASTER]); /* Write a header with PC/op to keep in sync */ @@ -178,7 +178,7 @@ static void master_sigill(int sig, siginfo_t *si, void *uc) RisuResult r; signal_count++; - r = send_register_info(uc); + r = send_register_info(uc, si->si_addr); if (r == RES_OK) { advance_pc(uc); } else { @@ -232,13 +232,13 @@ static RisuResult recv_register_info(struct reginfo *ri) } } -static RisuResult recv_and_compare_register_info(void *uc) +static RisuResult recv_and_compare_register_info(void *uc, void *siaddr) { uint64_t paramreg; RisuResult res; RisuOp op; - reginfo_init(&ri[APPRENTICE], uc); + reginfo_init(&ri[APPRENTICE], uc, siaddr); res = recv_register_info(&ri[MASTER]); if (res != RES_OK) { @@ -315,7 +315,7 @@ static void apprentice_sigill(int sig, siginfo_t *si, void *uc) RisuResult r; signal_count++; - r = recv_and_compare_register_info(uc); + r = recv_and_compare_register_info(uc, si->si_addr); if (r == RES_OK) { advance_pc(uc); } else { diff --git a/risu.h b/risu.h index bdb70c1..2c43384 100644 --- a/risu.h +++ b/risu.h @@ -115,7 +115,7 @@ RisuOp get_risuop(struct reginfo *ri); uintptr_t get_pc(struct reginfo *ri); /* initialize structure from a ucontext */ -void reginfo_init(struct reginfo *ri, ucontext_t *uc); +void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr); /* return 1 if structs are equal, 0 otherwise. */ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2); diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index be47980..1244454 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -82,7 +82,7 @@ int reginfo_size(struct reginfo *ri) } /* reginfo_init: initialize with a ucontext */ -void reginfo_init(struct reginfo *ri, ucontext_t *uc) +void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr) { int i; struct _aarch64_ctx *ctx, *extra = NULL; diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c index 202120b..85a39ac 100644 --- a/risu_reginfo_arm.c +++ b/risu_reginfo_arm.c @@ -118,7 +118,7 @@ static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc) } } -void reginfo_init(struct reginfo *ri, ucontext_t *uc) +void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr) { memset(ri, 0, sizeof(*ri)); /* necessary for memcmp later */ diff --git a/risu_reginfo_i386.c b/risu_reginfo_i386.c index e9730be..834b2ed 100644 --- a/risu_reginfo_i386.c +++ b/risu_reginfo_i386.c @@ -102,7 +102,7 @@ static void *xsave_feature_buf(struct _xstate *xs, int feature) } /* reginfo_init: initialize with a ucontext */ -void reginfo_init(struct reginfo *ri, ucontext_t *uc) +void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr) { int i, nvecregs; struct _fpstate *fp; diff --git a/risu_reginfo_loongarch64.c b/risu_reginfo_loongarch64.c index af6ab77..16384f1 100644 --- a/risu_reginfo_loongarch64.c +++ b/risu_reginfo_loongarch64.c @@ -81,7 +81,7 @@ static int parse_extcontext(struct sigcontext *sc, struct extctx_layout *extctx) } /* reginfo_init: initialize with a ucontext */ -void reginfo_init(struct reginfo *ri, ucontext_t *context) +void reginfo_init(struct reginfo *ri, ucontext_t *context, void *siaddr) { int i; struct ucontext *uc = (struct ucontext *)context; diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c index 4c25e77..e29da84 100644 --- a/risu_reginfo_m68k.c +++ b/risu_reginfo_m68k.c @@ -33,7 +33,7 @@ int reginfo_size(struct reginfo *ri) } /* reginfo_init: initialize with a ucontext */ -void reginfo_init(struct reginfo *ri, ucontext_t *uc) +void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr) { int i; memset(ri, 0, sizeof(*ri)); diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 9899b36..bbdd63c 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -42,7 +42,7 @@ int reginfo_size(struct reginfo *ri) } /* reginfo_init: initialize with a ucontext */ -void reginfo_init(struct reginfo *ri, ucontext_t *uc) +void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr) { int i; From patchwork Thu Sep 14 11:33:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1834169 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 14 Sep 2023 07:33:16 -0400 X-MC-Unique: ntSrBGGOPFOdBuupFRSOzg-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5404B800D8E; Thu, 14 Sep 2023 11:33:16 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.193.62]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4844B1054FC1; Thu, 14 Sep 2023 11:33:15 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Ilya Leoshkevich Subject: [risu PATCH v3 2/7] s390x: Add basic s390x support to the C code Date: Thu, 14 Sep 2023 13:33:06 +0200 Message-ID: <20230914113311.379537-3-thuth@redhat.com> In-Reply-To: <20230914113311.379537-1-thuth@redhat.com> References: <20230914113311.379537-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org With these changes, it is now possible to compile the "risu" binary for s390x hosts. Signed-off-by: Thomas Huth --- risu_reginfo_s390x.c | 140 +++++++++++++++++++++++++++++++++++++++++++ risu_reginfo_s390x.h | 25 ++++++++ risu_s390x.c | 51 ++++++++++++++++ test_s390x.S | 53 ++++++++++++++++ 4 files changed, 269 insertions(+) create mode 100644 risu_reginfo_s390x.c create mode 100644 risu_reginfo_s390x.h create mode 100644 risu_s390x.c create mode 100644 test_s390x.S diff --git a/risu_reginfo_s390x.c b/risu_reginfo_s390x.c new file mode 100644 index 0000000..3fd91b9 --- /dev/null +++ b/risu_reginfo_s390x.c @@ -0,0 +1,140 @@ +/****************************************************************************** + * Copyright 2023 Red Hat Inc. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Thomas Huth - initial implementation + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include "risu.h" +#include "risu_reginfo_s390x.h" + + +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} + +void arch_init(void) +{ +} + +int reginfo_size(struct reginfo *ri) +{ + return sizeof(*ri); +} + +/* reginfo_init: initialize with a ucontext */ +void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr) +{ + struct ucontext_extended *uce = (struct ucontext_extended *)uc; + + memset(ri, 0, sizeof(*ri)); + + /* + * We can get the size of the instruction by looking at the + * first two bits of the instruction + */ + switch (*(uint8_t *)siaddr >> 6) { + case 0: + ri->faulting_insn = *(uint16_t *)siaddr; + ri->faulting_insn_len = 2; + break; + case 3: + ri->faulting_insn = ((*(uint32_t *)siaddr) << 16) + | *(uint16_t *)(siaddr + 4); + ri->faulting_insn_len = 6; + break; + default: + ri->faulting_insn = *(uint32_t *)siaddr; + ri->faulting_insn_len = 4; + } + + ri->psw_mask = uce->uc_mcontext.regs.psw.mask; + ri->pc_offset = (uintptr_t)siaddr - image_start_address; + + memcpy(ri->gprs, uce->uc_mcontext.regs.gprs, sizeof(ri->gprs)); + + ri->fpc = uc->uc_mcontext.fpregs.fpc; + memcpy(ri->fprs, &uc->uc_mcontext.fpregs.fprs, sizeof(ri->fprs)); +} + +/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ +int reginfo_is_eq(struct reginfo *m, struct reginfo *a) +{ + return m->pc_offset == a->pc_offset && + m->fpc == a->fpc && + memcmp(m->gprs, a->gprs, sizeof(m->gprs)) == 0 && + memcmp(&m->fprs, &a->fprs, sizeof(m->fprs)) == 0; +} + +/* reginfo_dump: print state to a stream, returns nonzero on success */ +int reginfo_dump(struct reginfo *ri, FILE * f) +{ + int i; + + fprintf(f, " faulting insn 0x%" PRIx64 "\n", ri->faulting_insn); + fprintf(f, " PSW mask 0x%" PRIx64 "\n", ri->psw_mask); + fprintf(f, " PC offset 0x%" PRIx64 "\n\n", ri->pc_offset); + + for (i = 0; i < 16/2; i++) { + fprintf(f, "\tr%d: %16lx\tr%02d: %16lx\n", i, ri->gprs[i], + i + 8, ri->gprs[i + 8]); + } + fprintf(f, "\n"); + + for (i = 0; i < 16/2; i++) { + fprintf(f, "\tf%d: %16lx\tf%02d: %16lx\n", + i, *(uint64_t *)&ri->fprs[i], + i + 8, *(uint64_t *)&ri->fprs[i + 8]); + } + fprintf(f, "\tFPC: %8x\n\n", ri->fpc); + + return !ferror(f); +} + +int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f) +{ + int i; + + if (m->pc_offset != a->pc_offset) { + fprintf(f, "Mismatch: PC offset master: [%016lx] - PC offset apprentice: [%016lx]\n", + m->pc_offset, a->pc_offset); + } + + for (i = 0; i < 16; i++) { + if (m->gprs[i] != a->gprs[i]) { + fprintf(f, "Mismatch: r%d master: [%016lx] - r%d apprentice: [%016lx]\n", + i, m->gprs[i], i, a->gprs[i]); + } + } + + for (i = 0; i < 16; i++) { + if (*(uint64_t *)&m->fprs[i] != *(uint64_t *)&a->fprs[i]) { + fprintf(f, "Mismatch: f%d master: [%016lx] - f%d apprentice: [%016lx]\n", + i, *(uint64_t *)&m->fprs[i], + i, *(uint64_t *)&a->fprs[i]); + } + } + + if (m->fpc != a->fpc) { + fprintf(f, "Mismatch: FPC master: [%08x] - FPC apprentice: [%08x]\n", + m->fpc, a->fpc); + } + + return !ferror(f); +} diff --git a/risu_reginfo_s390x.h b/risu_reginfo_s390x.h new file mode 100644 index 0000000..c65fff7 --- /dev/null +++ b/risu_reginfo_s390x.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * Copyright 2023 Red Hat Inc. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Thomas Huth - initial implementation + *****************************************************************************/ + +#ifndef RISU_REGINFO_S390X_H +#define RISU_REGINFO_S390X_H + +struct reginfo { + uint64_t psw_mask; + uint64_t pc_offset; + uint64_t faulting_insn; + int faulting_insn_len; + uint32_t fpc; + uint64_t gprs[16]; + uint64_t fprs[16]; +}; + +#endif /* RISU_REGINFO_S390X_H */ diff --git a/risu_s390x.c b/risu_s390x.c new file mode 100644 index 0000000..cf9c72c --- /dev/null +++ b/risu_s390x.c @@ -0,0 +1,51 @@ +/****************************************************************************** + * Copyright 2023 Red Hat Inc. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Thomas Huth - initial implementation + *****************************************************************************/ + +#include + +#include "risu.h" + +void advance_pc(void *vuc) +{ + /* + * Note: The PSW address already points to the next instruction + * after we get a SIGILL, so we must not advance it here! + */ +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + ucontext_t *uc = vuc; + uc->uc_mcontext.gregs[0] = value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->gprs[0]; +} + +RisuOp get_risuop(struct reginfo *ri) +{ + uint32_t insn = ri->faulting_insn; + uint32_t op = insn & 0xff; + uint32_t key = insn & ~0xff; + + if (ri->faulting_insn_len == 4 && key == 0x835a0f00) { + return op; + } + + return OP_SIGILL; +} + +uintptr_t get_pc(struct reginfo *ri) +{ + return ri->pc_offset; +} diff --git a/test_s390x.S b/test_s390x.S new file mode 100644 index 0000000..16f3c6f --- /dev/null +++ b/test_s390x.S @@ -0,0 +1,53 @@ +/***************************************************************************** + * Copyright 2023 Red Hat Inc. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Thomas Huth - initial implementation + *****************************************************************************/ + + /* Initialise the general purpose registers */ + lgfi %r0, 0 + lgfi %r1, 0x1111111 + lgfi %r2, 0x2222222 + lgfi %r3, 0x3333333 + lgfi %r4, 0x4444444 + lgfi %r5, 0x5555555 + lgfi %r6, 0x6666666 + lgfi %r7, 0x7777777 + lgfi %r8, 0x8888888 + lgfi %r9, 0x9999999 + lgfi %r10, 0xaaaaaaa + lgfi %r11, 0xbbbbbbb + lgfi %r12, 0xccccccc + lgfi %r13, 0xddddddd + lgfi %r14, 0xeeeeeee + lgfi %r15, 0xfffffff + + /* Initialize floating point registers */ + ldgr %f0,%r0 + ldgr %f1,%r1 + ldgr %f2,%r2 + ldgr %f3,%r3 + ldgr %f4,%r4 + ldgr %f5,%r5 + ldgr %f6,%r6 + ldgr %f7,%r7 + ldgr %f8,%r8 + ldgr %f9,%r9 + ldgr %f10,%r10 + ldgr %f11,%r11 + ldgr %f12,%r12 + ldgr %f13,%r13 + ldgr %f14,%r14 + ldgr %f15,%r15 + + /* do compare */ + .int 0x835a0f00 + nop + + /* exit test */ + .int 0x835a0f01 From patchwork Thu Sep 14 11:33:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1834164 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=Vy0hqOkV; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RmZx35w8cz1yhd for ; Thu, 14 Sep 2023 21:34:47 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qgkb8-0000j9-4M; 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Thu, 14 Sep 2023 07:33:18 -0400 X-MC-Unique: rKNr3pE_M-KJf45hnRwfyA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9F7D8857A9C; Thu, 14 Sep 2023 11:33:17 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.193.62]) by smtp.corp.redhat.com (Postfix) with ESMTP id 95CF81054FC1; Thu, 14 Sep 2023 11:33:16 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Ilya Leoshkevich Subject: [risu PATCH v3 3/7] s390x: Add simple s390x.risu file Date: Thu, 14 Sep 2023 13:33:07 +0200 Message-ID: <20230914113311.379537-4-thuth@redhat.com> In-Reply-To: <20230914113311.379537-1-thuth@redhat.com> References: <20230914113311.379537-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This only adds a limited set of s390x instructions for initial testing. More instructions will be added later. Signed-off-by: Thomas Huth --- s390x.risu | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 s390x.risu diff --git a/s390x.risu b/s390x.risu new file mode 100644 index 0000000..1661be6 --- /dev/null +++ b/s390x.risu @@ -0,0 +1,81 @@ +############################################################################### +# Copyright 2023 Red Hat Inc. +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Thomas Huth - initial implementation +############################################################################### + +.mode s390x + +# format:RR Add (register + register, 32 bit) +AR Z 00011010 r1:4 r2:4 + +# format:RRE Add (register + register, 64 bit) +AGR Z 10111001 00001000 00000000 r1:4 r2:4 + +# format:RRE Add (register + register, 32 bit to 64 bit) +AGFR Z 10111001 00011000 00000000 r1:4 r2:4 + +# format:RRF-a Add (three registers, 32 bit) +ARK STFLE45 10111001 11111000 r3:4 0000 r1:4 r2:4 + +# format:RRF-a Add (three registers, 64 bit) +AGRK STFLE45 10111001 11101000 r3:4 0000 r1:4 r2:4 + + +# format:RRE Add Halfword Immediate (32 bit) +AHI Z 10100111 r1:4 1010 i2:16 + +# format:RI Add Halfword Immediate (64 bit) +AGHI Z 10100111 r1:4 1011 i2:16 + + +# format:RR Add Logical (32 bit) +ALR Z 00011110 r1:4 r2:4 + +# format:RRE Add Logical (64 bit) +ALGR Z 10111001 00001010 00000000 r1:4 r2:4 + +# format:RRE Add Logical (32 bit to 64 bit) +ALGFR Z 10111001 00011010 00000000 r1:4 r2:4 + + +# format:RRF-c Population Count +POPCNT STFLE45 10111001 11100001 m3:4 0000 r1:4 r2:4 + + +###### Binary floating point instructions ###### + +# format:RRE ADD (short BFP) +AEBR BFP 10110011 00001010 00000000 r1:4 r2:4 + +# format:RRE ADD (long BFP) +ADBR BFP 10110011 00011010 00000000 r1:4 r2:4 + +# format:RRE ADD (extended BFP) +AXBR BFP 10110011 01001010 00000000 r1:4 r2:4 + + +# format:RRE COMPARE (short BFP) +CEBR BFP 10110011 00001001 00000000 r1:4 r2:4 + +# format:RRE COMPARE (long BFP) +CDBR BFP 10110011 00011001 00000000 r1:4 r2:4 + +# format:RRE COMPARE (extended BFP) +CXBR BFP 10110011 01001001 00000000 r1:4 r2:4 + + +# format:RRF-e LOAD FP INTEGER (short BFP) +FIEBRA BFP 10110011 01010111 m3:4 m4:4 r1:4 r2:4 + +# format:RRF-e LOAD FP INTEGER (long BFP) +FIDBRA BFP 10110011 01011111 m3:4 m4:4 r1:4 r2:4 + +# format:RRF-e LOAD FP INTEGER (extended BFP) +FIXBRA BFP 10110011 01000111 m3:4 m4:4 r1:4 r2:4 + From patchwork Thu Sep 14 11:33:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1834163 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=JwYB5ZUo; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RmZx03km7z1yhn for ; Thu, 14 Sep 2023 21:34:44 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qgkb9-0000kK-Tl; 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Thu, 14 Sep 2023 07:33:19 -0400 X-MC-Unique: iT6Tk-zeNnazWE9txJtVsQ-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id F2B78857A9D; Thu, 14 Sep 2023 11:33:18 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.193.62]) by smtp.corp.redhat.com (Postfix) with ESMTP id E33D21054FC0; Thu, 14 Sep 2023 11:33:17 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Ilya Leoshkevich Subject: [risu PATCH v3 4/7] s390x: Add basic risugen perl module for s390x Date: Thu, 14 Sep 2023 13:33:08 +0200 Message-ID: <20230914113311.379537-5-thuth@redhat.com> In-Reply-To: <20230914113311.379537-1-thuth@redhat.com> References: <20230914113311.379537-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This implements support for simple 16-bit and 32-bit instructions. Support for 48-bit instructions and support for load/store memory instructions is not implemented yet. Signed-off-by: Thomas Huth --- risugen_s390x.pm | 186 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 risugen_s390x.pm diff --git a/risugen_s390x.pm b/risugen_s390x.pm new file mode 100644 index 0000000..260e2dd --- /dev/null +++ b/risugen_s390x.pm @@ -0,0 +1,186 @@ +#!/usr/bin/perl -w +############################################################################### +# Copyright 2023 Red Hat Inc. +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Thomas Huth - initial implementation (based on risugen_ppc64.pm etc.) +############################################################################### + +# risugen -- generate a test binary file for use with risu +# See 'risugen --help' for usage information. +package risugen_s390x; + +use strict; +use warnings; + +use risugen_common; + +require Exporter; + +our @ISA = qw(Exporter); +our @EXPORT = qw(write_test_code); + +my $periodic_reg_random = 1; + +# Maximum alignment restriction permitted for a memory op. +my $MAXALIGN = 64; + +sub write_mov_ri($$$) +{ + my ($r, $imm_h, $imm_l) = @_; + + # LGFI + insn16(0xc0 << 8 | $r << 4 | 0x1); + insn32($imm_l); + # IIHF r,imm_high + insn16(0xc0 << 8 | $r << 4 | 0x8); + insn32($imm_h); +} + +sub write_mov_fp($$) +{ + my ($r, $imm) = @_; + + write_mov_ri(0, ~$imm, $imm); + # LDGR + insn32(0xb3c1 << 16 | $r << 4); +} + +sub write_random_regdata() +{ + # Floating point registers + for (my $i = 0; $i < 16; $i++) { + write_mov_fp($i, rand(0xffffffff)); + } + + # Load FPC (via r0) + write_mov_ri(0, 0, (rand(0xffffffff) & 0x00fcff77)); + insn32(0xb3840000); + + # general purpose registers + for (my $i = 0; $i < 16; $i++) { + write_mov_ri($i, rand(0xffffffff), rand(0xffffffff)); + } +} + +my $OP_COMPARE = 0; # compare registers +my $OP_TESTEND = 1; # end of test, stop + +sub write_random_register_data() +{ + write_random_regdata(); + write_risuop($OP_COMPARE); +} + +sub gen_one_insn($$) +{ + # Given an instruction-details array, generate an instruction + my $constraintfailures = 0; + + INSN: while(1) { + my ($forcecond, $rec) = @_; + my $insn = int(rand(0xffffffff)); + my $insnname = $rec->{name}; + my $insnwidth = $rec->{width}; + my $fixedbits = $rec->{fixedbits}; + my $fixedbitmask = $rec->{fixedbitmask}; + my $constraint = $rec->{blocks}{"constraints"}; + my $memblock = $rec->{blocks}{"memory"}; + + $insn &= ~$fixedbitmask; + $insn |= $fixedbits; + + if (defined $constraint) { + # user-specified constraint: evaluate in an environment + # with variables set corresponding to the variable fields. + my $v = eval_with_fields($insnname, $insn, $rec, "constraints", $constraint); + if (!$v) { + $constraintfailures++; + if ($constraintfailures > 10000) { + print "10000 consecutive constraint failures for $insnname constraints string:\n$constraint\n"; + exit (1); + } + next INSN; + } + } + + # OK, we got a good one + $constraintfailures = 0; + + my $basereg; + + if (defined $memblock) { + die "memblock handling has not been implemented yet." + } + + if ($insnwidth == 16) { + insn16(($insn >> 16) & 0xffff); + } else { + insn32($insn); + } + + return; + } +} + +sub write_risuop($) +{ + my ($op) = @_; + insn32(0x835a0f00 | $op); +} + +sub write_test_code($) +{ + my ($params) = @_; + + my $condprob = $params->{ 'condprob' }; + my $numinsns = $params->{ 'numinsns' }; + my $outfile = $params->{ 'outfile' }; + + my %insn_details = %{ $params->{ 'details' } }; + my @keys = @{ $params->{ 'keys' } }; + + set_endian(1); + + open_bin($outfile); + + # convert from probability that insn will be conditional to + # probability of forcing insn to unconditional + $condprob = 1 - $condprob; + + # TODO better random number generator? + srand(0); + + print "Generating code using patterns: @keys...\n"; + progress_start(78, $numinsns); + + if (grep { defined($insn_details{$_}->{blocks}->{"memory"}) } @keys) { + write_memblock_setup(); + } + + # memblock setup doesn't clean its registers, so this must come afterwards. + write_random_register_data(); + + for my $i (1..$numinsns) { + my $insn_enc = $keys[int rand (@keys)]; + #dump_insn_details($insn_enc, $insn_details{$insn_enc}); + my $forcecond = (rand() < $condprob) ? 1 : 0; + gen_one_insn($forcecond, $insn_details{$insn_enc}); + write_risuop($OP_COMPARE); + # Rewrite the registers periodically. This avoids the tendency + # for the VFP registers to decay to NaNs and zeroes. + if ($periodic_reg_random && ($i % 100) == 0) { + write_random_register_data(); + } + progress_update($i); + } + write_risuop($OP_TESTEND); + progress_end(); + close_bin(); +} + +1; From patchwork Thu Sep 14 11:33:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1834166 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=c1DHVkmz; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RmZxP39sKz1yh0 for ; Thu, 14 Sep 2023 21:35:05 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qgkbC-0000lg-Aq; Thu, 14 Sep 2023 07:33:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qgkb8-0000jO-8Z for qemu-devel@nongnu.org; Thu, 14 Sep 2023 07:33:27 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qgkb6-00086y-Mf for qemu-devel@nongnu.org; Thu, 14 Sep 2023 07:33:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694691204; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c3brwRM26pCnGBxawE6Oh1yi2m+jFgMUL7ymoQKyt1A=; b=c1DHVkmzZRqEW+mKTZZYqiTIH1ootRyY5sxO4qO+IUhm7jIVhZNXA67KT38rBWeCHeAVYo GH94lmdp6GgxpHObLYmCDyUE28DyRAWva120mRIdt1o6M97zCZnQQuHnVcDWoFoTHFa3EW vT9iTkcEdVpP86yvkcrbic5DQlLbBH4= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-516-Qcc3YaZ5ObmAGS25O-ku9A-1; Thu, 14 Sep 2023 07:33:20 -0400 X-MC-Unique: Qcc3YaZ5ObmAGS25O-ku9A-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 55AA68057BF; Thu, 14 Sep 2023 11:33:20 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.193.62]) by smtp.corp.redhat.com (Postfix) with ESMTP id 422481054FC0; Thu, 14 Sep 2023 11:33:19 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Ilya Leoshkevich Subject: [risu PATCH v3 5/7] s390x: Update the configure script for s390x support Date: Thu, 14 Sep 2023 13:33:09 +0200 Message-ID: <20230914113311.379537-6-thuth@redhat.com> In-Reply-To: <20230914113311.379537-1-thuth@redhat.com> References: <20230914113311.379537-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Auto-detect s390x hosts and add s390x information to the help text. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- configure | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configure b/configure index ca2d7db..2f7c580 100755 --- a/configure +++ b/configure @@ -58,6 +58,8 @@ guess_arch() { ARCH="m68k" elif check_define __powerpc64__ ; then ARCH="ppc64" + elif check_define __s390x__ ; then + ARCH="s390x" else echo "This cpu is not supported by risu. Try -h. " >&2 exit 1 @@ -139,7 +141,7 @@ Some influential environment variables: prefixed with the given string. ARCH force target architecture instead of trying to detect it. - Valid values=[arm|aarch64|ppc64|ppc64le|m68k] + Valid values=[arm|aarch64|m68k|ppc64|ppc64le|s390x] CC C compiler command CFLAGS C compiler flags From patchwork Thu Sep 14 11:33:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1834165 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=gwNkiboD; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RmZxL0dsXz1yhd for ; Thu, 14 Sep 2023 21:35:02 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qgkbC-0000mG-SF; Thu, 14 Sep 2023 07:33:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qgkbB-0000l0-4S for qemu-devel@nongnu.org; Thu, 14 Sep 2023 07:33:29 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qgkb9-00088x-NS for qemu-devel@nongnu.org; Thu, 14 Sep 2023 07:33:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694691206; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L+r5qzrhYvesklEk2YhZl0RS3GmsTkW23te839BKj8g=; b=gwNkiboDEUXEFv7GrfOU3o0ZsrnmJCDF52NYrixwducvr8c+I1HJiwIWXrxDr2ef1R6dbu 1FZnvvBzq4CNL2RMgmjTA+sCVFFHp0m4SMvquzUu7RzDYBiub5g7riERoZxQb9cLGgHnio rma6K4Zco8dSwYom6D4PkGI1dsf9uZ0= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-520-QCX6mu3CO6qJmnluRcR-2Q-1; Thu, 14 Sep 2023 07:33:22 -0400 X-MC-Unique: QCX6mu3CO6qJmnluRcR-2Q-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 97EC381B194; Thu, 14 Sep 2023 11:33:21 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.193.62]) by smtp.corp.redhat.com (Postfix) with ESMTP id 976961054FC2; Thu, 14 Sep 2023 11:33:20 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Ilya Leoshkevich Subject: [risu PATCH v3 6/7] build-all-archs: Add s390x to the script that builds all architectures Date: Thu, 14 Sep 2023 13:33:10 +0200 Message-ID: <20230914113311.379537-7-thuth@redhat.com> In-Reply-To: <20230914113311.379537-1-thuth@redhat.com> References: <20230914113311.379537-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org To avoid regressions, let's check s390x also via this file. Suggested-by: Peter Maydell Signed-off-by: Thomas Huth --- build-all-archs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/build-all-archs b/build-all-archs index e5dcfc8..e89851b 100755 --- a/build-all-archs +++ b/build-all-archs @@ -91,7 +91,8 @@ program_exists() { for triplet in i386-linux-gnu i686-linux-gnu x86_64-linux-gnu \ aarch64-linux-gnu arm-linux-gnueabihf \ m68k-linux-gnu \ - powerpc64le-linux-gnu powerpc64-linux-gnu ; do + powerpc64le-linux-gnu powerpc64-linux-gnu \ + s390x-linux-gnu ; do if ! program_exists "${triplet}-gcc"; then echo "Skipping ${triplet}: no compiler found" From patchwork Thu Sep 14 11:33:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 1834167 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=UX7hlUZG; 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Thu, 14 Sep 2023 11:33:22 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.193.62]) by smtp.corp.redhat.com (Postfix) with ESMTP id DBE671054FC3; Thu, 14 Sep 2023 11:33:21 +0000 (UTC) From: Thomas Huth To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Ilya Leoshkevich Subject: [risu RFC PATCH v3 7/7] Add a travis.yml file for testing RISU in the Travis-CI Date: Thu, 14 Sep 2023 13:33:11 +0200 Message-ID: <20230914113311.379537-8-thuth@redhat.com> In-Reply-To: <20230914113311.379537-1-thuth@redhat.com> References: <20230914113311.379537-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Travis-CI offers native build machines for aarch64, ppc64le and s390x, so this is very useful for testing RISU on these architectures. While compiling works fine for all architectures, running the binary currently only works for s390x (the aarch64 runner reports a mismatch when comparing the registers, and the ppc64le runner simply hangs), so we can only run the resulting binary on s390x right now. Signed-off-by: Thomas Huth --- Not sure if this is useful for anybody but me since Travis is not that popular anymore these days ... so please feel free to ignore this patch. .travis.yml | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 .travis.yml diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 0000000..bafa8df --- /dev/null +++ b/.travis.yml @@ -0,0 +1,37 @@ +dist: focal +language: c +compiler: + - gcc +addons: + apt: + packages: + - perl + - perl-modules + - liblist-compare-perl + +before_script: + - ./configure +script: + - set -e + - make -j2 + - ./risugen --numinsns 1000 ${ARCH}.risu ${ARCH}.bin + +matrix: + include: + + - env: + - ARCH="aarch64" + arch: arm64 + + - env: + - ARCH="ppc64" + arch: ppc64le + + - env: + - ARCH="s390x" + arch: s390x + after_script: + - ./risu --master ${ARCH}.bin > stdout.txt 2> stderr.txt & + - sleep 1 + - ./risu --host localhost ${ARCH}.bin + - cat stdout.txt stderr.txt