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[178.235.177.248]) by smtp.gmail.com with ESMTPSA id s3-20020a170906060300b0099ce188be7fsm6592053ejb.3.2023.09.12.03.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 03:04:49 -0700 (PDT) From: Konrad Dybcio Date: Tue, 12 Sep 2023 12:04:43 +0200 Subject: [PATCH v4 01/10] dt-bindings: display/msm/gmu: Add Adreno 7[34]0 GMU MIME-Version: 1.0 Message-Id: <20230628-topic-a7xx_drmmsm-v4-1-8b3e402795c1@linaro.org> References: <20230628-topic-a7xx_drmmsm-v4-0-8b3e402795c1@linaro.org> In-Reply-To: <20230628-topic-a7xx_drmmsm-v4-0-8b3e402795c1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694513085; l=2826; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HNK2SS799OXNh7iy5vESf+h2uwh6BGHa1r43G7UvIKE=; b=+aNhNRKwvuwrMdhWRTbxNVQkwFcWZURLyBD2mwRyP/wVP/eXlh+1jqsekzIPBXb7Jrz+oB2AW 9yvuwejWMdsBoppcj4wodblH7P/o/r0eUQ6Pxz7OycwtF0+lEdiYMWk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The GMU on the A7xx series is pretty much the same as on the A6xx parts. It's now "smarter", needs a bit less register writes and controls more things (like inter-frame power collapse) mostly internally (instead of us having to write to G[PM]U_[CG]X registers from APPS) The only difference worth mentioning is the now-required DEMET clock, which is strictly required for things like asserting reset lines, not turning it on results in GMU not being fully functional (all OOB requests would fail and HFI would hang after the first submitted OOB). Describe the A730 and A740 GMU. Reviewed-by: Krzysztof Kozlowski Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gmu.yaml | 40 +++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 5fc4106110ad..20ddb89a4500 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -21,7 +21,7 @@ properties: compatible: oneOf: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu - const: qcom,adreno-gmu-wrapper @@ -213,6 +213,44 @@ allOf: - const: axi - const: memnoc + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-730.1 + - qcom,adreno-gmu-740.1 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + - description: GPUSS DEMET clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: hub + - const: demet + - if: properties: compatible: From patchwork Tue Sep 12 10:04:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 1832834 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=kzbwkr3Z; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RlK2L5zxdz1yhm for ; Tue, 12 Sep 2023 20:04:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232287AbjILKFA (ORCPT ); Tue, 12 Sep 2023 06:05:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233628AbjILKE5 (ORCPT ); Tue, 12 Sep 2023 06:04:57 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF71FCC3 for ; Tue, 12 Sep 2023 03:04:52 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-9aa0495f9cfso780404766b.1 for ; Tue, 12 Sep 2023 03:04:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694513091; x=1695117891; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=76F0+BldbGsR8SBANuEdRlfBFJURUSsOZA3YGl1lILM=; b=kzbwkr3Z4Cecmq3sCp5OTxC/OuWF89fG/jgPYZatb8oFqiRmxMtX8muRme8DRFlAE3 2KpvAxu58uBhaviD0aGzCw+m0KbN+DYLHHbK4ygrhfyuFUe3ilBIW61mDOJqs+ouQPBa Rh9loEgrWS2KWNVFWFUtDn8sZXFs/MmMJTz1PB1p7n1m5Nqb1HNbSp1DLbjX46YAKEKK XMSAOeUBi+8AguPz/Q0fTPbC/8/3evtIyWad8rRm0WjwiW34odJJA7E5vr7s8MUdc+pn XIBM1wSJLKY2ap6coD/ZxrhvAQIf+HBP4Hp9x2G3IpF7bKzvZrplhKacIpcVh0F5wjOC UsVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694513091; x=1695117891; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=76F0+BldbGsR8SBANuEdRlfBFJURUSsOZA3YGl1lILM=; b=KL7ni659CPXxlVHcpecmC31Sr6xz957v/EgqBNc185DZCdKHVqHWJd2szsA0b2+Blb ZY7WF8Pwsq4n30rqU+2O2PjowcgJ36hx+caha7Nb3z86o3pBex+OBDyqI9i/MYYMdQQx Fwlg2TeSKMqx0Q8J1huyd4TtKrFbaBB2GNEjoE/oTTz1HVbACPtNq0xsOxzzZdvdLWN8 e6hAbYdIZEz1dn2ZztytH5v+KhZ2lWmvtJrvD1KvL4pWKEZQ+WEUL337nMXwNliBp2WC SuUHR2IBx+NJ9uP4rrCvCmuyFB+YmTSKDx7Q63YvIcMRh2kS853EX9yH+4p7GiZ64vI1 uMvg== X-Gm-Message-State: AOJu0YyZ1CVsvUvLaHEEyX//TGTdhDVoldw6fZDnC8EVVohV4jyBPUig fUmU0kKI3lXHOvlBHtCFsqLcTw== X-Google-Smtp-Source: AGHT+IFFTR7Me9GkF8TwPhcPBB1Y5s/bvb5Njy18q0t6j3M2sBcRZTcWLShIUmaBK5Yj95BzYsqQxA== X-Received: by 2002:a17:906:5a54:b0:9a2:26e4:a5e2 with SMTP id my20-20020a1709065a5400b009a226e4a5e2mr2847448ejc.25.1694513091507; Tue, 12 Sep 2023 03:04:51 -0700 (PDT) Received: from [10.167.154.1] (178235177248.dynamic-4-waw-k-1-1-0.vectranet.pl. [178.235.177.248]) by smtp.gmail.com with ESMTPSA id s3-20020a170906060300b0099ce188be7fsm6592053ejb.3.2023.09.12.03.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 03:04:51 -0700 (PDT) From: Konrad Dybcio Date: Tue, 12 Sep 2023 12:04:44 +0200 Subject: [PATCH v4 02/10] dt-bindings: display/msm/gmu: Allow passing QMP handle MIME-Version: 1.0 Message-Id: <20230628-topic-a7xx_drmmsm-v4-2-8b3e402795c1@linaro.org> References: <20230628-topic-a7xx_drmmsm-v4-0-8b3e402795c1@linaro.org> In-Reply-To: <20230628-topic-a7xx_drmmsm-v4-0-8b3e402795c1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694513085; l=1312; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=f8Ks5qBU/xHwVpGLbBaIcN6/JSh0hSEZ3lbJ3m6GXGI=; b=9i+f9omsQyT4L6anbqN+1N8xukVQtyzR1G/5cFpfCRAcXhunuhaQaBlVP9C3SF6hKNycjZwNi tSIY9XL7KOcASIQvJHIYdBcJDX5frjvV03WkZdMxQnt8Xz6ujKo2wvN X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When booting the GMU, the QMP mailbox should be pinged about some tunables (e.g. adaptive clock distribution state). To achieve that, a reference to it is necessary. Allow it and require it with A730. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 20ddb89a4500..e132dbff3c4a 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -64,6 +64,10 @@ properties: iommus: maxItems: 1 + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM + operating-points-v2: true opp-table: @@ -251,6 +255,9 @@ allOf: - const: hub - const: demet + required: + - qcom,qmp + - if: properties: compatible: From patchwork Tue Sep 12 10:04:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 1832835 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=f3eQLp5X; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RlK2R6rL4z1yhZ for ; Tue, 12 Sep 2023 20:05:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233768AbjILKFD (ORCPT ); Tue, 12 Sep 2023 06:05:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233709AbjILKE7 (ORCPT ); Tue, 12 Sep 2023 06:04:59 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E48C1BB for ; Tue, 12 Sep 2023 03:04:55 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-502b0d23f28so4225121e87.2 for ; Tue, 12 Sep 2023 03:04:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694513094; x=1695117894; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ir9r9aQtaSZLleag9LnQwnbzzTQdAeEYrkqtlWNxaqg=; b=f3eQLp5XtvCZZsHP+2VpuFiC6WaoOrgQ98rYqNFvmfYosuSIE/bFDksKWh3puxYj+e Qet7lt5FYS8wIXuc40D0NQ889Jl3mXuWFcHBbOkPMZPxIFmenifCqJFQcfbKNl55Xdfh wSrsg+AFK5Mx04T2eR1xURGvK3DBL+64dh70z2RyLqUWneVkbJg8lBECTrBjwz64cFbm yU2twaxyPih777WrFvykwBSiABide2uHOgwQW38lyXo7ezRBJeTrNPO4CzGKtUyz8KgG UEJp8auCeSCYQhYAI5jwSFmNRiXSjyDrjnaNBjjh0UhUKEd3auEdehGtMrqGduoZNSLa aLSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694513094; x=1695117894; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ir9r9aQtaSZLleag9LnQwnbzzTQdAeEYrkqtlWNxaqg=; b=tlDge7N9foUkQBYOicfXqLSSSmMx3SRsaRrRw9IzkH7lLEtZQ7NlaP6f2DPkkosTcs NFRqkcAFiIc+6RDfyCsz62xTa3GvnNx2Tq+Q7ZvgXTCrY0VGaqJanmDohIgJhoHvWJeV eX+3a2CvlwxiuKhfzz6kaek5EB1ehj8YFLGAOqybPTAq0gHhQwLoisxjtTW2pgIWA4Qe SyYtfvJFdDeiw3nw4iqAbsl6/YDp3lY5CYMCgAVaFLxReUMnozR3tYqGUAemaxAAe99x yY6WCCKduunC1fVw247uQhICGLXXSQRD5KHg/8KWFL3JmJvemHgSxOA+KGNICqKB5zYb evqg== X-Gm-Message-State: AOJu0YzOW2LY72agw0sReRxvQAXd988D2bBrQpYvFFpiUh7im6sk+H6m 27usBMsl5k12WOHnZMnHVjL6Lw== X-Google-Smtp-Source: AGHT+IHyp6bxGr08MxrJXgU77ALZhRoZWA9rEEteS0kLQHTL/Fi8nw8lQ98cVxST83ghnfxL5Qje9w== X-Received: by 2002:ac2:58cc:0:b0:4fb:c657:3376 with SMTP id u12-20020ac258cc000000b004fbc6573376mr8841228lfo.29.1694513093643; Tue, 12 Sep 2023 03:04:53 -0700 (PDT) Received: from [10.167.154.1] (178235177248.dynamic-4-waw-k-1-1-0.vectranet.pl. [178.235.177.248]) by smtp.gmail.com with ESMTPSA id s3-20020a170906060300b0099ce188be7fsm6592053ejb.3.2023.09.12.03.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 03:04:53 -0700 (PDT) From: Konrad Dybcio Date: Tue, 12 Sep 2023 12:04:45 +0200 Subject: [PATCH v4 03/10] dt-bindings: display/msm/gpu: Allow A7xx SKUs MIME-Version: 1.0 Message-Id: <20230628-topic-a7xx_drmmsm-v4-3-8b3e402795c1@linaro.org> References: <20230628-topic-a7xx_drmmsm-v4-0-8b3e402795c1@linaro.org> In-Reply-To: <20230628-topic-a7xx_drmmsm-v4-0-8b3e402795c1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694513085; l=1566; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=VV4z2afr+St9/dA+OjbMmt+l3E+tCjarurRFVAL3RG8=; b=RliuCnOaiDRBp0EAJeURYXdZIfXDaE/0Hi/yLzX875X7bJqTyIF8cUX7zT13ntDismvMkq/5O ZcwAX8tFscDD90Z+QqcOFVeoXJG4vjP25RgJa/AF/5uGNgL+FYrxftf X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends. They use GMU for all things DVFS, just like most A6xx GPUs. Reviewed-by: Krzysztof Kozlowski Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 56b9b247e8c2..b019db954793 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -23,7 +23,7 @@ properties: The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. items: - - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$' - const: qcom,adreno - description: | The driver is parsing the compat string for Imageon to @@ -203,7 +203,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$' then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: